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Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/var/vell: update gpio for DMIC
......................................................................
mb/google/brya/var/vell: update gpio for DMIC
Data on channel 0 & 1 are normal (from DMIC) but there are noise on channel 2 & 3, so change to NF
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF4) to PAD_NC(GPP_R6, NONE),
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF4) to PAD_NC(GPP_R7, NONE),
BUG=b:210802722
TEST=FW_NAME=vell emerge-brya coreboot
Change-Id: I1b5ccd2c239e526e4f1ce2d5ed6c1386303590c8
Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/vell/gpio.c
1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/61033/3
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Change subject: soc/intel/common/cse: Add `cse_send_end_of_post()` as a public function
......................................................................
Patch Set 10: Code-Review+1
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common/cse: Add `cse_send_end_of_post()` as a public function
......................................................................
soc/intel/common/cse: Add `cse_send_end_of_post()` as a public function
This patch creates a global function `cse_send_end_of_post()` so
that IA common code may get access to this function for sending EOP
command to the HECI1/CSE device.
Additionally, use static variable to track and prevent sending EOP
command more than once in boot flow.
BUG=b:211954778
TEST=Able to build and boot Brya.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I837c5723eca766d21b191b98e39eb52889498bfc
---
M src/soc/intel/common/block/cse/cse_eop.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 23 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/61519/10
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Change subject: second test
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Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61791 )
Change subject: Documentation: Add GSoC info page
......................................................................
Documentation: Add GSoC info page
Work in progress.
Initial site was copied from https://www.coreboot.org/GSoC.
Change-Id: I5c21d026118cba571dc6b817e89cc4da296a1799
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
A Documentation/contributing/gsoc.md
M Documentation/index.md
2 files changed, 218 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/61791/1
diff --git a/Documentation/contributing/gsoc.md b/Documentation/contributing/gsoc.md
new file mode 100644
index 0000000..26ac604
--- /dev/null
+++ b/Documentation/contributing/gsoc.md
@@ -0,0 +1,217 @@
+# Google Summer of Code
+
+coreboot is applying for Google Summer of Code 2017 as a mentoring organization. It
+is not assumed that we are accepted yet. We will announce this on the mailing list,
+chat.coreboot.org and update this page when we are informed on 27 February.
+
+coreboot has many Project Ideas for various ability levels. The coreboot project also
+acts as an umbrella organization for other open-source firmware related projects.
+
+Official student application period in 2017 is from March 20 to April 3, with results
+announced on April 4. For the complete timeline, please see the GSoC 2017 timeline.
+
+
+## coreboot contacts
+
+If you are interested in participating in GSoC as a student student, please visit
+chat.coreboot.org. Working closely with the community is highly encouraged, as we've
+seen that our most successful students are generally very involved.
+
+Patrick Georgi and Martin Roth are the coreboot GSoC admins for 2017. Please feel free
+to reach out to them directly if you have any questions.
+
+
+## Why work on coreboot for GSoC 2017?
+
+* coreboot offers you the opportunity to work with various architectures right on the
+iron. coreboot supports both current and older silicon for a wide variety of chips and
+technologies.
+
+* coreboot has a worldwide developer and user base.
+
+* We are a very passionate team, so you will interact directly with the project
+initiators and project leaders.
+
+* We have a large, helpful community. coreboot has some extremely talented and helpful
+experts in firmware involved in the project. They are ready to assist and mentor
+students participating in GSoC.
+
+* One of the last areas where open source software is not common is firmware. Running
+proprietary firmware can have severe effects on user's freedom and security. coreboot
+changes that by providing a common framework for initial hardware initialization and
+you can help us succeed.
+
+
+## GSoC Student requirements
+
+What will be required of you to be a coreboot GSoC student?
+
+Google Summer of Code is a full-time job. This means we expect you to work roughly 40
+hours per week on your project, during the three months of coding. Obviously we have
+flexibility, but if your schedule (exams, courses, other obligations) does not give
+you this amount of time, then you should not apply. We expect to be able to see this
+level of effort in student output.
+
+
+### Before applying
+
+* Prior to project acceptance, you have demonstrated that you can work with the
+coreboot codebase.
+
+ * By the time you have submitted your application, you should have downloaded, built
+ and booted coreboot in QEMU, SimNow, or on real hardware. Please email your serial
+ output results to the mailing list.
+
+ * Look over some of the development processes guidelines: git, Gerrit Etiquette and
+ Guidelines, Development Guidelines, and Developer Manual
+
+ * Get signed up for gerrit and push at least one patch to Gerrit for review. Check
+ Easy projects or ask for simple tasks on the mailing list or on chat.coreboot.org if
+ you need ideas.
+
+ * Look through some patches on gerrit to get an understanding of the review process
+ and common issues
+
+* Before applying, you should also join the mailing list and chat.coreboot.org.
+Introduce yourself and mention that you are a prospective GSoC student. Ask questions
+and discuss the project that you are considering. Community involvement is a key
+component of coreboot development.
+
+
+### During the program
+
+* To pass and to be paid by Google requires that you meet certain milestones.
+
+ * First, you must be in good standing with the community before the official start
+ of the program. We expect you to post some design emails to the mailing list, and
+ get feedback on them, both before applying, and during the "community bonding period"
+ between acceptance and official start.
+
+ * You must have made progress and committed significant code before the mid-term point
+ and by the final.
+
+ * We require that accepted students to maintain a blog, where you are expected to write
+ about your project *WEEKLY*. This is a way to measure progress and for the community at
+ large to be able to help you. GSoC is *NOT* a private contract between your mentor and
+ you. blogs.coreboot.org
+
+* Student must be active in the community on chat.coreboot.org and the mailing list.
+
+* Students are expected to work on development publicly, and to push commits to the project
+on a regular basis. Depending on the project and what your mentor agrees to, these can be
+published directly to the project or to a public repository such as gitlab or github. If
+you are not publishing directly to the project codebase, be aware that we do not want large
+dumps of code that need to be rushed to meet the mid-term and final goals.
+
+We don't expect our students to be experts in our problem domain, but we don't want you to
+fail because some basic misunderstanding was in your way of completing the task.
+
+
+## Projects
+
+There are many development tasks available in coreboot. Please visit the following pages
+for some ideas or come up with your own idea.
+
+* coreboot project ideas
+* SerialICE project ideas
+
+We keep a list of previous GSoC Projects which might be of interest to you to see what
+others have accomplished. Similarly the blog posts related to previous GSoC projects might
+give some insights to what it is like to be a coreboot GSoC student.
+
+
+### Your own Project Ideas
+
+We have come up with some ideas for cool Summer of Code projects. These are projects that
+we think can be managed in the short period of GSoC, and they cover areas where coreboot
+is trying to reach new users and new use cases.
+
+Of course your application does not need to be based on any of the ideas listed. The
+opposite: Maybe you have a great idea that we just didn't think of yet. Please let us know!
+
+
+## coreboot Summer of Code Application
+
+coreboot welcomes students from all backgrounds and levels of experience.
+
+Your application should include a complete project proposal. You should document that you
+have the knowledge and the ability to complete your proposed project. This may require a
+little research and understanding of coreboot prior to sending your application. The
+community and coreboot project mentors are your best resource in fleshing out your project
+ideas and helping with a project timeline. We recommend that you get feedback and
+recommendations on your proposal before the application deadline.
+
+Please complete the standard Google SoC application and project proposal. Prospective
+coreboot GSoC student should provide the following information as part of their application.
+If you are applying for a flashrom or SerialICE project use common sense when using the
+template below, this is part of the test. ;)
+
+** Personal Information **
+
+* Name
+* Email
+* Phone number
+* chat/IM/IRC/Skype/other contact
+* Country/Timezone
+* Normal working hours(UTC)
+* School
+* Degree Program
+* Expected graduation date
+* Short bio / overview of your background
+* What are your other time commitments? Do you have a job, classes, vacations? When and how long?
+
+** Software experience **
+
+* Github / Web Page / Blog / Microblog / Portfolio:
+* Links to one or more patches submitted to the project you're applying for:
+* Links to posts on the mailing list with the serial output of your build: Mailing List Archives
+* Please comment on your software and firmware experience.
+* Have you contributed to an open source project? Which one? What was your experience?
+* Did you build and run coreboot? Did you have problems?
+
+** Your project **
+
+Please provide an overview of your project (in your own words).
+
+* Provide break down of your project in small specific weekly goals. Think about the potential timeline.
+* How will you accomplish this goal? What is your working style?
+* Explain what risks or potential problems your project might experience.
+* What would you expect as a minimum level of success?
+* Do you have a stretch goal?
+
+** Other **
+
+* Resume (optional)
+
+
+### Advice on how to apply
+
+* The Drupal project has a great page on how to write an SOC application.
+* GSoC Student Guide: [1]
+* Secrets for GSoC success: [2]
+
+
+## Mentors
+
+Each accepted project will have a lead mentor and a backup mentor. We will match
+mentors and students based on the project, experience level, and geographic location
+(native language, culture and time zone).
+
+Summer of Code primary mentors, are expected to stay in frequent contact with the
+student and provide guidance such as code reviews, pointers to useful documentation,
+etc. This should generally be a time commitment of one to two hours a week.
+
+Backup mentors are expected to coordinate with the primary mentor and student on a
+regular basis, and keep track of the student process. They should be work with the
+primary mentor and be available to take over mentoring duty if the primary mentor is
+unavailable (vacations, sickness, emergencies).
+
+
+### Volunteering to be a mentor
+
+If you'd like to volunteer to be a mentor, please read the GSoC Mentor Manual. This
+will give you a better idea of expectations, and where to go for help. After that,
+contact Martin or Patrick and let them know that you're interested.
+
+The following coreboot developers have volunteered to be GSoC 2017 mentors. Please
+stop by chat.coreboot.org and say hi to them and ask them questions.
diff --git a/Documentation/index.md b/Documentation/index.md
index bdfb6bf..61ae05f 100644
--- a/Documentation/index.md
+++ b/Documentation/index.md
@@ -170,6 +170,7 @@
* [Tutorial](tutorial/index.md)
* [Coding Style](contributing/coding_style.md)
* [Project Ideas](contributing/project_ideas.md)
+* [Google Summer of Code](contributing/gsoc.md)
* [Documentation Ideas](contributing/documentation_ideas.md)
* [Code of Conduct](community/code_of_conduct.md)
* [Language style](community/language_style.md)
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Change subject: soc/intel/skylake: Add function to clear PMCON status bits
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> and without access to the EDS?
:) Good question.
Do you have access to https://www.intel.com/content/www/us/en/search.html?ws=idsa-default#:~:text…
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ritul guru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61462 )
Change subject: soc/amd/common/block/psp: add PSP command
......................................................................
Patch Set 12: Code-Review+1
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Change subject: soc/intel/graphics: Create Kconfig for mapping graphic memory base
......................................................................
Patch Set 19:
(2 comments)
File src/soc/intel/common/block/graphics/Kconfig:
https://review.coreboot.org/c/coreboot/+/61389/comment/c9184899_893f34e1
PS19, Line 26: to
: reach at DSM
> In future platform, GMADR is replaced by LMEMBAR which is fixed map to DSM/GSM.
> There is document 643504(FAS) mention it.
>
> GTT size is "fixed" at 8MB(which it is WIP to update in external document).
@Ethan, Please correct me, I don't think this code adjustment is due to FSP GFX PEIM. I read this as HW change ?
https://review.coreboot.org/c/coreboot/+/61389/comment/04c55a09_33d42d76
PS19, Line 29: GTT_SIZE
> Yes, the hardware process behind BAR 2(0x18) is changed in future platform. […]
Adding to what Nico had mentioned. This is my understanding with future Intel SoC platform design change
1. GTTMMADR (used for pointing to the GTT base) aka BAR0 remains unchanged.
2. GMADR (used to point at DSM base) aka BAR2 is now renamed to LMEMBAR0 and pointing to the GTT base hence, we need to add GTT size to reach at DSM base using graphics_get_memory_base(). For older SoC platforms where GMADR already points to the DSM, we don't need any additional math but for future SOC, we need that offset adjustment which is nothing but GTT size.
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