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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61259
to look at the new patch set (#19).
Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices
......................................................................
soc/amd/cezanne: Turn off gpp clock request for disabled devices
The current behavior does not actually check if a device is present before enabling the corresponding gpp_clkx_clock_request_mapping bits which may cause issues with L1SS. This change sets the corresponding gpp_clkx_clock_request_mapping to off if the corresponding device is disabled.
BUG=b:202252869
TEST=Checked that value of GPP_CLK_CNTRL matched the expected value when devices are enabled/disabled
FIXED=b:202252869
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c
---
M src/mainboard/amd/majolica/Makefile.inc
M src/mainboard/google/guybrush/Makefile.inc
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/fch.c
4 files changed, 111 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/61259/19
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Change subject: soc/intel/graphics: Create Kconfig for mapping graphic memory base
......................................................................
Patch Set 19:
(1 comment)
File src/soc/intel/common/block/graphics/Kconfig:
https://review.coreboot.org/c/coreboot/+/61389/comment/750d6fed_76a46e03
PS19, Line 29: GTT_SIZE
So if I understand correctly, really, all this is saying is that the framebuffer that the GFX PEIM creates on future platforms may just be offset from GMADR ? In other words, GMADR (PCI config 0x18) used to point to the framebuffer, but now it points to DSM instead and the framebuffer is allocated after DSM?
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Change subject: mb/google/brya/var/primus4es: reconfig USE_PM_ACPI_TIMER
......................................................................
Patch Set 2: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60417/comment/c38962af_b24949cf
PS2, Line 9: Config USE_PM_ACPI_TIMER to y for primus4es only as
: commit 1ce0f3aab7 (mb/google/brya: Fix S0i3 regression)
: breaks suspend stress test on ES CPU SKU.
> ping
ping
Patchset:
PS2:
> Could we submit this CL to enable S0iX on ES CPU?
Ok, let's go with the hack for now, knowing that the 4es variants will not be around forever.
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Change subject: cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
> Sounds like maybe a ucode bug in picasso? […]
this might totally be a bug in picasso; i don't know yet. would probably be good to have root-caused this before thinking about reverting or reworking this patch
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Change subject: console: Add missing va_end() in wrap_interactive_printf()
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> would be good if you could add the coverity CID for easier cross-referencing in the future; iirc i w […]
Sorry, will try to remember that next time. This was CID 1469540
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Change subject: cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
> so this patch is likely correct, but the hardware doesn't behave as expected at all. […]
Sounds like maybe a ucode bug in picasso?
I don't think I see any potential issues from this patch train with reverting just this one, ideally they should be "equivalent" operations for returning an LAPIC ID, but a second opinion would be nice
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Change subject: soc/intel/skylake: Add function to clear PMCON status bits
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> For now, may be mapping against the EDS?
and without access to the EDS?
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Change subject: cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
> cpuid_ext(0xb, 0).edx is 0 on all cores on picasso. […]
so this patch is likely correct, but the hardware doesn't behave as expected at all. i was told that the nipperkin variant of guybrush which uses a cezanne soc behaves as expected, so this might only affect picasso. still investigating
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