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Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61380
to look at the new patch set (#5).
Change subject: soc/inte/common: Add support to control coreboot and Intel SoC features
......................................................................
soc/inte/common: Add support to control coreboot and Intel SoC features
The patch adds a framework to control coreboot and Intel SoC features
dynamically. BIOS reads control information from OEM Section in the
Descriptor Region and control the developer selected features.
With the feature, debug team can control the selected SoC and coreboot
features without rebuilding the coreboot.
In order to enable the feature, SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE has
to be selcted from mainboard.
The OEM section starts from offset:0xf00 till end of the Descriptor
Region(0xfff).
This patch adds support to control CSE firmware update functionality.
BUG=b:153410586
TEST=Verified CSE firmware update functionality on brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62
---
M src/soc/intel/common/block/cse/cse_lite.c
A src/soc/intel/common/block/debug/Kconfig
A src/soc/intel/common/block/debug/Makefile.inc
A src/soc/intel/common/block/debug/debug_feature.c
A src/soc/intel/common/block/include/intelblocks/debug_feature.h
5 files changed, 80 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/61380/5
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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59507 )
Change subject: soc/intel/alderlake: Inject CSE TS into CBMEM timestamp table
......................................................................
Patch Set 16:
(3 comments)
File src/soc/intel/common/block/cse/Kconfig:
https://review.coreboot.org/c/coreboot/+/59507/comment/77ba52fd_ac80d957
PS16, Line 149: SOC_INTEL_CSE_PRE_CPU_TELEMETRY
nit: SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY?
If agreed, you might need to change in other places too.
https://review.coreboot.org/c/coreboot/+/59507/comment/63d00c96_ea3d98e4
PS16, Line 153: performance
: telemetry data.
nit: pre - cpu reset boot performance telemetry data.
File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/59507/comment/645bb32b_8d776fec
PS16, Line 501: cse_get_bootperformance_data
nit: cse_get_boot_performance_data?
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61769 )
Change subject: Update intel-microcode submodule to upstream master
......................................................................
Patch Set 1: Code-Review+2
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Change subject: Update intel-microcode submodule to upstream master
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Patch Set 1: Code-Review+2
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Change subject: util/inteltool: Add support for Tiger Lake chips detection and GPIOs
......................................................................
Patch Set 6:
(2 comments)
File util/inteltool/gpio_names/tigerlake.h:
https://review.coreboot.org/c/coreboot/+/56171/comment/4d5739e2_dd8dd572
PS6, Line 332: GPP_U4
Typo, GPP_U5.
https://review.coreboot.org/c/coreboot/+/56171/comment/9a2780b3_91fa9284
PS6, Line 1016: ,
Sorry, comma added in my comment.
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Change subject: soc/intel/alderlake: Inject CSE TS into CBMEM timestamp table
......................................................................
Patch Set 16:
(2 comments)
File src/soc/intel/common/block/cse/telemetry.c:
https://review.coreboot.org/c/coreboot/+/59507/comment/cf40c213_3d6717b8
PS16, Line 13: s64
> nit: […]
replied in the other one.
https://review.coreboot.org/c/coreboot/+/59507/comment/3710a9df_0eee66db
PS16, Line 37: (s64)
> why signed? could there be "negative" timestamps?
no negative timestamps but start_stamp in the below operation can result in start_stamp being negative, that is a valid case. Type casting to s64 before subtraction. I think this is correct.
start_stamp = current_time - ts[PERF_DATA_CSME_GET_PERF_RESPONSE];
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