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Change subject: src/arch/ppc64/arch_timer.c: implement timer functions
......................................................................
src/arch/ppc64/arch_timer.c: implement timer functions
Change-Id: I4a244df01f6d15cbefb3b01079f6eec943136983
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
---
M src/arch/ppc64/Makefile.inc
A src/arch/ppc64/arch_timer.c
2 files changed, 43 insertions(+), 0 deletions(-)
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Change subject: src/cpu/power9: add file structure for power9, implement SCOM access
......................................................................
src/cpu/power9: add file structure for power9, implement SCOM access
Change-Id: Ib555ce51294c94b22d9a7c0db84d38d7928f7015
Signed-off-by: Igor Bagnucki <igor.bagnucki(a)3mdeb.com>
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---
M src/arch/ppc64/include/arch/byteorder.h
M src/arch/ppc64/include/arch/io.h
M src/cpu/Makefile.inc
A src/cpu/power9/Kconfig
A src/cpu/power9/Makefile.inc
A src/cpu/power9/power9.c
A src/cpu/power9/scom.c
A src/include/cpu/power/scom.h
A src/include/cpu/power/spr.h
9 files changed, 414 insertions(+), 0 deletions(-)
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Change subject: src/driver/wifi: Add _DSM method for DDRRFIM
......................................................................
src/driver/wifi: Add _DSM method for DDRRFIM
coreboot need to propagate the CnviDdrRfim value info of the feature
enable/disable state into the CNVi via the WiFi DSM ACPI object. This
patch adds _DSM method for that.
Add support for following 2 function in _DSM method
- Function 0: Function Support Query Returns a bitmask of functions
supported.
- Function 3: RFI enablement 0 Feature Enable 1 Feature Disable
BUG=b:201724512
TEST=Build, boot brya0 and dump SSDT entries
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
ToBuffer (Arg0, Local0)
If ((Local0 == ToUUID ("7266172c-220b-4b29-814f-75e4dd26b5fd")))
{
ToInteger (Arg2, Local1)
If ((Local1 == Zero))
{
Return (Buffer (One)
{
0x09
})
}
If ((Local1 == One)){}
If ((Local1 == 0x02)){}
If ((Local1 == 0x03))
{
Return (Zero)
}
Return (Buffer (One)
{
0x00
})
}
Return (Buffer (One)
{
0x00
})
}
Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com>
Change-Id: I217b736df3d4224a6732d1941a160abcddbd8f37
---
M src/drivers/wifi/generic/acpi.c
1 file changed, 64 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/61020/12
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Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61737 )
Change subject: util/inteltool: Actually read SATA init data from SIRD
......................................................................
Patch Set 4:
This change is ready for review.
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61586 )
Change subject: mb/google/brya: Use USB2_PORT_MAX_TYPE_C for Type-C USB2 port
......................................................................
mb/google/brya: Use USB2_PORT_MAX_TYPE_C for Type-C USB2 port
The patch selects USB2_PORT_MAX_TYPE_C macro for usb2 port#2 in
the device tree of Gimble DVT and Gimble EVT. The macro modifies the
USB2 configuration to indicate the port is mapped to Type-C and sets
Max TX and Pre-emp settings.
The change is required to enable port reset event on the USB2 port#2.
This event is passed to USB3 upstream ports to upgrade back to super
speed (USB3) after a downgrade during low power state. The change is
done for Gimble DVT and EVT boards.
BUG=b:193287279
TEST=Built coreboot for Gimble and tested type A pen drive detect as
super speed device on both the Type-C ports.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: If54faa63a983c859bf26a6a779751a6c3c85c43d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61586
Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/brya/variants/gimble/overridetree.cb
M src/mainboard/google/brya/variants/gimble4es/overridetree.cb
2 files changed, 2 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Rizwan Qureshi: Looks good to me, approved
Maulik V Vaghela: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb
index 88f4b07..e13d66a 100644
--- a/src/mainboard/google/brya/variants/gimble/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb
@@ -32,7 +32,7 @@
register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
- register "usb2_ports[1]" = "USB2_PORT_MAX(OC1)" # set MAX to USB2_C1 for eye diagram
+ register "usb2_ports[1]" = "USB2_PORT_MAX_TYPE_C(OC1)" # set MAX to USB2_C1 for eye diagram
register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2_C2
register "usb2_ports[3]" = "USB2_PORT_EMPTY" # M.2 WWAN
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port
diff --git a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb
index 7cfcdb2..d7a000c 100644
--- a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb
@@ -32,7 +32,7 @@
register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
- register "usb2_ports[1]" = "USB2_PORT_MAX(OC1)" # set MAX to USB2_C1 for eye diagram
+ register "usb2_ports[1]" = "USB2_PORT_MAX_TYPE_C(OC1)" # set MAX to USB2_C1 for eye diagram
register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2_C2
register "usb2_ports[3]" = "USB2_PORT_EMPTY" # M.2 WWAN
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port
--
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Gerrit-Change-Number: 61586
Gerrit-PatchSet: 11
Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61623 )
Change subject: soc/intel/alderlake: Define USB2_PORT_MAX_TYPE_C macro
......................................................................
soc/intel/alderlake: Define USB2_PORT_MAX_TYPE_C macro
The patch defines USB2_PORT_MAX_TYPE_C macro to allow mark the type_c
flag.The USB2_PORT_MAX_TYPE_C macro modifies the USB2 configuration to
indicate the port mapped to Type-C and sets Max TX and Pre-emp
settings. This is an extension to existing macro USB2_PORT_MAX.
The change is required to enable port reset event on a USB2 port.
This event is passed to USB3 upstream ports to upgrade back to super
speed (USB3) after a downgrade during low power state.
BUG=b:193287279
TEST=Build the code for Gimble board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: I464f139d8e367907191c04f9170ac53d327776ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61623
Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/intel/alderlake/include/soc/usb.h
1 file changed, 11 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Rizwan Qureshi: Looks good to me, approved
Maulik V Vaghela: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/include/soc/usb.h b/src/soc/intel/alderlake/include/soc/usb.h
index 70a367e..0eb6160 100644
--- a/src/soc/intel/alderlake/include/soc/usb.h
+++ b/src/soc/intel/alderlake/include/soc/usb.h
@@ -104,6 +104,17 @@
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
}
+/* Type-C Port, Max TX and Pre-emp settings */
+#define USB2_PORT_MAX_TYPE_C(pin) { \
+ .enable = 1, \
+ .ocpin = (pin), \
+ .tx_bias = USB2_BIAS_56P3MV, \
+ .tx_emp_enable = USB2_PRE_EMP_ON, \
+ .pre_emp_bias = USB2_BIAS_56P3MV, \
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
+ .type_c = 1, \
+}
+
/* Type-C Port, no BC1.2 charge detect module / MUX
* Length = 3.0" - 9.00" */
#define USB2_PORT_TYPE_C(pin) { \
--
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Gerrit-Change-Id: I464f139d8e367907191c04f9170ac53d327776ee
Gerrit-Change-Number: 61623
Gerrit-PatchSet: 6
Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61576 )
Change subject: util/ifdtool: add generic `PLATFORM_IFD2` for early SoC development
......................................................................
util/ifdtool: add generic `PLATFORM_IFD2` for early SoC development
`PLATFORM_IFD2` macro is more generic tag that can be associated with
early next SoC platform development which using IFDv2.
The current assumption is that newer SoC platform still uses the same
SPI/eSPI frequency definition being used for latest platform(TGL, ADL)
and if the frequency definition is updated later, `PLATFORM_IFD2' will
use latest frequency definition for early next SoC development.
And once upstream is allowed for new platform, platform name will be
added in tool later.
Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com>
Change-Id: I14a71a58c7d51b9c8b92e013b5637c6b35005f22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61576
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
---
M util/ifdtool/ifdtool.c
M util/ifdtool/ifdtool.h
2 files changed, 7 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index 586f50f..20c4ed4 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -231,6 +231,7 @@
return CHIPSET_300_SERIES_CANNON_POINT;
case PLATFORM_TGL:
case PLATFORM_ADL:
+ case PLATFORM_IFD2:
return CHIPSET_500_600_SERIES_TIGER_ALDER_POINT;
case PLATFORM_ICL:
return CHIPSET_400_SERIES_ICE_POINT;
@@ -260,6 +261,7 @@
PLATFORM_EHL,
PLATFORM_ADL,
PLATFORM_SKLKBL,
+ PLATFORM_IFD2,
};
unsigned int i;
@@ -1185,6 +1187,7 @@
case PLATFORM_JSL:
case PLATFORM_EHL:
case PLATFORM_ADL:
+ case PLATFORM_IFD2:
/* CPU/BIOS can read descriptor and BIOS. */
fmba->flmstr1 |= (1 << REGION_DESC) << rd_shift;
fmba->flmstr1 |= (1 << REGION_BIOS) << rd_shift;
@@ -1642,6 +1645,7 @@
" ehl - Elkhart Lake\n"
" glk - Gemini Lake\n"
" icl - Ice Lake\n"
+ " ifd2 - IFDv2 Platform\n"
" jsl - Jasper Lake\n"
" sklkbl - Sky Lake/Kaby Lake\n"
" tgl - Tiger Lake\n"
@@ -1909,6 +1913,8 @@
platform = PLATFORM_TGL;
} else if (!strcmp(optarg, "adl")) {
platform = PLATFORM_ADL;
+ } else if (!strcmp(optarg, "ifd2")) {
+ platform = PLATFORM_IFD2;
} else {
fprintf(stderr, "Unknown platform: %s\n", optarg);
exit(EXIT_FAILURE);
diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h
index bde104a..15e207d 100644
--- a/util/ifdtool/ifdtool.h
+++ b/util/ifdtool/ifdtool.h
@@ -58,6 +58,7 @@
PLATFORM_SKLKBL,
PLATFORM_TGL,
PLATFORM_ADL,
+ PLATFORM_IFD2,
};
#define LAYOUT_LINELEN 80
5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
--
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Gerrit-Change-Number: 61576
Gerrit-PatchSet: 8
Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com>
Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
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Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61520 )
Change subject: soc/intel/common/cse: Add function to perform global reset lock
......................................................................
soc/intel/common/cse: Add function to perform global reset lock
This patch implements `cse_control_global_reset_lock()` as per ME BWG
(doc: 627331) recommendation.
It is recommended that BIOS should set this bit early on in the boot
sequence, and then clear it and set the CF9LOCK bit prior to loading
the OS in both an Intel CSME Enabled and a Intel CSME Disabled system.
Note: For CSE-Lite SKUs BIOS should set CF9LOCK bit unconditionally.
BUG=b:211954778
TEST=Able to build and boot Brya.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61520
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 23 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Arthur Heymans: Looks good to me, approved
Lean Sheng Tan: Looks good to me, approved
Sridhar Siricilla: Looks good to me, approved
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index a9a619c..5140369 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -11,6 +11,7 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <intelblocks/cse.h>
+#include <intelblocks/pmclib.h>
#include <option.h>
#include <security/vboot/misc.h>
#include <security/vboot/vboot_common.h>
@@ -1008,6 +1009,25 @@
}
}
+void cse_control_global_reset_lock(void)
+{
+ /*
+ * As per ME BWG recommendation the BIOS should not lock down CF9GR bit during
+ * manufacturing and re-manufacturing environment if HFSTS1 [4] is set. Note:
+ * this recommendation is not applicable for CSE-Lite SKUs where BIOS should set
+ * CF9LOCK bit irrespectively.
+ *
+ * Other than that, make sure payload/OS can't trigger global reset.
+ *
+ * BIOS must also ensure that CF9GR is cleared and locked (Bit31 of ETR3)
+ * prior to transferring control to the OS.
+ */
+ if (CONFIG(SOC_INTEL_CSE_LITE_SKU) || cse_is_hfs1_spi_protected())
+ pmc_global_reset_disable_and_lock();
+ else
+ pmc_global_reset_enable(false);
+}
+
#if ENV_RAMSTAGE
/*
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index c2efab1..e67d9d8 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -495,6 +495,9 @@
/* Function sets D0I3 for all HECI devices */
void heci_set_to_d0i3(void);
+/* Function performs the global reset lock */
+void cse_control_global_reset_lock(void);
+
/*
* SoC override API to make heci1 disable using PCR.
*
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381
Gerrit-Change-Number: 61520
Gerrit-PatchSet: 15
Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61687 )
Change subject: mb/google/brya/var/nivviks: Add MT62F512M32D2DR-031 WT:B for P1 build
......................................................................
mb/google/brya/var/nivviks: Add MT62F512M32D2DR-031 WT:B for P1 build
Nivviks P1 will also use Micron MT62F512M32D2DR-031 WT:B. Add it to the
parts list and regenerate the memory IDs using part_id_gen.
BUG=b:217095281
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
Signed-off-by: Reka Norman <rekanorman(a)google.com>
Change-Id: I2b56b0844e70a2712923b197436dd2d668e58a27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61687
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Kangheui Won <khwon(a)chromium.org>
---
M src/mainboard/google/brya/variants/nivviks/memory/Makefile.inc
M src/mainboard/google/brya/variants/nivviks/memory/dram_id.generated.txt
M src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt
3 files changed, 3 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Kangheui Won: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/nivviks/memory/Makefile.inc b/src/mainboard/google/brya/variants/nivviks/memory/Makefile.inc
index db35a4d..3fb4d48 100644
--- a/src/mainboard/google/brya/variants/nivviks/memory/Makefile.inc
+++ b/src/mainboard/google/brya/variants/nivviks/memory/Makefile.inc
@@ -5,3 +5,4 @@
SPD_SOURCES =
SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 0(0b0000) Parts = MT62F1G32D4DR-031 WT:B
+SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = MT62F512M32D2DR-031 WT:B
diff --git a/src/mainboard/google/brya/variants/nivviks/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/nivviks/memory/dram_id.generated.txt
index 1ad0e36..9a239f8 100644
--- a/src/mainboard/google/brya/variants/nivviks/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/nivviks/memory/dram_id.generated.txt
@@ -5,3 +5,4 @@
DRAM Part Name ID to assign
MT62F1G32D4DR-031 WT:B 0 (0000)
+MT62F512M32D2DR-031 WT:B 1 (0001)
diff --git a/src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt
index 9c853bd..3769843 100644
--- a/src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt
@@ -10,3 +10,4 @@
# Part Name
MT62F1G32D4DR-031 WT:B
+MT62F512M32D2DR-031 WT:B
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I2b56b0844e70a2712923b197436dd2d668e58a27
Gerrit-Change-Number: 61687
Gerrit-PatchSet: 4
Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org>
Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged