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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57684 )
Change subject: soc/intel/common: Add PMC Crashlog PCI driver
......................................................................
Patch Set 8:
(3 comments)
File src/soc/intel/common/block/crashlog/pmc_crashlog.c:
https://review.coreboot.org/c/coreboot/+/57684/comment/8b163b49_4544cefb
PS1, Line 248: en_gen_on_all_reboot
> That is really weird. […]
Ack
File src/soc/intel/common/block/crashlog/pmc_crashlog.c:
https://review.coreboot.org/c/coreboot/+/57684/comment/dc53683b_5f943596
PS6, Line 151: printk
> can we have DEBUG_CRASHLOG like config to skip printing this msg by default?
Ack
https://review.coreboot.org/c/coreboot/+/57684/comment/e4cb0180_266b5953
PS6, Line 233: copy_dwords_from_sram(table_addr, dest, crashlog_info.table.total_size);
> nit - blank line between declarations and first line of code
Ack
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Subrata Banik has uploaded a new patch set (#8) to the change originally created by Tim Wawrzynczak. ( https://review.coreboot.org/c/coreboot/+/57684 )
Change subject: soc/intel/common: Add PMC Crashlog PCI driver
......................................................................
soc/intel/common: Add PMC Crashlog PCI driver
This driver discovers if any crashlog data is available from the PMC and
provides a mechanism to copy the data to memory.
BUG=b:195327879
TEST=with patch series, can collect PMC crashlog on every reboot
Change-Id: Ifc27bbdf35fcd680be224ba0a0e642c94d29bca3
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Signed-off-by: Francois Toguo <francois.toguo.fotso(a)intel.com>
---
M src/soc/intel/common/Kconfig.common
A src/soc/intel/common/block/crashlog/Kconfig
A src/soc/intel/common/block/crashlog/Makefile.inc
A src/soc/intel/common/block/crashlog/crashlog_lib.c
A src/soc/intel/common/block/crashlog/crashlog_lib.h
A src/soc/intel/common/block/crashlog/pmc_crashlog.c
6 files changed, 574 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/57684/8
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Change subject: util/inteltool: Add support for Tiger Lake chips detection and GPIOs
......................................................................
Patch Set 5:
(3 comments)
File util/inteltool/gpio_names/tigerlake.h:
https://review.coreboot.org/c/coreboot/+/56171/comment/fcd34f02_35b19d64
PS4, Line 26: n/a"
> DDSP_HPDC
Done
https://review.coreboot.org/c/coreboot/+/56171/comment/b3b3349a_0f510563
PS4, Line 128: n/a
> I2C4_SDA
Done
https://review.coreboot.org/c/coreboot/+/56171/comment/c3b1936e_bcf33633
PS4, Line 129: n/a
> I2C4_SCL
Done
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Hello Felix Singer, build bot (Jenkins), Wonkyu Kim, Ravishankar Sarawadi, Stefan Reinauer, Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56171
to look at the new patch set (#6).
Change subject: util/inteltool: Add support for Tiger Lake chips detection and GPIOs
......................................................................
util/inteltool: Add support for Tiger Lake chips detection and GPIOs
Add PCI IDs for Tiger Lake LP and Tiger Lake H devices and their GPIO
tables.
TEST: dump GPIOs on i5-1135G7, Tiger Lake H untested
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I6071a999be9e8a372997db0369218f297e579d08
---
M util/inteltool/gpio.c
M util/inteltool/gpio_groups.c
A util/inteltool/gpio_names/tigerlake.h
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
M util/inteltool/pcr.c
6 files changed, 1,503 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/56171/6
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Change subject: mb/google/nissa: Set half_populated true
......................................................................
Patch Set 3:
This change is ready for review.
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Change subject: mb/intel/adlrvp: Fix vbt loading error
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61528/comment/ded19baa_24b758e7
PS4, Line 15: VBTs for different RVP boards; while we only need 1 vbt for generic
> Why aren't the files added to the tree? In case somebody wants to […]
Yeah agreed, using site-local is more proper way. we can merge this in for generic use case while chrome setup should use site-local instead. Thanks for the review Nico :)
Patchset:
PS1:
> Hi Meera may I know do you stitch different vbt together and integrate in coreboot?
Close this as Maulik has replied.
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Change subject: util/inteltool: Add support for Tiger Lake chips detection and GPIOs
......................................................................
Patch Set 5:
(3 comments)
File util/inteltool/gpio_names/tigerlake.h:
https://review.coreboot.org/c/coreboot/+/56171/comment/379805ff_e7188d83
PS4, Line 26: n/a"
DDSP_HPDC
https://review.coreboot.org/c/coreboot/+/56171/comment/f855995e_5e510eba
PS4, Line 128: n/a
I2C4_SDA
https://review.coreboot.org/c/coreboot/+/56171/comment/b45a593a_605942e9
PS4, Line 129: n/a
I2C4_SCL
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Change subject: util/inteltool: Add support for Tiger Lake chips detection and GPIOs
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
Added other groups like SPI, CPU, JTAG... Hopefully I didn't mess this up
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Change subject: util/inteltool: Add support for Tiger Lake chips detection and GPIOs
......................................................................
Patch Set 4:
(17 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56171/comment/79667a05_290d8004
PS4, Line 9: Tiger Lake
> nit: Tiger Lake LP
Done
Patchset:
PS4:
> Right, I may use OpenBoardPackage
Done
File util/inteltool/gpio_names/tigerlake.h:
PS4:
> If the other files also lack the license, I would put a separate patch to fill all missing license h […]
Ack
https://review.coreboot.org/c/coreboot/+/56171/comment/efc257af_33a0f4bf
PS4, Line 70:
> nit: drop blank line
Done
https://review.coreboot.org/c/coreboot/+/56171/comment/b47b13f7_1d88323f
PS4, Line 135: };
> missing GSPI2_CLK_LOOPBK
Done
https://review.coreboot.org/c/coreboot/+/56171/comment/114730cd_7aa4bccb
PS4, Line 169: };
> 24 is GPPE_CLK_LOOPBK, "n/a", "THC0_CLK_LOOPBACK"
Done
https://review.coreboot.org/c/coreboot/+/56171/comment/46173f77_f0d7e33e
PS4, Line 179: const char *const tigerlake_pch_lp_fe_hole_names[] = {
> this is the HVMOS group, compare util/inteltool/gpio_names/cannonlake_lp. […]
Done
https://review.coreboot.org/c/coreboot/+/56171/comment/e11f1864_fa227c30
PS4, Line 221: };
> 24 is GPPF_CLK_LOOPBK, "n/a", "THC1_CLK_LOOPBACK"
Done
https://review.coreboot.org/c/coreboot/+/56171/comment/d47aeb65_74668459
PS4, Line 336: "Reserved",
> Yes, they are. […]
Added all GPP_U pins according to OpenBoardPackage
https://review.coreboot.org/c/coreboot/+/56171/comment/b9f772de_801c3ce0
PS4, Line 361: };
> These are GPD12+??
Done
https://review.coreboot.org/c/coreboot/+/56171/comment/5abf762d_1ab95f6c
PS4, Line 535: 3
> I think this is actually 5? GPP_C was dumping strangely and it mismatches the pad_count.
Yes, copy pasta error
https://review.coreboot.org/c/coreboot/+/56171/comment/431d31e1_c8a13da5
PS4, Line 575: tigerlake_pch_h_group_e_names
> "GPP_E0/SATAXPCIE0/SATAGP0" is missing.
Done
https://review.coreboot.org/c/coreboot/+/56171/comment/664c22d0_a314f896
PS4, Line 753: GPP_J
> GPP_K
Done
https://review.coreboot.org/c/coreboot/+/56171/comment/89beaa95_25f93989
PS4, Line 759: tigerlake_pch_h_group_r_names
> "GPP_R0/HDA_BCLK/I2S0_SCLK/n_a/HDACPU_BCLK," "GPP_R1/HDA_SYNC/I2S0_SFRM/n_a/n_a" and "GPP_R2/HDA_SDO […]
Done
https://review.coreboot.org/c/coreboot/+/56171/comment/f32dc808_4ea594bd
PS4, Line 777:
> nit: drop blank line
Done
https://review.coreboot.org/c/coreboot/+/56171/comment/9d302334_7746a85d
PS4, Line 901: tigerlake_pch_h_communities
> Will check with other sources. […]
Done
File util/inteltool/pcr.c:
https://review.coreboot.org/c/coreboot/+/56171/comment/6c290ea8_6623ae3c
PS4, Line 108: case PCI_DEVICE_ID_INTEL_Q570:
: case PCI_DEVICE_ID_INTEL_Z590:
: case PCI_DEVICE_ID_INTEL_H570:
: case PCI_DEVICE_ID_INTEL_B560:
: case PCI_DEVICE_ID_INTEL_H510:
: case PCI_DEVICE_ID_INTEL_WM590:
: case PCI_DEVICE_ID_INTEL_QM580:
: case PCI_DEVICE_ID_INTEL_HM570:
: case PCI_DEVICE_ID_INTEL_C252:
: case PCI_DEVICE_ID_INTEL_C256:
: case PCI_DEVICE_ID_INTEL_W580:
> Okay. We may pray that nobody changes the default sideband BAR...
Done
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Attention is currently required from: Felix Singer, Wonkyu Kim, Benjamin Doron, Ravishankar Sarawadi, Stefan Reinauer, Angel Pons, Michael Niewöhner.
Hello Felix Singer, Wonkyu Kim, build bot (Jenkins), Ravishankar Sarawadi, Stefan Reinauer, Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56171
to look at the new patch set (#5).
Change subject: util/inteltool: Add support for Tiger Lake chips detection and GPIOs
......................................................................
util/inteltool: Add support for Tiger Lake chips detection and GPIOs
Add PCI IDs for Tiger Lake LP and Tiger Lake H devices and their GPIO
tables.
TEST: dump GPIOs on i5-1135G7, Tiger Lake H untested
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I6071a999be9e8a372997db0369218f297e579d08
---
M util/inteltool/gpio.c
M util/inteltool/gpio_groups.c
A util/inteltool/gpio_names/tigerlake.h
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
M util/inteltool/pcr.c
6 files changed, 1,503 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/56171/5
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