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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/var/anahera4es: Add gpios to lock
......................................................................
mb/google/var/anahera4es: Add gpios to lock
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
Also fix the gpio order of GPP_F19.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
anahera4es boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com>
Change-Id: I9a73aca1c364dcbc3f3957cd4193d86f399a40bb
---
M src/mainboard/google/brya/variants/anahera4es/gpio.c
1 file changed, 12 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/61661/4
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Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61162 )
Change subject: soc/intel/common: Re-use Alder Lake-M device IDs for Alder Lake-N
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61162/comment/fb07b29d_2a819093
PS3, Line 11: Hence rename those device IDs as ADL_M_N and use them for Alder Lake-N
> No new paragraph needed.
Ack
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Hello Bora Guvendik, build bot (Jenkins), Kangheui Won, Selma Bensaid, Reka Norman, Tim Wawrzynczak, Rizwan Qureshi, Krishna P Bhat D, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common: Re-use Alder Lake-M device IDs for Alder Lake-N
......................................................................
soc/intel/common: Re-use Alder Lake-M device IDs for Alder Lake-N
Few of the Alder Lake-N Device IDs according to EDS, are named as ADL_M
IDs in the current code. Hence rename those device IDs as ADL_M_N and
use them for Alder Lake-N platform.
Document Number: 619501, 645548
Signed-off-by: Usha P <usha.p(a)intel.com>
Change-Id: I6042017c6189cbc3ca9dce0e50acfb68ea4003f1
---
M src/include/device/pci_ids.h
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/uart/uart.c
11 files changed, 120 insertions(+), 118 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/61162/5
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Change subject: soc/intel/common: Re-use Alder Lake-M device IDs for Alder Lake-N
......................................................................
soc/intel/common: Re-use Alder Lake-M device IDs for Alder Lake-N
Few of the Alder Lake-N Device IDs according to EDS, are named as ADL_M
IDs in the current code. Hence rename those device IDs as ADL_M_N and use
them for Alder Lake-N platform.
Document Number: 619501, 645548
Signed-off-by: Usha P <usha.p(a)intel.com>
Change-Id: I6042017c6189cbc3ca9dce0e50acfb68ea4003f1
---
M src/include/device/pci_ids.h
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/uart/uart.c
11 files changed, 120 insertions(+), 118 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/61162/4
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 )
Change subject: soc/intel/common/cse: Add `finalize` operation for CSE
......................................................................
Patch Set 25:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/60405/comment/4ab67c50_b3c576a9
PS24, Line 1195: static void cse_final(struct device *dev)
: {
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT)) {
: cse_send_end_of_post();
:
: cse_control_global_reset_lock();
:
: if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) {
: cse_set_to_d0i3();
: heci1_disable();
: }
: }
:
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
: heci_set_to_d0i3();
: }
> hi Sridhar, I am not following your statement, but seems like you are not too familiar with FSP and coreboot design..
> Or else you would have known that any new changes in FSP spec will only comes with next version, and then we can then design accordingly based on latest FSP spec, but the current implementation should be consistent across FSP2.0.
+1 to what Sheng said, I'm unable to understand how you will able to change the FSP design and make those API call non-sequentially compared to how it's design in FSP2.0 driver (https://review.coreboot.org/c/coreboot/+/15855/) 6 year ago.
Even if you could build Intel UEFI FSP-Wrapper code in API mode, you will see those APIs are getting executed sequentially.
I don't want to say here, but looking at your review comments in this patch trend, it looks like you have some concern in mind which you are not sharing. Are you against this approach of coreboot implementing notify phase natively. If yes, then here is read for you.
FSPv2.1 release note in coreboot mailing list
https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/AJUY…
 Dispatch Mode – A new optional FSP boot mode intended to ease integration of FSP with PI spec bootloaders. In dispatch mode, FSP-M and FSP-S are containers that expose firmware volumes (FVs) directly to the bootloader. The PEIMs in these FVs are executed directly in the context of the PEI environment provided by the bootloader. In dispatch mode, the FspMemoryInit(), FspSiliconInit(), and
NotifyPhase() API’s are not used.
***NotifyPhase() is replaced by FSP-S containing DXE drivers that provide a native implementation of equivalent events for each of the NotifyPhase() invocations.***
FSP in dispatch mode is not using PEI implementation of Notify Phase instead uses DXE driver. Then what is wrong if coreboot decides to implement a native code of managing notify work. As I have mentioned, all these registers are part of EDS and FAS section 12 has mentioned about the OEM/ODM fundamental right about implementing those lockdowns. I'm even planning to land all the Silicon recommendations as per FAS over incremental CLs.
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Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61759 )
Change subject: payloads/tianocore: Add option to include EFI Shell
......................................................................
payloads/tianocore: Add option to include EFI Shell
Add TIANOCORE_HAVE_EFI_SHELL, which when enabled, will build edk2
with the EFI Shell binary.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I1272f514e3f5becfe1fddd58ca0d820c5d1c1b54
---
M payloads/external/Makefile.inc
M payloads/external/tianocore/Kconfig
M payloads/external/tianocore/Makefile
3 files changed, 12 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/61759/1
diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
index 06a8ca2..baa6104 100644
--- a/payloads/external/Makefile.inc
+++ b/payloads/external/Makefile.inc
@@ -153,6 +153,7 @@
CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \
CONFIG_TIANOCORE_CBMEM_LOGGING=$(CONFIG_TIANOCORE_CBMEM_LOGGING) \
CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC=$(CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC) \
+ CONFIG_TIANOCORE_HAVE_EFI_SHELL=$(CONFIG_TIANOCORE_HAVE_EFI_SHELL) \
CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \
CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
GCC_CC_x86_32=$(GCC_CC_x86_32) \
diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig
index 9989457..387a05e 100644
--- a/payloads/external/tianocore/Kconfig
+++ b/payloads/external/tianocore/Kconfig
@@ -138,8 +138,14 @@
default n
help
Follow the BGRT Specification implemented by Microsoft and
- the Boot Logo will be vertically centered 38.2% from the
- top of the display.
+ the Boot Logo 38.2% will be vertically centered 38.2% from
+ the top of the display.
+
+config TIANOCORE_HAVE_EFI_SHELL
+ bool "Include EFI Shell"
+ default y
+ help
+ Include the EFI shell Binary
endif
diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile
index 15dbd19..f40e103 100644
--- a/payloads/external/tianocore/Makefile
+++ b/payloads/external/tianocore/Makefile
@@ -43,6 +43,9 @@
# PLATFORM_BOOT_TIMEOUT = 3
ifneq ($(TIANOCORE_BOOT_TIMEOUT),)
BUILD_STR += -D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT)
+# SHELL_TYPE = BUILD_SHELL
+ifneq ($(CONFIG_TIANOCORE_HAVE_EFI_SHELL),y)
+BUILD_STR += -D SHELL_TYPE=NONE
endif
# USE_CBMEM_FOR_CONSOLE = FALSE
ifeq ($(CONFIG_TIANOCORE_CBMEM_LOGGING),y)
--
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Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems>
Gerrit-MessageType: newchange
Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61758 )
Change subject: payloads/tianocore: Add option to use follow BGRT spec
......................................................................
payloads/tianocore: Add option to use follow BGRT spec
Adds TIANOCORE_FOLLOW_BGRT_SPEC which, when enabled, will follow
the BGRT Specification implemented by Microsoft and the Boot Logo
will be vertically centered 38.2% from the top of the display.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: If508166fe657d1cc032dd09a0fa231c7b60d9846
---
M payloads/external/Makefile.inc
M payloads/external/tianocore/Kconfig
M payloads/external/tianocore/Makefile
3 files changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/61758/1
diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
index df72edf..06a8ca2 100644
--- a/payloads/external/Makefile.inc
+++ b/payloads/external/Makefile.inc
@@ -152,6 +152,7 @@
CONFIG_TIANOCORE_BOOT_MANAGER_ESCAPE=$(CONFIG_TIANOCORE_BOOT_MANAGER_ESCAPE) \
CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \
CONFIG_TIANOCORE_CBMEM_LOGGING=$(CONFIG_TIANOCORE_CBMEM_LOGGING) \
+ CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC=$(CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC) \
CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \
CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
GCC_CC_x86_32=$(GCC_CC_x86_32) \
diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig
index 333378c..9989457 100644
--- a/payloads/external/tianocore/Kconfig
+++ b/payloads/external/tianocore/Kconfig
@@ -133,6 +133,14 @@
this option, especially if using a debug (vs release) build.
Selecting this option will increase the payload size in CBFS by 0x10000.
+config TIANOCORE_FOLLOW_BGRT_SPEC
+ bool "Center logo 38.2% from the top of screen"
+ default n
+ help
+ Follow the BGRT Specification implemented by Microsoft and
+ the Boot Logo will be vertically centered 38.2% from the
+ top of the display.
+
endif
if TIANOCORE_COREBOOTPAYLOAD
diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile
index a2b1c9e..15dbd19 100644
--- a/payloads/external/tianocore/Makefile
+++ b/payloads/external/tianocore/Makefile
@@ -36,6 +36,10 @@
ifeq ($(CONFIG_TIANOCORE_DEBUG),y)
BUILD_STR += -b DEBUG
endif
+# FOLLOW_BGRT_SPEC = FALSE
+ifeq ($(CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC),y)
+BUILD_STR += -D FOLLOW_BGRT_SPEC=TRUE
+endif
# PLATFORM_BOOT_TIMEOUT = 3
ifneq ($(TIANOCORE_BOOT_TIMEOUT),)
BUILD_STR += -D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT)
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If508166fe657d1cc032dd09a0fa231c7b60d9846
Gerrit-Change-Number: 61758
Gerrit-PatchSet: 1
Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems>
Gerrit-MessageType: newchange