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Change subject: soc/mediatek: Only update required bits when triggering WDT reset
......................................................................
Patch Set 3:
(1 comment)
File src/soc/mediatek/common/wdt.c:
https://review.coreboot.org/c/coreboot/+/61729/comment/5442e302_91630724
PS3, Line 36: write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
> Do we want to change this as well?
no need to do this.
we just need to write MTK_WDT_SWRST_KEY to do reset.
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Change subject: soc/mediatek: Only update required bits when triggering WDT reset
......................................................................
Patch Set 3:
(1 comment)
File src/soc/mediatek/common/wdt.c:
https://review.coreboot.org/c/coreboot/+/61729/comment/609dd107_e5f89930
PS3, Line 36: write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
Do we want to change this as well?
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Change subject: soc/intel/common/cse: Add `finalize` operation for CSE
......................................................................
Patch Set 25:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/60405/comment/f16fc2da_a9e4abfa
PS24, Line 1195: static void cse_final(struct device *dev)
: {
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT)) {
: cse_send_end_of_post();
:
: cse_control_global_reset_lock();
:
: if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) {
: cse_set_to_d0i3();
: heci1_disable();
: }
: }
:
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
: heci_set_to_d0i3();
: }
> Hi Subrata, are you planning to change the kconfig from SKIP_ to CONFIG_USE_ as per suggested by Arthur in current patch train or later on?
I will pick this in current train itself. Will get back in 1-2 days. Thanks for your review time.
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Change subject: soc/intel/common/cse: Add `finalize` operation for CSE
......................................................................
Patch Set 25:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/60405/comment/34f4457d_b753635f
PS24, Line 1195: static void cse_final(struct device *dev)
: {
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT)) {
: cse_send_end_of_post();
:
: cse_control_global_reset_lock();
:
: if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) {
: cse_set_to_d0i3();
: heci1_disable();
: }
: }
:
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
: heci_set_to_d0i3();
: }
> > hi Sridhar, I am not following your statement, but seems like you are not too familiar with FSP an […]
Hi Subrata, are you planning to change the kconfig from SKIP_ to CONFIG_USE_ as per suggested by Arthur in current patch train or later on?
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Hello build bot (Jenkins), Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61761
to look at the new patch set (#3).
Change subject: mb/google/brya/var/vell: Add Wifi SAR for vell
......................................................................
mb/google/brya/var/vell: Add Wifi SAR for vell
Add wifi sar for vell
BUG=b:
TEST=emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
Change-Id: I74fddd1dbcb7019fd5fe394da291f125f0d4960f
Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/vell/Makefile.inc
A src/mainboard/google/brya/variants/vell/variant.c
2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/61761/3
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Change subject: soc/intel/common/cse: Add `cse_send_end_of_post()` as a public function
......................................................................
Patch Set 9: Code-Review+1
(1 comment)
Patchset:
PS9:
looks good with current progress.
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Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61725 )
Change subject: .mailmap: Add a .mailmap file for git
......................................................................
Patch Set 1:
(1 comment)
File .mailmap:
https://review.coreboot.org/c/coreboot/+/61725/comment/d6c609d1_dd40d883
PS1, Line 225: Max Blau <tripleshiftone(a)gmail.com> Bluemax <1403092+BlueMax(a)users.noreply.github.com>
Hi Martin
Please add my email
"Maxim Polyakov <max.senia.poliak(a)gmail.com> <m.poliakov(a)yahoo.com>"
Thanks
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61716 )
Change subject: sc7280: Disable fingerprint sensor feature as its not present on device
......................................................................
Patch Set 2: Verified+1
(1 comment)
File src/mainboard/google/herobrine/mainboard.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-140402):
https://review.coreboot.org/c/coreboot/+/61716/comment/64d4c10a_159e5c8c
PS2, Line 111: /* Disable fingerprint sensor intialization as its not present on device */
'intialization' may be misspelled - perhaps 'initialization'?
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Change subject: qualcomm/sc7280: Add support for edp and mdp driver
......................................................................
Patch Set 12: Verified+1
(2 comments)
File src/mainboard/google/herobrine/mainboard.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-140401):
https://review.coreboot.org/c/coreboot/+/61342/comment/a62e4c28_7857fa17
PS12, Line 61: if (display_init_required()) {
suspect code indent for conditional statements (8, 24)
File src/soc/qualcomm/sc7280/display/edp_ctrl.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-140401):
https://review.coreboot.org/c/coreboot/+/61342/comment/3f36aae2_ab4a8a68
PS12, Line 863: ret = edp_start_link_train_2(ctrl,dpcd);
space required after that ',' (ctx:VxV)
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