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Change subject: soc/amd/cezanne: Update XHCI GPE to use constant
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Change subject: mb/google/skyrim: Store XHCI PCI BARs
......................................................................
Patch Set 11: Code-Review+2
(1 comment)
File src/mainboard/google/skyrim/mainboard.c:
https://review.coreboot.org/c/coreboot/+/68325/comment/6a30d2f6_7cede94e
PS6, Line 138:
> What's the concern with not returning early? If ELOG isn't selected then the BARs will be stored, bu […]
This suggestion was to eliminate the need to protect the smm_pci_bar_store_fill_bars() declaration with #IF CONFIG(ELOG).
If you return early, that's not needed.
This is moot after the refactoring though.
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Change subject: util/crossgcc/buildgcc: Disable LLVM_INCLUDE_{TESTS,EXAMPLES}
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util/crossgcc/buildgcc: Disable LLVM_INCLUDE_{TESTS,EXAMPLES}
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Change subject: util/crossgcc/buildgcc: Use one line per configure option
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Change subject: soc/amd/mendocino: Set up SoC-specific XHCI defines
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Patch Set 12: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/67938/comment/9545a98f_5a200b29
PS12, Line 10:
Nit: add "Enable SOC_AMD_COMMON_BLOCK_XHCI"
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Change subject: Docs: Add page for external resources
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Patch Set 1:
(1 comment)
File Documentation/external_docs.md:
https://review.coreboot.org/c/coreboot/+/70239/comment/bfc0c4b2_8a19ec7a
PS1, Line 11: ## General Information
```
* [Open Security Training](https://opensecuritytraining.info/Training.html),
[Open Security Training 2](https://p.ost2.fyi/):
Open course material for a variety of topics such as assembly, firmware, security, debugging, and more.
```
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Change subject: soc/amd/common/xhci: Add support for logging XHCI wake events
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Patch Set 12: Code-Review+2
(1 comment)
File src/soc/amd/common/block/include/amdblocks/xhci.h:
https://review.coreboot.org/c/coreboot/+/67936/comment/6f250f20_14c5462c
PS10, Line 13: #define XHCI_GEVENT GEVENT_31
> This definition is just for clarity. […]
Seems reasonable. Is this same GEVENT used for XHCI on all chips?
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