coreboot-gerrit December 2022

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: util/crossgcc/buildgcc: Use one line per configure option
by Felix Singer (Code Review) 01 Dec '22

01 Dec '22

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69941 ) Change subject: util/crossgcc/buildgcc: Use one line per configure option ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/69941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc39e4d0849d220d85e1d9ce92fc008fec610694 Gerrit-Change-Number: 69941 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Dec 2022 21:12:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/crossgcc/buildgcc: Put configure option before target dir
by Felix Singer (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Felix Singer, Paul Menzel. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69940 ) Change subject: util/crossgcc/buildgcc: Put configure option before target dir ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/69940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1b724f9c9b4d2a8ce166946794c1c0882ad1653 Gerrit-Change-Number: 69940 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 01 Dec 2022 21:12:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: device/xhci: Add struct for capability registers
by Martin Roth (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Robert Zieba, Raul Rangel, Karthik Ramasubramanian. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69915 ) Change subject: device/xhci: Add struct for capability registers ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If38bfde726bd4e5dd314456f25a2b08acd3cd20c Gerrit-Change-Number: 69915 Gerrit-PatchSet: 4 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 21:03:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex: Add MPTS method for WWAN over PCIe
by build bot (Jenkins) (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Tarun Tuli, Kapil Porwal. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70229 ) Change subject: mb/google/rex: Add MPTS method for WWAN over PCIe ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165021): https://review.coreboot.org/c/coreboot/+/70229/comment/353e91b0_c7d2cd76 PS1, Line 6: Possible long commit subject (prefer a maximum 65 characters) -- To view, visit https://review.coreboot.org/c/coreboot/+/70229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27ade63cfe0586aee9f03ba816b2590f14dcb610 Gerrit-Change-Number: 70229 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 20:56:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex: Add MPTS method for WWAN over PCIe
by Subrata Banik (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Tarun Tuli, Kapil Porwal. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70229 ) Change subject: mb/google/rex: Add MPTS method for WWAN over PCIe ...................................................................... mb/google/rex: Add MPTS method for WWAN over PCIe This patch generates the following for the mainboard: Scope (\_SB) { Method (MPTS, 1, Serialized) { Local0 = \_SB.PCI0.RP06.RTD3._STA () If ((Local0 == One)) { \_SB.PCI0.RP06.PXSX.DPTS (Arg0) } } } Change-Id: I27ade63cfe0586aee9f03ba816b2590f14dcb610 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/mainboard.c M src/mainboard/google/rex/variants/rex0/overridetree.cb 2 files changed, 58 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/70229/1 diff --git a/src/mainboard/google/rex/mainboard.c b/src/mainboard/google/rex/mainboard.c index f61af2c..bb64c63 100644 --- a/src/mainboard/google/rex/mainboard.c +++ b/src/mainboard/google/rex/mainboard.c @@ -5,10 +5,13 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <device/device.h> +#include <drivers/wwan/fm/chip.h> #include <ec/ec.h> #include <fw_config.h> #include <vendorcode/google/chromeos/chromeos.h> +WEAK_DEV_PTR(rp6_wwan); + static void mainboard_init(void *chip_info) { const struct pad_config *pads; @@ -47,8 +50,38 @@ acpigen_write_if_end(); } +static void mainboard_generate_wwan_shutdown(const struct device *dev) +{ + const struct drivers_wwan_fm_config *config = config_of(dev); + const struct device *parent = dev->bus->dev; + + if (!config) + return; + if (config->rtd3dev) { + acpigen_write_store(); + acpigen_emit_namestring(acpi_device_path_join(parent, "RTD3._STA")); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_if_lequal_op_int(LOCAL0_OP, ONE_OP); + { + acpigen_emit_namestring(acpi_device_path_join(dev, "DPTS")); + acpigen_emit_byte(ARG0_OP); + } + acpigen_write_if_end(); + } +} + static void mainboard_fill_ssdt(const struct device *dev) { + const struct device *wwan = DEV_PTR(rp6_wwan); + + if (wwan) { + acpigen_write_scope("\\_SB"); + acpigen_write_method_serialized("MPTS", 1); + mainboard_generate_wwan_shutdown(wwan); + acpigen_write_method_end(); /* Method */ + acpigen_write_scope_end(); /* Scope */ + } + acpigen_write_scope("\\_SB"); acpigen_write_method_serialized("MS0X", 1); mainboard_generate_s0ix_hook(); diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 8d1d528..97b8b84 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -468,7 +468,7 @@ register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)" register "add_acpi_dma_property" = "true" use rp6_rtd3 as rtd3dev - device generic 0 on end + device generic 0 alias rp6_wwan on end end end #PCIE6 WWAN card device ref gspi1 on -- To view, visit https://review.coreboot.org/c/coreboot/+/70229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27ade63cfe0586aee9f03ba816b2590f14dcb610 Gerrit-Change-Number: 70229 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/rex: Add probed fw_configs to SMBIOS OEM strings
by Subrata Banik (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Tarun Tuli, Kapil Porwal. Hello Tarun Tuli, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70228 to look at the new patch set (#2). Change subject: mb/google/rex: Add probed fw_configs to SMBIOS OEM strings ...................................................................... mb/google/rex: Add probed fw_configs to SMBIOS OEM strings Enable this feature, and it can use the probe statement in devicetree to cache of fw_config field as oem string. TEST=With CBI FW_CONFIG field set to 0x1561 localhost ~ # dmidecode -t 11 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0009, DMI type 11, 5 bytes OEM Strings String 1: AUDIO-MAX98357_ALC5682I_I2S String 2: CELLULAR-CELLULAR_PCIE String 3: UFC-UFC_MIPI String 4: WFC-WFC_MIPI String 5: DB_SD-SD_GL9755S Change-Id: I6cb35eb9c0fbe32764ca76bb7a929cc92fc38404 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/mainboard.c 1 file changed, 40 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/70228/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cb35eb9c0fbe32764ca76bb7a929cc92fc38404 Gerrit-Change-Number: 70228 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/rex: Implement S0ix hooks aka `MS0X` method
by Subrata Banik (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Utkarsh H Patel, Kapil Porwal, Ivy Jian, Sridhar Siricilla, Eric Lai. Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, Ivy Jian, Utkarsh H Patel, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70196 to look at the new patch set (#7). Change subject: mb/google/rex: Implement S0ix hooks aka `MS0X` method ...................................................................... mb/google/rex: Implement S0ix hooks aka `MS0X` method This patch ensures to be able to drive SYS_SLP_S0IX_L `low` based on the state of the system while `SLP_S0_L` signal is `low` (while the system is in S0ix). Implemented runtime ASL method (MS0X) being called by PEPD device _DSM to configure `SLP_S0_GATE (GPP_H14)` PIN at S0ix entry/exit. Scope (\_SB) { Method (MS0X, 1, Serialized) { If ((Arg0 == One)) { \_SB.PCI0.CTXS (0x75) } Else { \_SB.PCI0.STXS (0x75) } } BUG=b:256807255 TEST=Able to see SYS_SLP_S0IX_L goes low in S0ix. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ie6b5e066f228ea5dc79ae14dd803fc283fd248ce --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/mainboard.c M src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/gpio.h 4 files changed, 84 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/70196/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/70196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6b5e066f228ea5dc79ae14dd803fc283fd248ce Gerrit-Change-Number: 70196 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-CC: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: Docs: Add page for external resources
by Felix Singer (Code Review) 01 Dec '22

01 Dec '22

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[M] Change in coreboot[master]: Docs: Add page for external resources
by Felix Singer (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Martin L Roth, Maximilian Brune. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70239 ) Change subject: Docs: Add page for external resources ...................................................................... Patch Set 1: (3 comments) Patchset: PS1: Great idea! File Documentation/external_docs.md: https://review.coreboot.org/c/coreboot/+/70239/comment/58dd54ca_a17c29e3 PS1, Line 58: * Intel `[Architecture Software Developer Manuals](https://www.intel.com/content/www/us/en/developer/articles/technic… https://review.coreboot.org/c/coreboot/+/70239/comment/3a978862_76b0f7b4 PS1, Line 68: * [IOTools](https://github.com/adurbin/iotools) - Command line tools to access hardware registers ``` [UEFITool](https://github.com/LongSoft/UEFITool) [CHIPSEC](https://chipsec.github.io) ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/70239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf411e67bf865426b1a3b99ecbabed2302a7b738 Gerrit-Change-Number: 70239 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 20:39:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/var/gaelin: Configure audio in devicetree
by Felix Held (Code Review) 01 Dec '22

01 Dec '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69964 ) Change subject: mb/google/brya/var/gaelin: Configure audio in devicetree ...................................................................... mb/google/brya/var/gaelin: Configure audio in devicetree Refer to brask board to add audio settings for gaelin. BUG=b:253177160 BRANCH=firmware-brya-14505.B TEST=Able to verify audio playback on gaelin with kernel v5.10. Change-Id: Ibc8cacce6cb4b3e55fc7332bb9eb9ac20848fc5b Signed-off-by: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69964 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Derek Huang <derekhuang(a)google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/gaelin/overridetree.cb 1 file changed, 50 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Raymond Chung: Looks good to me, but someone else must approve Derek Huang: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/gaelin/overridetree.cb b/src/mainboard/google/brya/variants/gaelin/overridetree.cb index 57079f3..6a572d3f 100644 --- a/src/mainboard/google/brya/variants/gaelin/overridetree.cb +++ b/src/mainboard/google/brya/variants/gaelin/overridetree.cb @@ -160,6 +160,30 @@ end end end + device ref i2c0 on + chip drivers/i2c/nau8825 + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)" + register "jkdet_enable" = "1" + register "jkdet_pull_enable" = "0" + register "jkdet_pull_up" = "0" + register "jkdet_polarity" = "1" # ActiveLow + register "vref_impedance" = "2" # 125kOhm + register "micbias_voltage" = "6" # 2.754 + register "sar_threshold_num" = "4" + register "sar_threshold[0]" = "0x0C" + register "sar_threshold[1]" = "0x1C" + register "sar_threshold[2]" = "0x38" + register "sar_threshold[3]" = "0x60" + register "sar_hysteresis" = "1" + register "sar_voltage" = "6" + register "sar_compare_time" = "0" # 500ns + register "sar_sampling_time" = "0" # 2us + register "short_key_debounce" = "2" # 100ms + register "jack_insert_debounce" = "7" # 512ms + register "jack_eject_debounce" = "7" # 512ms + device i2c 1a on end + end # Audio Nau8825 + end # I2C0 device ref pcie_rp5 on # Enable PCIE 5 using clk 2 register "pch_pcie_rp[PCH_RP(5)]" = "{ @@ -212,5 +236,11 @@ end end end + device ref hda on + chip drivers/generic/alc1015 + register "hid" = ""RTL1015"" + device generic 0 on end + end # RT1015 Amplifier + end # Intel HDA end end -- To view, visit https://review.coreboot.org/c/coreboot/+/69964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc8cacce6cb4b3e55fc7332bb9eb9ac20848fc5b Gerrit-Change-Number: 69964 Gerrit-PatchSet: 4 Gerrit-Owner: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bruce Chiang <brucechiang(a)msi.corp-partner.google.com> Gerrit-CC: Eason Chang <easonchang(a)msi.corp-partner.google.com> Gerrit-CC: Eddy Lu <eddylu(a)ami.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit December 2022