coreboot-gerrit December 2022

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[S] Change in coreboot[master]: vboot: Allow for comparison of hash without zero-padding
by Julius Werner (Code Review) 01 Dec '22

01 Dec '22

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69762 ) Change subject: vboot: Allow for comparison of hash without zero-padding ...................................................................... vboot: Allow for comparison of hash without zero-padding Adjust asserts to allow to store and compare (at S3 resume) hashes without padding to maximum hash length / slot size. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: If6d46e0b58dbca86af56221b7ff2606ab2d1799a Reviewed-on: https://review.coreboot.org/c/coreboot/+/69762 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/ec/google/chromeec/vboot_storage.c M src/security/vboot/vboot_logic.c 2 files changed, 21 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/ec/google/chromeec/vboot_storage.c b/src/ec/google/chromeec/vboot_storage.c index f708b3e..63e1314 100644 --- a/src/ec/google/chromeec/vboot_storage.c +++ b/src/ec/google/chromeec/vboot_storage.c @@ -14,8 +14,8 @@ uint32_t lock_status; int num_slots; - /* Ensure the digests being saved match the EC's slot size. */ - assert(digest_size == EC_VSTORE_SLOT_SIZE); + /* Ensure the digests being saved does not exceed the EC's slot size. */ + assert(digest_size > 0 && digest_size <= EC_VSTORE_SLOT_SIZE); if (google_chromeec_vstore_write(slot, digest, digest_size)) return -1; diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 98a044c..f7b4801 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -86,7 +86,7 @@ uint8_t saved_hash[VBOOT_MAX_HASH_SIZE]; const size_t saved_hash_sz = sizeof(saved_hash); - assert(slot_hash_sz == saved_hash_sz); + assert(slot_hash_sz <= saved_hash_sz); printk(BIOS_DEBUG, "Platform is resuming.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/69762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6d46e0b58dbca86af56221b7ff2606ab2d1799a Gerrit-Change-Number: 69762 Gerrit-PatchSet: 7 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: vboot/vboot_common: Fix vboot_save_data() code exclusion guard
by Julius Werner (Code Review) 01 Dec '22

01 Dec '22

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69761 ) Change subject: vboot/vboot_common: Fix vboot_save_data() code exclusion guard ...................................................................... vboot/vboot_common: Fix vboot_save_data() code exclusion guard Compilers are not optimizing-out code correctly. This patch fixes incorrect behavior by splitting if statement and extracting code to another function, this allowing for better code size optimization and reduction of undefined references. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: Ia5330efeeb4cfd7477cf8f7f64c6abed68281e30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69761 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/security/vboot/vboot_common.c 1 file changed, 37 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index dd611d1..3c4957a 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -9,26 +9,33 @@ #include "antirollback.h" -void vboot_save_data(struct vb2_context *ctx) +static void save_secdata(struct vb2_context *ctx) { - if (!verification_should_run() && !(ENV_ROMSTAGE && CONFIG(VBOOT_EARLY_EC_SYNC)) - && (ctx->flags - & (VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED | VB2_CONTEXT_SECDATA_KERNEL_CHANGED))) - die("TPM writeback in " ENV_STRING "?"); - - if (ctx->flags & VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED && - (CONFIG(VBOOT_MOCK_SECDATA) || tlcl_lib_init() == VB2_SUCCESS)) { + if (ctx->flags & VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED + && (CONFIG(VBOOT_MOCK_SECDATA) || tlcl_lib_init() == VB2_SUCCESS)) { printk(BIOS_INFO, "Saving secdata firmware\n"); antirollback_write_space_firmware(ctx); ctx->flags &= ~VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED; } - if (ctx->flags & VB2_CONTEXT_SECDATA_KERNEL_CHANGED && - (CONFIG(VBOOT_MOCK_SECDATA) || tlcl_lib_init() == VB2_SUCCESS)) { + if (ctx->flags & VB2_CONTEXT_SECDATA_KERNEL_CHANGED + && (CONFIG(VBOOT_MOCK_SECDATA) || tlcl_lib_init() == VB2_SUCCESS)) { printk(BIOS_INFO, "Saving secdata kernel\n"); antirollback_write_space_kernel(ctx); ctx->flags &= ~VB2_CONTEXT_SECDATA_KERNEL_CHANGED; } +} + +void vboot_save_data(struct vb2_context *ctx) +{ + if (!verification_should_run() && !(ENV_ROMSTAGE && CONFIG(VBOOT_EARLY_EC_SYNC))) { + if (ctx->flags + & (VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED + | VB2_CONTEXT_SECDATA_KERNEL_CHANGED)) + die("TPM writeback in " ENV_STRING "?"); + } else { + save_secdata(ctx); + } if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) { printk(BIOS_INFO, "Saving nvdata\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/69761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5330efeeb4cfd7477cf8f7f64c6abed68281e30 Gerrit-Change-Number: 69761 Gerrit-PatchSet: 6 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: vboot/vboot_common: Fix vboot_save_data() code exclusion guard
by Julius Werner (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Jakub Czapiga. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69761 ) Change subject: vboot/vboot_common: Fix vboot_save_data() code exclusion guard ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69761/comment/504253e0_f4140f90 PS4, Line 12: reduction of undefined references. > I'm marking this comment as resolved due to no response for a week. Sorry sorry, have been swamped for a couple of weeks. Have looked at it now, can confirm the compiler is stupid here: ``` 0: 53 push %ebx 1: 83 ec 08 sub $0x8,%esp 4: 8b 5c 24 10 mov 0x10(%esp),%ebx # load ctx 8: 8b 03 mov (%ebx),%eax # load flags a: a9 02 04 00 00 test $0x402,%eax # test flags f: 74 0d je 1e <vboot_save_data+0x1e> (File Offset: 0xab) 11: 83 ec 0c sub $0xc,%esp # die path 14: 68 00 00 00 00 push $0x0 15: R_386_32 .rodata.vboot_save_data.str1.1 19: e8 fc ff ff ff call 1a <vboot_save_data+0x1a> (File Offset: 0xa7) 1a: R_386_PC32 die 1e: a8 02 test $0x2,%al # test KERNEL_SECDATA flag again even if we jumped over the die path 20: 74 25 je 47 <vboot_save_data+0x47> (File Offset: 0xd4) (CONFIG(VBOOT_MOCK_SECDATA) || tlcl_lib_init() == VB2_SUCCESS)) { 22: e8 fc ff ff ff call 23 <vboot_save_data+0x23> (File Offset: 0xb0) 23: R_386_PC32 tlcl_lib_init ``` Let's go with your solution. -- To view, visit https://review.coreboot.org/c/coreboot/+/69761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5330efeeb4cfd7477cf8f7f64c6abed68281e30 Gerrit-Change-Number: 69761 Gerrit-PatchSet: 5 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 22:11:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: kconfig2html: Denote that the script is python3
by Angel Pons (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Patrick Georgi, Martin L Roth. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69190 ) Change subject: kconfig2html: Denote that the script is python3 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d68873d86dc3f044238d921c10fc434a83a76f5 Gerrit-Change-Number: 69190 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 22:11:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: board-status: Implement handling of "Clone of"
by Angel Pons (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Patrick Georgi, Martin L Roth. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69184 ) Change subject: board-status: Implement handling of "Clone of" ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb728ebb5d0e98b0c8a59f3bd8803ce193a05e5f Gerrit-Change-Number: 69184 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 22:10:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: board-status: Remove shell version, update docs
by Angel Pons (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Patrick Georgi, Martin L Roth. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68960 ) Change subject: board-status: Remove shell version, update docs ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I532db49799eadf3214a70297c5fc84aa006bc3f7 Gerrit-Change-Number: 68960 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 22:10:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/common, alderlake: provide a list of D-states to enter LPM
by Eran Mitrani (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Eran Mitrani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70166 ) Change subject: soc/intel/common, alderlake: provide a list of D-states to enter LPM ...................................................................... Patch Set 7: (13 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/70166/comment/12dedd94_dc40a586 PS3, Line 7: soc/intel/common > and alderlake Done File src/soc/intel/alderlake/acpi.c: https://review.coreboot.org/c/coreboot/+/70166/comment/8a7eb829_0f52d391 PS3, Line 225: : min_sleep_state_t **get_min_sleep_state_array(int *size) : { : *size = ARRAY_SIZE(min_pci_sleep_states); : return &min_pci_sleep_states; : } > nit: you cab avoid having double point (IMO, we don't need) […] Done https://review.coreboot.org/c/coreboot/+/70166/comment/b1f8d2f9_3b42d1b7 PS3, Line 233: void soc_lpi_get_constraints(void *unused) : { : acpi_generate_lpi_constraint_table(); : } > Can't we remove this method itself? No.. It's implemented differently for previous generations in src/soc/intel/common/block/acpi/pep.c File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/70166/comment/a6979589_4277f7c0 PS3, Line 29: #define LPI_REVISION 0 : #define LPI_ENABLED 1 > may be enum? Done https://review.coreboot.org/c/coreboot/+/70166/comment/494c22d7_18a17967 PS3, Line 440: ** > __weak struct min_sleep_state *get_min_sleep_state_array(size_t *size) […] Done https://review.coreboot.org/c/coreboot/+/70166/comment/3145e674_9d88a407 PS3, Line 443: return NULL; > set size to 0 as we are returning NULL. Done https://review.coreboot.org/c/coreboot/+/70166/comment/caf62f12_b00f89f3 PS3, Line 448: min_sleep_state_t **min_pci_sleep_states; > size_t size; […] Done https://review.coreboot.org/c/coreboot/+/70166/comment/9aabd4c4_485579d4 PS3, Line 450: min_pci_sleep_states > shouldn't we do a NULL check here ? Done https://review.coreboot.org/c/coreboot/+/70166/comment/8d910adb_74c1dd50 PS3, Line 464: *min_pci_sleep_states)[i].pci_dev > state[i]. […] Done https://review.coreboot.org/c/coreboot/+/70166/comment/ef0fca31_ecdd4d92 PS3, Line 465: *min_pci_sleep_states)[i] > state[i]. […] Done https://review.coreboot.org/c/coreboot/+/70166/comment/89178ffb_6d025adc PS3, Line 486: > Need to handle a case when `num_entries` is 0 here. Done https://review.coreboot.org/c/coreboot/+/70166/comment/cf5a79cb_e5a220e4 PS3, Line 537: printk(BIOS_INFO, "Returning SoC specific constraint package for %d devices\n", num_entries); > u can drop this Done File src/soc/intel/common/block/include/intelblocks/acpi.h: https://review.coreboot.org/c/coreboot/+/70166/comment/c69b94a6_7c7a1eba PS3, Line 138: typedef > I would avoid doing typedef Done -- To view, visit https://review.coreboot.org/c/coreboot/+/70166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752 Gerrit-Change-Number: 70166 Gerrit-PatchSet: 7 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 22:04:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/common, alderlake: provide a list of D-states to enter LPM
by Eran Mitrani (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Tarun Tuli, Eran Mitrani. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70166 to look at the new patch set (#7). Change subject: soc/intel/common, alderlake: provide a list of D-states to enter LPM ...................................................................... soc/intel/common, alderlake: provide a list of D-states to enter LPM This was done previously for ADL. moving the code to common so it can be leveraged for other platforms (e.g. MTL) TEST=Built and tested on anahera by verifying SSDT contents Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752 Signed-off-by: Eran Mitrani <mitrani(a)google.com> --- M src/include/acpi/acpi.h M src/soc/intel/alderlake/acpi.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/acpi.h 4 files changed, 203 insertions(+), 156 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/70166/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/70166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752 Gerrit-Change-Number: 70166 Gerrit-PatchSet: 7 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[master]: ec/google/chromeec: Refresh ec_commands.h
by Nick Vaccaro (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Caveh Jalali. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69375 ) Change subject: ec/google/chromeec: Refresh ec_commands.h ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72620c4365fb1d53bb8161ecbbc041a32614e1ea Gerrit-Change-Number: 69375 Gerrit-PatchSet: 4 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Thu, 01 Dec 2022 22:00:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/common: provide a list of D-states to enter LPM
by Eran Mitrani (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Tarun Tuli, Eran Mitrani. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70166 to look at the new patch set (#6). Change subject: soc/intel/common: provide a list of D-states to enter LPM ...................................................................... soc/intel/common: provide a list of D-states to enter LPM This was done previously for ADL. moving the code to common so it can be leveraged for other platforms (e.g. MTL) TEST=Built and tested on anahera by verifying SSDT contents Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752 Signed-off-by: Eran Mitrani <mitrani(a)google.com> --- M src/include/acpi/acpi.h M src/soc/intel/alderlake/acpi.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/acpi.h 4 files changed, 203 insertions(+), 156 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/70166/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/70166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752 Gerrit-Change-Number: 70166 Gerrit-PatchSet: 6 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2022