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Utkarsh H Patel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70196 )
Change subject: mb/google/rex: Implement S0ix hooks aka `MS0X` method
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/70196/comment/ee0f3b5e_466b9c8f
PS5, Line 10: on the state of the system while `SKL_S0_L` signal is `low` (while
SLP_S0_L
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Attention is currently required from: Kapil Porwal, Ivy Jian, Sridhar Siricilla, Eric Lai, Utkarsh H Patel.
Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, Ivy Jian, Utkarsh H Patel, Eric Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/70196
to look at the new patch set (#5).
Change subject: mb/google/rex: Implement S0ix hooks aka `MS0X` method
......................................................................
mb/google/rex: Implement S0ix hooks aka `MS0X` method
This patch ensures to be able to drive SYS_SLP_S0IX_L `low` based
on the state of the system while `SKL_S0_L` signal is `low` (while
the system is in S0ix).
Implemented runtime ASL method (MS0X) being called by PEPD device
_DSM to configure `SLP_S0_GATE (GPP_H14)` PIN at S0ix entry/exit.
Scope (\_SB)
{
Method (MS0X, 1, Serialized)
{
If ((Arg0 == One))
{
\_SB.PCI0.CTXS (0x75)
}
Else
{
\_SB.PCI0.STXS (0x75)
}
}
BUG=b:256807255
TEST=Able to see SYS_SLP_S0IX_L goes low in S0ix.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ie6b5e066f228ea5dc79ae14dd803fc283fd248ce
---
M src/mainboard/google/rex/Kconfig
M src/mainboard/google/rex/mainboard.c
M src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/gpio.h
4 files changed, 84 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/70196/5
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Attention is currently required from: Subrata Banik, Kapil Porwal, Ivy Jian, Eric Lai, Utkarsh H Patel.
Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, Ivy Jian, Utkarsh H Patel, Eric Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/70196
to look at the new patch set (#4).
Change subject: mb/google/rex: Implement S0ix hooks aka `MS0X` method
......................................................................
mb/google/rex: Implement S0ix hooks aka `MS0X` method
This patch ensures to be able to drive SYS_SLP_S0IX_L `low` based
on the state of the system while `SKL_S0_L` signal is `low` (while
the system is in S0ix).
Implemeted runtime ASL method (MS0X) being called by PEPD device
_DSM to configure `SLP_S0_GATE (GPP_H14)` PIN at S0ix entry/exit.
Scope (\_SB)
{
Method (MS0X, 1, Serialized)
{
If ((Arg0 == One))
{
\_SB.PCI0.CTXS (0x75)
}
Else
{
\_SB.PCI0.STXS (0x75)
}
}
BUG=b:256807255
TEST=Able to see SYS_SLP_S0IX_L goes low in S0ix.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ie6b5e066f228ea5dc79ae14dd803fc283fd248ce
---
M src/mainboard/google/rex/Kconfig
M src/mainboard/google/rex/mainboard.c
M src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/gpio.h
4 files changed, 84 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/70196/4
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Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69852 )
Change subject: util/amdfwtool: Deal with psp position in flash offset directly
......................................................................
Patch Set 4:
(1 comment)
File src/soc/amd/common/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/69852/comment/92e80956_7931813e
PS4, Line 25: $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 1 $(CONFIG_AMD_FWM_POSITION))
> > would it make sense to add flash offset support to cbfstool? It already knows the flash size from […]
I agree with what Karthik's saying here. The values that are listed all assume offsets from the bottom of a 16MiB ROM space. When changing that to starting at the bottom of an 8MiB ROM, the 0xC20000 needs to become 0x420000. I don't think we want that.
So either you need to subtract the rom size in two different locations,
Once as you are to adjust the start of the rom area
and again subtracting (16Mib-ROM size) to correctly adjust the location selected.
Since we have a set 16MiB ROM area now, I think we can just keep the actual ROM size out of the equation (Though maybe we want to check that the selected space is inside the ROM).
For upcoming chips, my understanding is that this is all going to go away, and the 16MiB ROM (or larger) becomes mandatory, and the only supported offset is 0x020000.
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Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70215 )
Change subject: google/skyrim/Kconfig: Enable DPTC for Frostflow
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> I'm assuming the STT params are all set?
Yeah. I moved everything to the base `devicetree.cb` with this CL:
69904: mb/google/skyrim: Move common DPTC values to devicetree.cb | https://review.coreboot.org/c/coreboot/+/69904
That should give everything a starting point, which can be tuned in the appropriate `overridetree.cb`.
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Change subject: google/skyrim/Kconfig: Enable DPTC for Morthal
......................................................................
Patch Set 1: Code-Review+2
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Change subject: google/skyrim/Kconfig: Enable DPTC for Frostflow
......................................................................
Patch Set 1: Code-Review+2
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