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Change subject: mb/google/nissa/var/xivu: Fine-tune eMMC DLL
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69892/comment/26ce9b1b_505915a1
PS8, Line 12:
> nit:extra space
deleted the extra space.
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Hello build bot (Jenkins), Tarun Tuli, Jamie Chen, Henry Sun, Kangheui Won, Reka Norman, Nick Vaccaro, Eric Lai, Shou-Chieh Hsu,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/nissa/var/xivu: Fine-tune eMMC DLL
......................................................................
mb/google/nissa/var/xivu: Fine-tune eMMC DLL
Fine-tune eMMC DLL based on Xivu EVT system.
BUG=b:256538132
TEST=executed 3000 cycles of cold boot successfully
Change-Id: Iaa8338fd0faa0e01f42ee77dea135c7a241ed3be
Signed-off-by: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/xivu/overridetree.cb
1 file changed, 60 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/69892/9
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Change subject: drivers/mrc_cache: Prevent printing errors in expected use cases
......................................................................
Patch Set 2:
(3 comments)
File src/drivers/mrc_cache/mrc_cache.c:
https://review.coreboot.org/c/coreboot/+/69542/comment/02712c7e_0590a12c
PS1, Line 159: printk(BIOS_WARNING, "MRC: failed to locate region type %d\n", type);
> I feel like you might even want to go further and make this BIOS_DEBUG (with a comment explaining wh […]
Done
https://review.coreboot.org/c/coreboot/+/69542/comment/8eb5218e_f2e13855
PS1, Line 180: BIOS_WARNING
> INFO maybe?
Done
https://review.coreboot.org/c/coreboot/+/69542/comment/300c7503_2d446dc0
PS1, Line 275: printk(BIOS_WARNING, "MRC: invalid header in '%s'\n", name);
> Maybe just remove this? Not sure why we need to print again here if the function already prints in a […]
I thought the `name` might be useful. However, there's already a debug message printed in `fmap_locate_area`, so removing this should be fine.
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Hello Shelley Chen, build bot (Jenkins), Julius Werner,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: drivers/mrc_cache: Prevent printing errors in expected use cases
......................................................................
drivers/mrc_cache: Prevent printing errors in expected use cases
The following are considered "expected" situations, where we shouldn't
print error messages as in other unexpected errors:
1. When the previous boot is in recovery mode, under certain config
combination the normal MRC cache would have been invalidated.
Therefore the "couldn't read metadata" error is expected to show in
the current normal boot. Special-case this situation by printing a
different message.
2. If the platform doesn't have recovery cache (!HAS_RECOVERY_MRC_CACHE)
and vboot starts before romstage (!VBOOT_STARTS_IN_ROMSTAGE), then
there should be no region for recovery cache. In this case, "failed
to locate region type 0" will be shown. Since it's pretty clear from
the code that this is the only case for the error to happen, simply
change it to BIOS_DEBUG. Also remove a duplicate message when
mrc_header_valid() fails.
BUG=b:257401937
TEST=emerge-corsola coreboot
TEST=Ran `cbmem -1 | grep ERROR` in recovery boot
TEST=Ran `cbmem -1 | grep ERROR` in normal boot following recovery boot
BRANCH=corsola
Change-Id: Ia942eeecaca3f6b2b90bac725279d2dc6174e0fd
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/drivers/mrc_cache/mrc_cache.c
1 file changed, 48 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/69542/2
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Change subject: mb/intel/adlrvp: Add RTD3 support for PCIe slot1
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/intel/adlrvp: Add RTD3 support for PCIe slot1
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> pls wait a bit, might need a change to add power enable pin.
Add more change to turn off/on 3.3v main power with sufficient delay between powering on the device and its #PERST deassertion.
changes verified.
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Change subject: mb/google/nissa/var/xivu: Fine-tune eMMC DLL
......................................................................
Patch Set 8: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69892/comment/e33cb4c4_b85ca578
PS8, Line 12:
nit:extra space
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Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69931 )
(
6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: mb/google/skyrim/var/frostflow: Enable DPTC support
......................................................................
mb/google/skyrim/var/frostflow: Enable DPTC support
Enable DPTC support for frostflow.
BUG=b:257187831
TEST=emerge-skyrim coreboot
Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com>
Change-Id: Iac7b8789a5189827fe98cb06328d666300841a5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69931
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---
M src/mainboard/google/skyrim/Kconfig.name
1 file changed, 21 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Frank Wu: Looks good to me, approved
Dtrain Hsu: Looks good to me, approved
Tim Van Patten: Looks good to me, approved
diff --git a/src/mainboard/google/skyrim/Kconfig.name b/src/mainboard/google/skyrim/Kconfig.name
index 3146819..8bfbe3f 100644
--- a/src/mainboard/google/skyrim/Kconfig.name
+++ b/src/mainboard/google/skyrim/Kconfig.name
@@ -17,6 +17,7 @@
config BOARD_GOOGLE_FROSTFLOW
bool "-> Frostflow"
select BOARD_GOOGLE_BASEBOARD_SKYRIM
+ select SOC_AMD_COMMON_BLOCK_ACPI_DPTC
select DRIVERS_GENESYSLOGIC_GL9755
config BOARD_GOOGLE_CRYSTALDRIFT
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