coreboot-gerrit December 2022

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[M] Change in coreboot[master]: drivers/ipmi: Retry ipmi_get_device_id in ipmi_kcs_init
by Johnny Lin (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, Paul Menzel, Christian Walter, Nill Ge, TangYiwei, Shelly Chang. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69310 ) Change subject: drivers/ipmi: Retry ipmi_get_device_id in ipmi_kcs_init ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69310/comment/907b4e7d_ad10d61a PS2, Line 11: > In addition to Johnny said, BMC does not reset during host warm reset and host DC cycle, so IPMI han […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/69310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b972c905fb0f8223570212432a4a10bd715f3f7 Gerrit-Change-Number: 69310 Gerrit-PatchSet: 3 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 04:09:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/var/marasov: update gpio table for EVT
by build bot (Jenkins) (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Tarun Tuli. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70236 ) Change subject: mb/google/brya/var/marasov: update gpio table for EVT ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/marasov/gpio.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165035): https://review.coreboot.org/c/coreboot/+/70236/comment/75e3b04f_3a5f2aa9 PS1, Line 15: trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/70236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5a73126737a3abbe6f0ef37276ce20f687b47fc Gerrit-Change-Number: 70236 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 04:03:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/var/marasov: update gpio table for EVT
by Frank Chu (Code Review) 02 Dec '22

02 Dec '22

Frank Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70236 ) Change subject: mb/google/brya/var/marasov: update gpio table for EVT ...................................................................... mb/google/brya/var/marasov: update gpio table for EVT BUG=b:260565911 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: Id5a73126737a3abbe6f0ef37276ce20f687b47fc --- M src/mainboard/google/brya/variants/marasov/gpio.c 1 file changed, 153 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/70236/1 diff --git a/src/mainboard/google/brya/variants/marasov/gpio.c b/src/mainboard/google/brya/variants/marasov/gpio.c index a6ebe95..67f606e 100644 --- a/src/mainboard/google/brya/variants/marasov/gpio.c +++ b/src/mainboard/google/brya/variants/marasov/gpio.c @@ -6,8 +6,19 @@ /* Pad configuration in ramstage */ static const struct pad_config override_gpio_table[] = { + /* A5 : ESPI_ALERT0# ==> NC */ + PAD_NC(GPP_A5, NONE), + /* A6 : ESPI_ALERT1# ==> NC */ + PAD_NC(GPP_A6, NONE), + /* A7 : SRCCLK_OE7# ==> NC */ + PAD_NC(GPP_A7, NONE), + /* A8 : WWAN_RF_DISABLE_ODL ==> NC */ PAD_NC(GPP_A8, NONE), + /* A9 : ESPI_CLK ==> ESPI_CLK */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* A10 : ESPI_RESET# ==> ESPI_PCH_RST_EC_L */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* A12 : EN_PP3300_WWAN ==> NC */ PAD_NC(GPP_A12, NONE), /* A19 : USB_C2_AUX_DC_P ==> NC */ @@ -18,20 +29,60 @@ PAD_NC(GPP_A21, NONE), /* A22 : USB_C1_AUX_DC_N ==> NC */ PAD_NC(GPP_A22, NONE), + /* B2 : GPP_B2(TP97) ==> GPP_B2(TP1712) */ + PAD_NC(GPP_B2, NONE), + /* B3 : PROC_GP2 ==> NC */ + PAD_NC(GPP_B3, NONE), /* B5 : PCH_I2C_MISC_SDA ==> NC */ PAD_NC(GPP_B5, NONE), /* B6 : PCH_I2C_MISC_SCL ==> NC */ PAD_NC(GPP_B6, NONE), + /* B7 : PCH_I2C_TCHSCR_SDA ==> PCH_I2C_TCHSCR_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : PCH_I2C_TCHSCR_SCL ==> PCH_I2C_TCHSCR_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), + /* B15 : FP_USER_PRES_FP_L ==> NC */ + PAD_NC(GPP_B15, NONE), + /* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */ + PAD_CFG_NF_LOCK(GPP_B23, DN_20K, NF2, LOCK_CONFIG), + /* C3 : EN_UCAM_PWR ==> EN_UCAM_PWR(TP1103) */ + PAD_NC(GPP_C3, NONE), + /* C4 : EN_UCAM_SENR_PWR ==> EN_UCAM_SENR_PWR(TP1104) */ + PAD_NC(GPP_C4, NONE), + /* D0 : ISH_GP0 ==> NC */ + PAD_NC(GPP_D0, NONE), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC(GPP_D3, NONE), /* D5 : WWAN_DPR_SAR_ODL ==> NC */ PAD_NC(GPP_D5, NONE), /* D8 : SD_CLKREQ_ODL ==> NC */ PAD_NC(GPP_D8, NONE), /* D9 : USB_C2_LSX_TX ==> NC */ PAD_NC(GPP_D9, NONE), - /* D14 : SPKR_INT_L ==> NC */ + /* D10 : ISH_SPI_CLK ==> NC */ + PAD_NC(GPP_D10, NONE), + /* D13 : ISH_UART0_RXD ==> NC */ + PAD_NC(GPP_D13, NONE), + /* D14 : ISH_UART0_TXD ==> NC */ PAD_NC(GPP_D14, NONE), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_NC(GPP_D15, NONE), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_NC(GPP_D16, NONE), + /* D17 : UART1_RXD ==> NC */ + PAD_NC(GPP_D17, NONE), + /* D18 : UART1_TXD ==> NC */ + PAD_NC(GPP_D18, NONE), /* E0 : WWAN_PERST_L ==> NC */ PAD_NC(GPP_E0, NONE), + /* E3 : PROC_GP0 ==> NC */ + PAD_NC(GPP_E3, NONE), + /* E4 : SATA_DEVSLP0 ==> NC */ + PAD_NC(GPP_E4, NONE), + /* E5 : SATA_DEVSLP1 ==> NC */ + PAD_NC(GPP_E5, NONE), + /* E7 : PROC_GP1 ==> NC */ + PAD_NC(GPP_E7, NONE), /* E10 : WWAN_CONFIG0 ==> NC */ PAD_NC(GPP_E10, NONE), /* E16 : WWAN_RST_L ==> NC */ @@ -40,26 +91,53 @@ PAD_CFG_GPI(GPP_E17, NONE, DEEP), /* E18 : USB_C0_LSX_TX ==> NC */ PAD_NC(GPP_E18, NONE), + /* E19 : DDP1_CTRLDATA ==> NC */ + PAD_NC(GPP_E19, NONE), /* E20 : USB_C1_LSX_TX ==> NC */ PAD_NC(GPP_E20, NONE), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC(GPP_E21, NONE), /* F6 : WWAN_WLAN_COEX3 ==> NC */ PAD_NC(GPP_F6, NONE), + /* F19 : GPP_F19(TP93) ==> NC */ + PAD_NC(GPP_F19, NONE), + /* F20 : UCAM_RST_L ==> NC */ + PAD_NC(GPP_F20, NONE), /* F21 : WWAN_FCPO_L ==> NC */ PAD_NC(GPP_F21, NONE), - /* H8 : WWAN_WLAN_COEX1 ==> NC */ - PAD_NC(GPP_H8, NONE), - /* H9 : WWAN_WLAN_COEX2 ==> NC */ - PAD_NC(GPP_H9, NONE), + /* F23 : NC */ + PAD_CFG_NF_LOCK(GPP_F23, NONE, NF1, LOCK_CONFIG), + /* H8 : WWAN_WLAN_COEX1 ==> PCB_ID0(NC) */ + PAD_CFG_GPI_LOCK(GPP_H8, NONE, LOCK_CONFIG), + /* H9 : WWAN_WLAN_COEX2 ==> PCB_ID1(NC) */ + PAD_CFG_GPI_LOCK(GPP_H9, NONE, LOCK_CONFIG), + /* H12 : I2C7_SDA ==> NC */ + PAD_NC(GPP_H12, NONE), + /* H19 : SRCCLKREQ4# ==> NC */ + PAD_NC(GPP_H19, NONE), /* H21 : UCAM_MCLK ==> NC */ PAD_NC(GPP_H21, NONE), /* H22 : WCAM_MCLK ==> NC */ PAD_NC(GPP_H22, NONE), /* H23 : WWAN_CLKREQ_ODL ==> NC */ PAD_NC(GPP_H23, NONE), - /* S0 : SDW_HP_CLK_R ==> NC */ - PAD_NC(GPP_S0, NONE), - /* S1 : SDW_HP_DATA_R ==> NC */ - PAD_NC(GPP_S1, NONE), + /* R4 : HDA_RST# ==> NC */ + PAD_NC(GPP_R4, NONE), + /* R5 : HDA_SDI1 ==> NC */ + PAD_NC(GPP_R5, NONE), + /* R6 : I2S2_TXD ==> I2S_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), + /* R7 : I2S2_RXD ==> I2S_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), + /* S0 : SNDW0_CLK ==> SDW_HP_CLK_R */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), + /* S1 : SNDW0_DATA ==> SDW_HP_DATA_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), + /* S2 : SNDW1_CLK ==> DMIC_CLK0_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), + + /* S3 : SNDW1_DATA ==> NC */ + PAD_NC(GPP_S3, NONE), /* S4 : SDW_SPKR_CLK ==> NC */ PAD_NC(GPP_S4, NONE), /* S5 : SDW_SPKR_DATA ==> NC */ @@ -68,13 +146,65 @@ PAD_NC(GPP_S6, NONE), /* S7 : DMIC_DATA1_R ==> NC */ PAD_NC(GPP_S7, NONE), + /* GPD11: LANPHYC ==> NC */ + PAD_NC(GPD11, NONE), + }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* A13 : GSC_PCH_INT_ODL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : SSD_PERST_L ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* B7 : PCH_I2C_TCHSCR_SDA ==> PCH_I2C_TCHSCR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : PCH_I2C_TCHSCR_SCL ==> PCH_I2C_TCHSCR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + + /* + * D1 : FP_RST_ODL ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : EN_FP_PWR ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D11 : EN_PP3300_SSD ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* E0 : WWAN_PERST_L ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E13 : MEM_CH_SEL ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E15 : PCH_WP_OD ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* E16 : WWAN_RST_L ==> NC */ + PAD_NC(GPP_E16, NONE), + /* F18 : EC_IN_RW_OD ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : PCH_I2C_TPM_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : PCH_I2C_TPM_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H10 : UART_PCH_RX_DBG_TX ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART_PCH_TX_DBG_RX ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : EN_PP3300_SD ==> EN_PP3300_SD(TP1201) */ + PAD_NC(GPP_H13, UP_20K), }; static const struct pad_config romstage_gpio_table[] = { + /* B4 : SSD_PERST_L ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + + /* D1 : FP_RST_ODL ==> FP_RST_ODL */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : EN_FP_PWR ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 0, DEEP), }; const struct pad_config *variant_gpio_override_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/70236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5a73126737a3abbe6f0ef37276ce20f687b47fc Gerrit-Change-Number: 70236 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/brya/var/marasov: override mem_cfg to lp5x
by Frank Chu (Code Review) 02 Dec '22

02 Dec '22

Frank Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70235 ) Change subject: mb/google/brya/var/marasov: override mem_cfg to lp5x ...................................................................... mb/google/brya/var/marasov: override mem_cfg to lp5x Drop the __weak qualifier as this function is not overridden. BUG=b:260565911 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: Ica25b2bc4325ff9d27be672926b4e3b550c86e96 --- M src/mainboard/google/brya/variants/marasov/memory.c 1 file changed, 20 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/70235/1 diff --git a/src/mainboard/google/brya/variants/marasov/memory.c b/src/mainboard/google/brya/variants/marasov/memory.c index fb7c748..f05f407 100644 --- a/src/mainboard/google/brya/variants/marasov/memory.c +++ b/src/mainboard/google/brya/variants/marasov/memory.c @@ -70,12 +70,12 @@ .UserBd = BOARD_TYPE_MOBILE, }; -const struct mb_cfg *__weak variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &baseboard_memcfg; } -int __weak variant_memory_sku(void) +int variant_memory_sku(void) { /* * Memory configuration board straps @@ -92,7 +92,7 @@ return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); } -bool __weak variant_is_half_populated(void) +bool variant_is_half_populated(void) { /* * Ideally half_populated is used in platforms with multiple channels to @@ -106,7 +106,7 @@ return gpio_get(GPP_E13); } -void __weak variant_get_spd_info(struct mem_spd *spd_info) +void variant_get_spd_info(struct mem_spd *spd_info) { spd_info->topo = MEM_TOPO_MEMORY_DOWN; spd_info->cbfs_index = variant_memory_sku(); -- To view, visit https://review.coreboot.org/c/coreboot/+/70235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica25b2bc4325ff9d27be672926b4e3b550c86e96 Gerrit-Change-Number: 70235 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: [TEST ONLY] test upload code
by Jamie Chen (Code Review) 02 Dec '22

02 Dec '22

Jamie Chen has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/70249 ) Change subject: [TEST ONLY] test upload code ...................................................................... Abandoned only for test -- To view, visit https://review.coreboot.org/c/coreboot/+/70249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92688006fd5f1abdb23fb5098eff4941555cd885 Gerrit-Change-Number: 70249 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: [TEST ONLY] test upload code
by Jamie Chen (Code Review) 02 Dec '22

02 Dec '22

Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70249 ) Change subject: [TEST ONLY] test upload code ...................................................................... [TEST ONLY] test upload code Change-Id: I92688006fd5f1abdb23fb5098eff4941555cd885 Signed-off-by: jamie_chen <jamie_chen(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/xivu/overridetree.cb 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/70249/1 diff --git a/src/mainboard/google/brya/variants/xivu/overridetree.cb b/src/mainboard/google/brya/variants/xivu/overridetree.cb index bfaa639..de4d480 100644 --- a/src/mainboard/google/brya/variants/xivu/overridetree.cb +++ b/src/mainboard/google/brya/variants/xivu/overridetree.cb @@ -98,7 +98,7 @@ .speed = I2C_SPEED_FAST_PLUS, .scl_lcnt = 55, .scl_hcnt = 30, - .sda_hold = 7, + .sda_hold = 8, } }, .i2c[1] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/70249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92688006fd5f1abdb23fb5098eff4941555cd885 Gerrit-Change-Number: 70249 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/brya/var/marasov: Add the FIVR configurations
by Frank Chu (Code Review) 02 Dec '22

02 Dec '22

Frank Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70233 ) Change subject: mb/google/brya/var/marasov: Add the FIVR configurations ...................................................................... mb/google/brya/var/marasov: Add the FIVR configurations This patch enables V1p05 and Vnn external bypass VRs for Banshee. BUG=b:260565911 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: Id28305b02e86f5ac55382ac6d2bd5e0453aae9b4 --- M src/mainboard/google/brya/variants/marasov/overridetree.cb 1 file changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/70233/1 diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb index 70787c6..f2b8ed9 100644 --- a/src/mainboard/google/brya/variants/marasov/overridetree.cb +++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb @@ -49,6 +49,20 @@ }, }" register "sagv" = "SaGv_Enabled" + + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1250, + }" register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C2] = PchSerialIoDisabled, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/70233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id28305b02e86f5ac55382ac6d2bd5e0453aae9b4 Gerrit-Change-Number: 70233 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: drivers/ocp: add VPD processing framework
by Johnny Lin (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Marc Jones, Jonathan Zhang, Paul Menzel, Angel Pons, Johnny Li, Shuming Chu (Shuming), Tim Chu. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68784 ) Change subject: drivers/ocp: add VPD processing framework ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I705bea348b1611f25ccbd798b77cfee22ec30f0f Gerrit-Change-Number: 68784 Gerrit-PatchSet: 6 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 03:25:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: acpi/acpi.c: update ACPI table revisions
by Tim Wawrzynczak (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Lance Zhao, Jonathan Zhang, Angel Pons. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70245 ) Change subject: acpi/acpi.c: update ACPI table revisions ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Looks like right now only Xeon uses these two tables? -- To view, visit https://review.coreboot.org/c/coreboot/+/70245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecc3a9892b0f8093013b2a426749e2ec5c00803b Gerrit-Change-Number: 70245 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 03:24:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/marasov: Adjust I2C speed
by Frank Chu (Code Review) 02 Dec '22

02 Dec '22

Frank Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70232 ) Change subject: mb/google/brya/var/marasov: Adjust I2C speed ...................................................................... mb/google/brya/var/marasov: Adjust I2C speed Adjust I2C speed for codec, TPM, touchpad, touchscreen. BUG=b:260565911 TEST=Built and verified adjusted I2C speed Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: Idcec6e401992d30dff01940c50473cba48cffc19 --- M src/mainboard/google/brya/variants/marasov/overridetree.cb 1 file changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/70232/1 diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb index 70787c6..14c2474 100644 --- a/src/mainboard/google/brya/variants/marasov/overridetree.cb +++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb @@ -36,16 +36,28 @@ register "common_soc_config" = "{ .i2c[0] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, .i2c[1] = { .early_init = 1, .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, .i2c[3] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, .i2c[5] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, }" register "sagv" = "SaGv_Enabled" -- To view, visit https://review.coreboot.org/c/coreboot/+/70232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcec6e401992d30dff01940c50473cba48cffc19 Gerrit-Change-Number: 70232 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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