coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

1 participants
7286 discussions

[M] Change in coreboot[master]: mb/intel/adlrvp: Add RTD3 support for PCIe slot1
by Cliff Huang (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Cliff Huang. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70119 ) Change subject: mb/intel/adlrvp: Add RTD3 support for PCIe slot1 ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Patchset: PS1: pls wait a bit, might need a change to add power enable pin. -- To view, visit https://review.coreboot.org/c/coreboot/+/70119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb7d207a7ec3763bad3e82522e86a825c1ed00b6 Gerrit-Change-Number: 70119 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Tue, 29 Nov 2022 22:34:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/alderlake: skip external buses for D-states list
by Eran Mitrani (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik. Hello Tarun Tuli, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70163 to look at the new patch set (#3). Change subject: soc/intel/alderlake: skip external buses for D-states list ...................................................................... soc/intel/alderlake: skip external buses for D-states list The devices in the list that was introduced in commit c66ea9857768 ("soc/intel/alderlake: provide a list of D-states to enter LPM") are all internal. This CL skips the external buses (which caused the addition of packages to non-existant paths such as "_SB.PCI0.RP1.MCHC", and warnings from the kernel) BUG=b:231582182 TEST=Built and tested on anahera by verifying SSDT contents Change-Id: I3785b2b2af85d96e2e1296b6cfdefcd72080b5fe Signed-off-by: Eran Mitrani <mitrani(a)google.com> --- M src/soc/intel/alderlake/acpi.c 1 file changed, 22 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/70163/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/70163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3785b2b2af85d96e2e1296b6cfdefcd72080b5fe Gerrit-Change-Number: 70163 Gerrit-PatchSet: 3 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: soc/intel/alderlake: skip external buses for D-states list
by Eran Mitrani (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik. Hello Tarun Tuli, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70163 to look at the new patch set (#2). Change subject: soc/intel/alderlake: skip external buses for D-states list ...................................................................... soc/intel/alderlake: skip external buses for D-states list The devices in the list that was introduced in commit c66ea9857768 ("soc/intel/alderlake: provide a list of D-states to enter LPM") are all internal. This CL skips the external buses. (which caused the addition of packages to non-existant paths such as "_SB.PCI0.RP1.MCHC", and warnings from the kernel) BUG=b:231582182 TEST=Built and tested on anahera by verifying SSDT contents Change-Id: I3785b2b2af85d96e2e1296b6cfdefcd72080b5fe Signed-off-by: Eran Mitrani <mitrani(a)google.com> --- M src/soc/intel/alderlake/acpi.c 1 file changed, 22 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/70163/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3785b2b2af85d96e2e1296b6cfdefcd72080b5fe Gerrit-Change-Number: 70163 Gerrit-PatchSet: 2 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: mb/google/nissa/pujjo: Add new audio sku configure
by Reka Norman (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Tarun Tuli, Kangheui Won, Shou-Chieh Hsu, Leo Chou. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70131 ) Change subject: mb/google/nissa/pujjo: Add new audio sku configure ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9ddc683945002a0b19efd67006e1983b2eb9f2d Gerrit-Change-Number: 70131 Gerrit-PatchSet: 2 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jynn Chen <jynn.chen(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin3 Yang <Kevin3.Yang(a)lcfuturecenter.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Tue, 29 Nov 2022 22:24:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/herobrine: Mask out upper bits from sku_id()
by Shelley Chen (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Paul Menzel, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70164 ) Change subject: mb/google/herobrine: Mask out upper bits from sku_id() ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/herobrine/mainboard.c: https://review.coreboot.org/c/coreboot/+/70164/comment/f5700cf6_4020de77 PS1, Line 98: 0x1F > Lowercase? 0x1f Done -- To view, visit https://review.coreboot.org/c/coreboot/+/70164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e786ec392b5e1484cb2ff6d83a8d4fdd698950c Gerrit-Change-Number: 70164 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 29 Nov 2022 22:15:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/herobrine: Mask out upper bits from sku_id()
by Shelley Chen (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Shelley Chen, Julius Werner. Hello Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70164 to look at the new patch set (#2). Change subject: mb/google/herobrine: Mask out upper bits from sku_id() ...................................................................... mb/google/herobrine: Mask out upper bits from sku_id() When retrieving the SKU id bits through the sku_id() function in mainboard_needs_pcie_init(), we only want the values in the lower 5 bits as we can only represent SKU id up to 27. Everything in the higher bits should be masked out because they are not needed. BUG=b:254281839 BRANCH=None TEST=Make sure that NVMe is not initialized Tested on a herobrine board with SKU id 0 Change-Id: I0e786ec392b5e1484cb2ff6d83a8d4fdd698950c Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/herobrine/mainboard.c 1 file changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/70164/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e786ec392b5e1484cb2ff6d83a8d4fdd698950c Gerrit-Change-Number: 70164 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: mb/google/brya: add missing devices to DSDT
by Eran Mitrani (Code Review) 29 Nov '22

29 Nov '22

Eran Mitrani has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/69392 ) Change subject: mb/google/brya: add missing devices to DSDT ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/69392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82d53913c8da07b093e479ed8e12fda8c9990e3d Gerrit-Change-Number: 69392 Gerrit-PatchSet: 6 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: abandon

1 0

[S] Change in coreboot[master]: mb/google/herobrine: Mask out upper bits from sku_id()
by Paul Menzel (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Shelley Chen, Julius Werner. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70164 ) Change subject: mb/google/herobrine: Mask out upper bits from sku_id() ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/herobrine/mainboard.c: https://review.coreboot.org/c/coreboot/+/70164/comment/829c4403_98985030 PS1, Line 98: 0x1F Lowercase? 0x1f -- To view, visit https://review.coreboot.org/c/coreboot/+/70164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e786ec392b5e1484cb2ff6d83a8d4fdd698950c Gerrit-Change-Number: 70164 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 29 Nov 2022 22:12:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/alderlake: skip external buses for D-states list
by Eran Mitrani (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik. Eran Mitrani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70163 ) Change subject: soc/intel/alderlake: skip external buses for D-states list ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/70163/comment/0674ad11_48e7c40c PS1, Line 9: The devices in the list that was introduced in commit > Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit c66ea9857768 ("soc/intel/alderlake: provide a list of D-states to enter LPM")' Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/70163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3785b2b2af85d96e2e1296b6cfdefcd72080b5fe Gerrit-Change-Number: 70163 Gerrit-PatchSet: 1 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Tue, 29 Nov 2022 21:58:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/alderlake: skip external buses for D-states list
by build bot (Jenkins) (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70163 ) Change subject: soc/intel/alderlake: skip external buses for D-states list ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164871): https://review.coreboot.org/c/coreboot/+/70163/comment/1967e71b_639692ee PS1, Line 9: The devices in the list that was introduced in commit Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit c66ea9857768 ("soc/intel/alderlake: provide a list of D-states to enter LPM")' -- To view, visit https://review.coreboot.org/c/coreboot/+/70163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3785b2b2af85d96e2e1296b6cfdefcd72080b5fe Gerrit-Change-Number: 70163 Gerrit-PatchSet: 1 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Tue, 29 Nov 2022 21:55:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2022