coreboot-gerrit November 2022

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[S] Change in coreboot[master]: mb/google/herobrine: Mask out upper bits from sku_id()
by Shelley Chen (Code Review) 30 Nov '22

30 Nov '22

Attention is currently required from: Shelley Chen, Paul Menzel. Hello Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70164 to look at the new patch set (#5). Change subject: mb/google/herobrine: Mask out upper bits from sku_id() ...................................................................... mb/google/herobrine: Mask out upper bits from sku_id() When retrieving the SKU id value through the sku_id() function in mainboard_needs_pcie_init(), we only want the values in the lower 5 bits as we can only represent SKU id up to 27. Everything in the higher bits should be masked out because they are not needed. BUG=b:254281839 BRANCH=None TEST=Make sure that NVMe is not initialized Tested on a herobrine board with SKU id 0 Change-Id: I0e786ec392b5e1484cb2ff6d83a8d4fdd698950c Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/herobrine/mainboard.c 1 file changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/70164/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/70164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e786ec392b5e1484cb2ff6d83a8d4fdd698950c Gerrit-Change-Number: 70164 Gerrit-PatchSet: 5 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/herobrine: Mask out upper bits from sku_id()
by Julius Werner (Code Review) 30 Nov '22

30 Nov '22

Attention is currently required from: Shelley Chen, Paul Menzel. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70164 ) Change subject: mb/google/herobrine: Mask out upper bits from sku_id() ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e786ec392b5e1484cb2ff6d83a8d4fdd698950c Gerrit-Change-Number: 70164 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 30 Nov 2022 03:08:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: /: Remove extra space after comma
by Eric Lai (Code Review) 30 Nov '22

30 Nov '22

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69903 ) Change subject: /: Remove extra space after comma ...................................................................... /: Remove extra space after comma Change-Id: Ic64625bdaf8c4e9f8a5c1c22cece7f4070012da7 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69903 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/pirq_routing.c M src/drivers/intel/gma/intel_ddi.c M src/lib/selfboot.c M src/security/vboot/secdata_tpm.c M src/soc/intel/broadwell/pch/pcie.c M src/soc/samsung/exynos5420/dp_lowlevel.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/i82801gx/i82801gx.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pcie.c 10 files changed, 25 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c index 0da057f..0a1e75d 100644 --- a/src/arch/x86/pirq_routing.c +++ b/src/arch/x86/pirq_routing.c @@ -164,7 +164,7 @@ } for (i = 0; i < CONFIG_MAX_PIRQ_LINKS; i++) - printk(BIOS_DEBUG, "PIRQ%c: %d\n", i + 'A', pirq[i]); + printk(BIOS_DEBUG, "PIRQ%c: %d\n", i + 'A', pirq[i]); pirq_assign_irqs(pirq); } diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index 24bc162..6c6d13e 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -48,7 +48,7 @@ hsw_ddi_translations_fdi : hsw_ddi_translations_dp); - printk(BIOS_SPEW, "Initializing DDI buffers for port %d in %s mode\n", + printk(BIOS_SPEW, "Initializing DDI buffers for port %d in %s mode\n", port, use_fdi_mode ? "FDI" : "DP"); diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 637ad13..e21c493 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -93,7 +93,7 @@ break; } default: - printk(BIOS_INFO, "CBFS: Unknown compression type %d\n", compression); + printk(BIOS_INFO, "CBFS: Unknown compression type %d\n", compression); return 0; } /* Calculate middle after any changes to len. */ diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 7885069..844b28d 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -15,7 +15,7 @@ #include <console/console.h> #define VBDEBUG(format, args...) \ - printk(BIOS_INFO, "%s():%d: " format, __func__, __LINE__, ## args) + printk(BIOS_INFO, "%s():%d: " format, __func__, __LINE__, ## args) #define RETURN_ON_FAILURE(tpm_cmd) do { \ uint32_t result_; \ diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index b37f256..61d6962 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -295,7 +295,7 @@ if (dev->enabled) continue; - printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* 8.2 Configuration of PCI Express Root Ports */ pci_or_config32(dev, 0x338, 1 << 26); diff --git a/src/soc/samsung/exynos5420/dp_lowlevel.c b/src/soc/samsung/exynos5420/dp_lowlevel.c index 0cd6483..2d33873 100644 --- a/src/soc/samsung/exynos5420/dp_lowlevel.c +++ b/src/soc/samsung/exynos5420/dp_lowlevel.c @@ -229,7 +229,7 @@ CH2_PD | CH3_PD); break; default: - printk(BIOS_ERR, "DP undefined block number : %d\n", block); + printk(BIOS_ERR, "DP undefined block number : %d\n", block); return -1; } diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index d24604c..16ffaf5 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -327,7 +327,7 @@ } if (!dev->enabled) { - printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* * PCIE Power Savings for PantherPoint and CougarPoint/B1+ @@ -408,7 +408,7 @@ return pch_pcie_enable(dev); if (!dev->enabled) { - printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ pci_and_config16(dev, PCI_COMMAND, diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c index 6d4e7115..4783099 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.c +++ b/src/southbridge/intel/i82801gx/i82801gx.c @@ -56,7 +56,7 @@ u16 reg16; if (!dev->enabled) { - printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ reg16 = pci_read_config16(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 8f7cdb8..f83f3f6 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -185,7 +185,7 @@ return; if (!dev->enabled) { - printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ pci_and_config16(dev, PCI_COMMAND, diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 24fab3b..2f01560 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -322,7 +322,7 @@ if (dev->enabled) continue; - printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ pci_and_config16(dev, PCI_COMMAND, -- To view, visit https://review.coreboot.org/c/coreboot/+/69903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic64625bdaf8c4e9f8a5c1c22cece7f4070012da7 Gerrit-Change-Number: 69903 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: /: Remove extra space after comma
by Eric Lai (Code Review) 30 Nov '22

30 Nov '22

Attention is currently required from: Angel Pons, Julius Werner, Elyes Haouas. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69903 ) Change subject: /: Remove extra space after comma ...................................................................... Patch Set 2: (1 comment) File src/lib/selfboot.c: https://review.coreboot.org/c/coreboot/+/69903/comment/21ede53c_463bbf62 PS2, Line 96: > Eric, maybe this is out of scope of current patch (extra space *after* comma) ? I am fine. Just mentioned it :p No want to block this. -- To view, visit https://review.coreboot.org/c/coreboot/+/69903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic64625bdaf8c4e9f8a5c1c22cece7f4070012da7 Gerrit-Change-Number: 69903 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 30 Nov 2022 03:07:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Enable Dynamic DPTC config
by Dtrain Hsu (Code Review) 30 Nov '22

30 Nov '22

Attention is currently required from: Jason Nien, EricKY Cheng, Jon Murphy, Martin Roth, Tim Van Patten, Moises Garcia, Eric Peers, Karthikeyan Ramasubramanian. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69024 ) Change subject: mb/google/skyrim/var/winterhold: Enable Dynamic DPTC config ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I957511c44278a7cffb7cb5d7e099eb13232b6a1a Gerrit-Change-Number: 69024 Gerrit-PatchSet: 10 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Wed, 30 Nov 2022 02:47:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/zork: Select VBOOT by default
by Eric Lai (Code Review) 30 Nov '22

30 Nov '22

Attention is currently required from: Jason Nien, Matt DeVillier, Martin Roth. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69763 ) Change subject: mb/google/zork: Select VBOOT by default ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2447bf69baefd5560a0153dcd3d9b87b0a91a3f9 Gerrit-Change-Number: 69763 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 30 Nov 2022 02:25:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/common: provide a list of D-states to enter LPM
by Eran Mitrani (Code Review) 30 Nov '22

30 Nov '22

Eran Mitrani has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70166 ) Change subject: soc/intel/common: provide a list of D-states to enter LPM ...................................................................... soc/intel/common: provide a list of D-states to enter LPM This was done previously for ADL. moving the code to common so it can be leveraged for other platforms (e.g. MTL) Signed-off-by: Eran Mitrani <mitrani(a)google.com> Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752 --- M src/include/acpi/acpi.h M src/soc/intel/alderlake/acpi.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/acpi.h 4 files changed, 193 insertions(+), 156 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/70166/1 diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 57dbc65..e95c0a0 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -51,6 +51,7 @@ ACPI_DEVICE_SLEEP_D3 = 3, ACPI_DEVICE_SLEEP_D3_HOT = ACPI_DEVICE_SLEEP_D3, ACPI_DEVICE_SLEEP_D3_COLD = 4, + ACPI_DEVICE_SLEEP_NONE = 5, }; #define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ @@ -1283,7 +1284,6 @@ acpi_einj_action_table_t action_table[ACTION_COUNT]; } __packed acpi_einj_t; - uintptr_t get_coreboot_rsdp(void); void acpi_create_einj(acpi_einj_t *einj, uintptr_t addr, u8 actions); diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index c874067..60a2992 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -21,13 +21,6 @@ #include <cpu/cpu.h> #include <types.h> - -#define DEFAULT_CPU_D_STATE D0 -#define LPI_STATES_ALL 0xff -#define LPI_REVISION 0 -#define LPI_ENABLED 1 - - /* * List of supported C-states in this processor. */ @@ -118,14 +111,6 @@ C_STATE_C10 }; -enum dev_sleep_states { - D0, /* 0 */ - D1, /* 1 */ - D2, /* 2 */ - D3, /* 3 */ - NONE -}; - const acpi_cstate_t *soc_get_cstate_map(size_t *entries) { static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), @@ -180,153 +165,74 @@ fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; } -static const struct { - uint8_t pci_dev; - enum dev_sleep_states min_sleep_state; -} min_pci_sleep_states[] = { - { SA_DEVFN_ROOT, D3 }, - { SA_DEVFN_CPU_PCIE1_0, D3 }, - { SA_DEVFN_IGD, D3 }, - { SA_DEVFN_DPTF, D3 }, - { SA_DEVFN_IPU, D3 }, - { SA_DEVFN_CPU_PCIE6_0, D3 }, - { SA_DEVFN_CPU_PCIE6_2, D3 }, - { SA_DEVFN_TBT0, D3 }, - { SA_DEVFN_TBT1, D3 }, - { SA_DEVFN_TBT2, D3 }, - { SA_DEVFN_TBT3, D3 }, - { SA_DEVFN_GNA, D3 }, - { SA_DEVFN_TCSS_XHCI, D3 }, - { SA_DEVFN_TCSS_XDCI, D3 }, - { SA_DEVFN_TCSS_DMA0, D3 }, - { SA_DEVFN_TCSS_DMA1, D3 }, - { SA_DEVFN_VMD, D3 }, - { PCH_DEVFN_I2C6, D3 }, - { PCH_DEVFN_I2C7, D3 }, - { PCH_DEVFN_THC0, D3 }, - { PCH_DEVFN_THC1, D3 }, - { PCH_DEVFN_XHCI, D3 }, - { PCH_DEVFN_USBOTG, D3 }, - { PCH_DEVFN_SRAM, D3 }, - { PCH_DEVFN_CNVI_WIFI, D3 }, - { PCH_DEVFN_I2C0, D3 }, - { PCH_DEVFN_I2C1, D3 }, - { PCH_DEVFN_I2C2, D3 }, - { PCH_DEVFN_I2C3, D3 }, - { PCH_DEVFN_CSE, D0 }, - { PCH_DEVFN_SATA, D3 }, - { PCH_DEVFN_I2C4, D3 }, - { PCH_DEVFN_I2C5, D3 }, - { PCH_DEVFN_UART2, D3 }, - { PCH_DEVFN_PCIE1, D0 }, - { PCH_DEVFN_PCIE2, D0 }, - { PCH_DEVFN_PCIE3, D0 }, - { PCH_DEVFN_PCIE4, D0 }, - { PCH_DEVFN_PCIE5, D0 }, - { PCH_DEVFN_PCIE6, D0 }, - { PCH_DEVFN_PCIE7, D0 }, - { PCH_DEVFN_PCIE8, D0 }, - { PCH_DEVFN_PCIE9, D0 }, - { PCH_DEVFN_PCIE10, D0 }, - { PCH_DEVFN_PCIE11, D0 }, - { PCH_DEVFN_PCIE12, D0 }, - { PCH_DEVFN_UART0, D3 }, - { PCH_DEVFN_UART1, D3 }, - { PCH_DEVFN_GSPI0, D3 }, - { PCH_DEVFN_GSPI1, D3 }, - { PCH_DEVFN_ESPI, D0 }, - { PCH_DEVFN_PMC, D0 }, - { PCH_DEVFN_HDA, D0 }, - { PCH_DEVFN_SPI, D3 }, - { PCH_DEVFN_GBE, D3 }, +min_sleep_state_t min_pci_sleep_states[] = { + { SA_DEVFN_ROOT, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_CPU_PCIE1_0, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_IGD, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_DPTF, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_IPU, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_CPU_PCIE6_0, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_CPU_PCIE6_2, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_TBT0, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_TBT1, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_TBT2, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_TBT3, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_GNA, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_TCSS_XHCI, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_TCSS_XDCI, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_TCSS_DMA0, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_TCSS_DMA1, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_VMD, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_I2C6, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_I2C7, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_THC0, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_THC1, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_XHCI, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_USBOTG, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_SRAM, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_CNVI_WIFI, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_I2C0, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_I2C1, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_I2C2, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_I2C3, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_CSE, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_SATA, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_I2C4, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_I2C5, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_UART2, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_PCIE1, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE2, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE3, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE4, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE5, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE6, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE7, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE8, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE9, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE10, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE11, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PCIE12, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_UART0, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_UART1, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_GSPI0, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_GSPI1, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_ESPI, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PMC, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_HDA, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_SPI, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_GBE, ACPI_DEVICE_SLEEP_D3 }, }; -static enum dev_sleep_states get_min_sleep_state(const struct device *dev) +min_sleep_state_t **get_min_sleep_state_array(int *size) { - if (!is_dev_enabled(dev)) - return NONE; - - switch (dev->path.type) { - case DEVICE_PATH_APIC: - return DEFAULT_CPU_D_STATE; - - case DEVICE_PATH_PCI: - for (size_t i = 0; i < ARRAY_SIZE(min_pci_sleep_states); i++) - if (min_pci_sleep_states[i].pci_dev == dev->path.pci.devfn) - return min_pci_sleep_states[i].min_sleep_state; - printk(BIOS_WARNING, "Unknown min d_state for %x\n", dev->path.pci.devfn); - return NONE; - - default: - return NONE; - } + *size = ARRAY_SIZE(min_pci_sleep_states); + return (&min_pci_sleep_states); } /* Generate the LPI constraint table and return the number of devices included */ void soc_lpi_get_constraints(void *unused) { - unsigned int num_entries; - const struct device *dev; - enum dev_sleep_states min_sleep_state; - - num_entries = 0; - - for (dev = all_devices; dev; dev = dev->next) { - if (get_min_sleep_state(dev) != NONE) - num_entries++; - } - - acpigen_emit_byte(RETURN_OP); - acpigen_write_package(num_entries); - - size_t cpu_index = 0; - for (dev = all_devices; dev; dev = dev->next) { - min_sleep_state = get_min_sleep_state(dev); - if (min_sleep_state == NONE) - continue; - - acpigen_write_package(3); - { - char path[32] = { 0 }; - /* Emit the device path */ - switch (dev->path.type) { - case DEVICE_PATH_PCI: - acpigen_emit_namestring(acpi_device_path(dev)); - break; - - case DEVICE_PATH_APIC: - snprintf(path, sizeof(path), CONFIG_ACPI_CPU_STRING, - cpu_index++); - acpigen_emit_namestring(path); - break; - - default: - /* Unhandled */ - printk(BIOS_WARNING, - "Unhandled device path type %d\n", dev->path.type); - acpigen_emit_namestring(NULL); - break; - } - - acpigen_write_integer(LPI_ENABLED); - acpigen_write_package(2); - { - acpigen_write_integer(LPI_REVISION); - acpigen_write_package(2); /* no optional device info */ - { - /* Assume constraints apply to all entries */ - acpigen_write_integer(LPI_STATES_ALL); - acpigen_write_integer(min_sleep_state); /* min D-state */ - } - acpigen_write_package_end(); - } - acpigen_write_package_end(); - } - acpigen_write_package_end(); - } - - acpigen_write_package_end(); - printk(BIOS_INFO, "Returning SoC specific constraint package for %d devices\n", num_entries); + acpi_generate_lpi_constraint_table(); } uint32_t soc_read_sci_irq_select(void) diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 860c868..82cd89f 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi.h> #include <acpi/acpi_pm.h> #include <acpi/acpigen.h> #include <arch/ioapic.h> @@ -23,6 +24,11 @@ #define CPUID_6_EAX_ISST (1 << 7) +#define DEFAULT_CPU_D_STATE ACPI_DEVICE_SLEEP_D0 +#define LPI_STATES_ALL 0xff +#define LPI_REVISION 0 +#define LPI_ENABLED 1 + static int acpi_sci_irq(void) { int sci_irq = 9; @@ -69,7 +75,6 @@ current += acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags); - return current; } @@ -431,3 +436,103 @@ if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) sgx_fill_ssdt(); } + +__weak min_sleep_state_t **get_min_sleep_state_array(int *size) +{ + printk(BIOS_ERR, "%s is called without a proper implementation\n", __func__); + return NULL; +} + +static enum acpi_device_sleep_states get_min_sleep_state(const struct device *dev) +{ + min_sleep_state_t ** min_pci_sleep_states; + int array_size; + min_pci_sleep_states = get_min_sleep_state_array(&array_size); + + if (!is_dev_enabled(dev)) + return ACPI_DEVICE_SLEEP_NONE; + + switch (dev->path.type) { + case DEVICE_PATH_APIC: + return DEFAULT_CPU_D_STATE; + + case DEVICE_PATH_PCI: + /* skip external buses*/ + if (dev->bus->secondary != 0) + return NONE; + for (size_t i = 0; i < array_size; i++) + if ((*min_pci_sleep_states)[i].pci_dev == dev->path.pci.devfn) + return (*min_pci_sleep_states)[i].min_sleep_state; + printk(BIOS_WARNING, "Unknown min d_state for %x\n", dev->path.pci.devfn); + return ACPI_DEVICE_SLEEP_NONE; + + default: + return ACPI_DEVICE_SLEEP_NONE; + } +} + +void acpi_generate_lpi_constraint_table(void) +{ + unsigned int num_entries; + const struct device *dev; + enum acpi_device_sleep_states min_sleep_state; + + num_entries = 0; + + for (dev = all_devices; dev; dev = dev->next) { + if (get_min_sleep_state(dev) != ACPI_DEVICE_SLEEP_NONE) + num_entries++; + } + + acpigen_emit_byte(RETURN_OP); + acpigen_write_package(num_entries); + + size_t cpu_index = 0; + for (dev = all_devices; dev; dev = dev->next) { + min_sleep_state = get_min_sleep_state(dev); + if (min_sleep_state == ACPI_DEVICE_SLEEP_NONE) + continue; + + acpigen_write_package(3); + { + char path[32] = { 0 }; + /* Emit the device path */ + switch (dev->path.type) { + case DEVICE_PATH_PCI: + acpigen_emit_namestring(acpi_device_path(dev)); + break; + + case DEVICE_PATH_APIC: + snprintf(path, sizeof(path), CONFIG_ACPI_CPU_STRING, + cpu_index++); + acpigen_emit_namestring(path); + break; + + default: + /* Unhandled */ + printk(BIOS_WARNING, + "Unhandled device path type %d\n", dev->path.type); + acpigen_emit_namestring(NULL); + break; + } + + acpigen_write_integer(LPI_ENABLED); + acpigen_write_package(2); + { + acpigen_write_integer(LPI_REVISION); + acpigen_write_package(2); /* no optional device info */ + { + /* Assume constraints apply to all entries */ + acpigen_write_integer(LPI_STATES_ALL); + acpigen_write_integer(min_sleep_state); /* min D-state */ + } + acpigen_write_package_end(); + } + acpigen_write_package_end(); + } + acpigen_write_package_end(); + } + + acpigen_write_package_end(); + printk(BIOS_INFO, "Returning SoC specific constraint package for %d devices\n", num_entries); +} \ No newline at end of file diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index d05ddf3..6399dd2 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -133,4 +133,17 @@ /* Check if CPU supports Nominal frequency or not */ bool soc_is_nominal_freq_supported(void); + +/* Min sleep state per device*/ +typedef struct min_sleep_state { + uint8_t pci_dev; + enum acpi_device_sleep_states min_sleep_state; +} min_sleep_state_t; + +/* Returns an array that maps devices to their min sleep state*/ +min_sleep_state_t **get_min_sleep_state_array(int *size); + +/* Generates an ACPI table for LPI constraints*/ +void acpi_generate_lpi_constraint_table(void); + #endif /* _SOC_INTEL_COMMON_BLOCK_ACPI_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/70166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752 Gerrit-Change-Number: 70166 Gerrit-PatchSet: 1 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/herobrine: Update FMD file for multiple ROM sizes
by Eric Lai (Code Review) 30 Nov '22

30 Nov '22

Attention is currently required from: Martin L Roth, Martin Roth. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69939 ) Change subject: mb/google/herobrine: Update FMD file for multiple ROM sizes ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia75725b0c4d61e832c94160fa4cd455e89c60274 Gerrit-Change-Number: 69939 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 30 Nov 2022 01:07:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/herobrine: Update FMD file for multiple ROM sizes
by Shelley Chen (Code Review) 30 Nov '22

30 Nov '22

Attention is currently required from: Martin L Roth, Martin Roth. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69939 ) Change subject: mb/google/herobrine: Update FMD file for multiple ROM sizes ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia75725b0c4d61e832c94160fa4cd455e89c60274 Gerrit-Change-Number: 69939 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 30 Nov 2022 01:02:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/herobrine: Only retrieve sku_id from EC once
by Shelley Chen (Code Review) 30 Nov '22

30 Nov '22

Attention is currently required from: Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70162 ) Change subject: mb/google/herobrine: Only retrieve sku_id from EC once ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/herobrine/boardid.c: https://review.coreboot.org/c/coreboot/+/70162/comment/d6054877_10d67816 PS2, Line 28: printk(BIOS_INFO, "BoardID :%d - " > Ok, I removed it. Qualcomm, if you need this to stay in for some reason, please let us know. Also, I put in an early exit like in sku_id because I figured that it wouldn't be useful setting up the array anyway if we were not going to call gpio_base3_value again anyway. -- To view, visit https://review.coreboot.org/c/coreboot/+/70162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia787968100baf58a41ccce0cf95ed3ec9ce1758a Gerrit-Change-Number: 70162 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 30 Nov 2022 00:59:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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