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Change subject: mb/google/herobrine: Mask out upper bits from sku_id()
......................................................................
Patch Set 4:
(2 comments)
File src/mainboard/google/herobrine/mainboard.c:
https://review.coreboot.org/c/coreboot/+/70164/comment/10f1937b_197c89f5
PS2, Line 95: bits
> pins
Done
https://review.coreboot.org/c/coreboot/+/70164/comment/9374d9b6_144b292c
PS2, Line 98: uint32_t sku_bits_mask = 0x1f;
> I would maybe just make it 0xff to have a cleaner boundary, that way we have some room to add a 4th […]
Done
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Hello Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/70164
to look at the new patch set (#4).
Change subject: mb/google/herobrine: Mask out upper bits from sku_id()
......................................................................
mb/google/herobrine: Mask out upper bits from sku_id()
When retrieving the SKU id bits through the sku_id() function in
mainboard_needs_pcie_init(), we only want the values in the lower 5
bits as we can only represent SKU id up to 27. Everything in the
higher bits should be masked out because they are not needed.
BUG=b:254281839
BRANCH=None
TEST=Make sure that NVMe is not initialized
Tested on a herobrine board with SKU id 0
Change-Id: I0e786ec392b5e1484cb2ff6d83a8d4fdd698950c
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
M src/mainboard/google/herobrine/mainboard.c
1 file changed, 26 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/70164/4
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Change subject: mb/google/nissa/pujjo: Add new audio sku configure
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/google/herobrine: Only retrieve sku_id from EC once
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/herobrine/boardid.c:
https://review.coreboot.org/c/coreboot/+/70162/comment/0b591732_fd0bf3d7
PS2, Line 28: printk(BIOS_INFO, "BoardID :%d - "
> Can we get rid of this too?
Ok, I removed it. Qualcomm, if you need this to stay in for some reason, please let us know.
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Hello build bot (Jenkins), Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/70162
to look at the new patch set (#3).
Change subject: mb/google/herobrine: Only retrieve sku_id from EC once
......................................................................
mb/google/herobrine: Only retrieve sku_id from EC once
Currently, we are getting the sku id from the EC every time we call
the sku_id() function. However, this will never change so we only
need to retrieve it once. Inserting exit condition if sku id is
already set, then don't get it from the EC again.
Also, removing the ram_code function, which does nothing right now.
There is already a weak stub_function for this in
src/lib/coreboot_table.c that already does the same thing.
BUG=b:260740438,b:182963902
BRANCH=None
TEST=make sure image still boots to login on herobrine device
Change-Id: Ia787968100baf58a41ccce0cf95ed3ec9ce1758a
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
M src/mainboard/google/herobrine/boardid.c
1 file changed, 35 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/70162/3
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Change subject: mb/google/nissa/pujjo: Add new audio sku configure
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/intel/meteorlake: Refactor `pmc_lockdown_cfg` function
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Change subject: soc/intel/alderlake: Disable L1 substates for PCIe compliance test mode
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164877):
https://review.coreboot.org/c/coreboot/+/70165/comment/f7a272a1_2b843da8
PS1, Line 10: continous clock output.
'continous' may be misspelled - perhaps 'continuous'?
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Hello Bora Guvendik,
I'd like you to do a code review.
Please visit
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to review the following change.
Change subject: soc/intel/alderlake: Disable L1 substates for PCIe compliance test mode
......................................................................
soc/intel/alderlake: Disable L1 substates for PCIe compliance test mode
Disable L1 substates for PCIe compliance test mode in order to get
continous clock output.
BUG=b:235863379
TEST=Boot in compliance mode, check FSP settings
Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com>
Change-Id: I2a3b313425e00fe11f616d964f825baaef463c71
---
M src/soc/intel/alderlake/fsp_params.c
1 file changed, 19 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/70165/1
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 853b2f2..224cf8a 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -471,7 +471,9 @@
*/
static int get_l1_substate_control(enum L1_substates_control ctl)
{
- if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT))
+ if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
+ ctl = L1_SS_DISABLED;
+ else if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT))
ctl = L1_SS_L1_2;
return ctl - 1;
}
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Change subject: lib/fmap.c: Show error on fmd flash size mismatch with Kconfig
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
File src/lib/fmap.c:
https://review.coreboot.org/c/coreboot/+/69486/comment/231b49fc_1a728f37
PS2, Line 3: #include <assert.h>
nit: not technically needed for _Static_assert(), it's a compiler built-in.
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