coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/dedede/variants/sasukette: Disable PCIE RP8 and CLKSRC4
by Dtrain Hsu (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Rui Zhou, Aamir Bohra. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69848 ) Change subject: mb/google/dedede/variants/sasukette: Disable PCIE RP8 and CLKSRC4 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61bcefa128d4f39613a760b647048f9e19e262c2 Gerrit-Change-Number: 69848 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Aamir Bohra <aamirbohra(a)google.com> Gerrit-Comment-Date: Wed, 30 Nov 2022 05:59:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Documentation: Add wake source info to device tree documentation
by Karthik Ramasubramanian (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Raul Rangel, Dmitry Torokhov, Tim Wawrzynczak, Paul Menzel, Tim Van Patten. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67385 ) Change subject: Documentation: Add wake source info to device tree documentation ...................................................................... Patch Set 7: (2 comments) File Documentation/drivers/dt_entries.md: https://review.coreboot.org/c/coreboot/+/67385/comment/ecbe8f7d_cf35e1e0 PS7, Line 130: "Level" and "Active" Nit: "Trigger" and "Polarity" https://review.coreboot.org/c/coreboot/+/67385/comment/760f9477_e55b19e5 PS7, Line 208: method Nit: methods -- To view, visit https://review.coreboot.org/c/coreboot/+/67385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcdbd5371408784bf9b81c1ade90263de8c60e0f Gerrit-Change-Number: 67385 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Dmitry Torokhov <dtor(a)chromium.org> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Mark Hasemeyer <markhas(a)google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Zieba <robertzieba(a)google.com> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Dmitry Torokhov <dtor(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Wed, 30 Nov 2022 05:58:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmn/cse: Allow to perform essential CSE operations post EOP
by Sridhar Siricilla (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69978 ) Change subject: soc/intel/cmn/cse: Allow to perform essential CSE operations post EOP ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/common/block/cse/cse_eop.c: https://review.coreboot.org/c/coreboot/+/69978/comment/cda7e074_ed8eb88d PS5, Line 244: if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE)) : cse_late_finalize(); > > This code has to be decoupled or function name must be renamed to reflect new addition. […] You may rename the function as cse_send_eop_and_late_finalize .. -- To view, visit https://review.coreboot.org/c/coreboot/+/69978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4c4564befcd38732368b21f1ca3e24b68c30e0c Gerrit-Change-Number: 69978 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 30 Nov 2022 04:40:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/qualcomm/sc7280: Add API to differentialize PRO and NON_PRO SKUs
by Venkat Thogaru (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Shelley Chen, Taniya Das, Paul Menzel, Julius Werner, Sudheer Amrabadi. Venkat Thogaru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68384 ) Change subject: soc/qualcomm/sc7280: Add API to differentialize PRO and NON_PRO SKUs ...................................................................... Patch Set 15: (1 comment) File src/soc/qualcomm/sc7280/socinfo.c: https://review.coreboot.org/c/coreboot/+/68384/comment/401039f4_392f7924 PS4, Line 12: static struct chipinfo chipinfolut[] = { > Sure. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9f23696384a6c1a89000292eafebd8a16c273ca Gerrit-Change-Number: 68384 Gerrit-PatchSet: 15 Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Wed, 30 Nov 2022 04:38:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/e7505: Hook up PCI domain and CPU ops to devicetree
by Kyösti Mälkki (Code Review) 29 Nov '22

29 Nov '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70058 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: nb/intel/e7505: Hook up PCI domain and CPU ops to devicetree ...................................................................... nb/intel/e7505: Hook up PCI domain and CPU ops to devicetree Change-Id: I70fb470b63ddd06f1d1e34deaea296d81e24f75f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70058 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/aopen/dxplplusu/devicetree.cb M src/northbridge/intel/e7505/northbridge.c 2 files changed, 17 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/aopen/dxplplusu/devicetree.cb b/src/mainboard/aopen/dxplplusu/devicetree.cb index 2dfa03d..df99751 100644 --- a/src/mainboard/aopen/dxplplusu/devicetree.cb +++ b/src/mainboard/aopen/dxplplusu/devicetree.cb @@ -3,9 +3,11 @@ chip northbridge/intel/e7505 device cpu_cluster 0 on + ops e7505_cpu_bus_ops end device domain 0 on + ops e7505_pci_domain_ops device pci 0.0 on end # Chipset host controller device pci 0.1 on end # Host RASUM controller device pci 2.0 on # Hub interface B diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index cc7f85d..a353759 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -55,7 +55,7 @@ assign_resources(dev->link_list); } -static struct device_operations pci_domain_ops = { +struct device_operations e7505_pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, .scan_bus = pci_domain_scan_bus, @@ -63,23 +63,12 @@ }; -static struct device_operations cpu_bus_ops = { +struct device_operations e7505_cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = mp_cpu_bus_init, }; -static void enable_dev(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - struct chip_operations northbridge_intel_e7505_ops = { CHIP_NAME("Intel E7505 Northbridge") - .enable_dev = enable_dev, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/70058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70fb470b63ddd06f1d1e34deaea296d81e24f75f Gerrit-Change-Number: 70058 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: commonlib: Add essential comments for ELOG_CROS_DIAG_RESULT
by Hsuan-ting Chen (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Yu-Ping Wu. Hsuan-ting Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70145 ) Change subject: commonlib: Add essential comments for ELOG_CROS_DIAG_RESULT ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/70145/comment/07cafeaa_61e7755d PS1, Line 13: guidelines The guideline is at https://chromium.googlesource.com/chromium/src.git/+/HEAD/tools/metrics/his… Not knowing how to put long URL on commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/70145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a1a7c863d5aa9496649f81dc94fd79a6ad482df Gerrit-Change-Number: 70145 Gerrit-PatchSet: 1 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 30 Nov 2022 03:57:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: commonlib: Add essential comments for ELOG_CROS_DIAG_RESULT
by Hsuan-ting Chen (Code Review) 29 Nov '22

29 Nov '22

Hsuan-ting Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70145 ) Change subject: commonlib: Add essential comments for ELOG_CROS_DIAG_RESULT ...................................................................... commonlib: Add essential comments for ELOG_CROS_DIAG_RESULT ELOG_CROS_DIAG_RESULT_* codes should be consistent with the enum definition of enumerated histograms. Hence add comments based on the requirements of enum histograms in histogram guidelines. BUG=b:4047421 TEST=none Change-Id: I1a1a7c863d5aa9496649f81dc94fd79a6ad482df --- M src/commonlib/bsd/include/commonlib/bsd/elog.h 1 file changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/70145/1 diff --git a/src/commonlib/bsd/include/commonlib/bsd/elog.h b/src/commonlib/bsd/include/commonlib/bsd/elog.h index 06ea5a7..1f39090 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/elog.h +++ b/src/commonlib/bsd/include/commonlib/bsd/elog.h @@ -316,7 +316,12 @@ #define ELOG_CROS_DIAG_TYPE_STORAGE_TEST_EXTENDED 0x03 #define ELOG_CROS_DIAG_TYPE_MEMORY_QUICK 0x04 #define ELOG_CROS_DIAG_TYPE_MEMORY_FULL 0x05 -/* Result codes for elog_event_cros_diag_log in ELOG_CROS_DIAGNOSTICS_LOGS */ +/* + * Result codes for elog_event_cros_diag_log in ELOG_CROS_DIAGNOSTICS_LOGS + * + * These values are persisted to logs. Entries should not be renumbered and + * numeric values should never be reused. + */ #define ELOG_CROS_DIAG_RESULT_PASSED 0x01 #define ELOG_CROS_DIAG_RESULT_ERROR 0x02 #define ELOG_CROS_DIAG_RESULT_FAILED 0x03 -- To view, visit https://review.coreboot.org/c/coreboot/+/70145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a1a7c863d5aa9496649f81dc94fd79a6ad482df Gerrit-Change-Number: 70145 Gerrit-PatchSet: 1 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-CC: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/brya/var/gaelin: Configure audio in devicetree
by Derek Huang (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Tarun Tuli, Raymond Chung, Paul Menzel, Zhuohao Lee. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69964 ) Change subject: mb/google/brya/var/gaelin: Configure audio in devicetree ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/gaelin/overridetree.cb: https://review.coreboot.org/c/coreboot/+/69964/comment/b6a3b4e8_2afcf009 PS3, Line 239: device ref hda on does it necessary to turn hda on? I think it's for sound wire device, ALC1015 uses i2s only? -- To view, visit https://review.coreboot.org/c/coreboot/+/69964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc8cacce6cb4b3e55fc7332bb9eb9ac20848fc5b Gerrit-Change-Number: 69964 Gerrit-PatchSet: 3 Gerrit-Owner: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bruce Chiang <brucechiang(a)msi.corp-partner.google.com> Gerrit-CC: Eason Chang <easonchang(a)msi.corp-partner.google.com> Gerrit-CC: Eddy Lu <eddylu(a)ami.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Wed, 30 Nov 2022 03:23:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: TEST-ONLY mb/google/brya/var/vell: Config I2C frequency
by Shon Wang (Code Review) 29 Nov '22

29 Nov '22

Shon Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70168 ) Change subject: TEST-ONLY mb/google/brya/var/vell: Config I2C frequency ...................................................................... TEST-ONLY mb/google/brya/var/vell: Config I2C frequency Update parameters for TP devices. After applied this patch, the measured the I2C frequency meets spec BUG=b: TEST=FW_NAME=vell emerge-brya coreboot flash and measure TP devices 1. I2C5 (Touchpad): 386 Khz, hold time 0.76 us, Change-Id: Ib2e1e3273b592f6b4c079104fd84d1c51b2a4b16 --- M src/mainboard/google/brya/variants/vell/overridetree.cb 1 file changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/70168/1 diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 3feb29f..9147ca8 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -57,6 +57,16 @@ .fall_time_ns = 400, .data_hold_time_ns = 50, }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .data_hold_time_ns = 50, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 170, + .scl_hcnt = 70, + .sda_hold = 40, + } + }, .i2c[7] = { .speed = I2C_SPEED_FAST_PLUS, .speed_config[0] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/70168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2e1e3273b592f6b4c079104fd84d1c51b2a4b16 Gerrit-Change-Number: 70168 Gerrit-PatchSet: 1 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/alderlake: Disable L1 substates for PCIe compliance test mode
by Jérémy Compostella (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Bora Guvendik, Tarun Tuli, Subrata Banik. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70165 ) Change subject: soc/intel/alderlake: Disable L1 substates for PCIe compliance test mode ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/70165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a3b313425e00fe11f616d964f825baaef463c71 Gerrit-Change-Number: 70165 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 30 Nov 2022 03:10:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2022