coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[master]: mb/intel/mtlrvp: Enable EC and building ChromeOS
by Harsha B R (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, Paul Menzel, Angel Pons, Krishna P Bhat D, Tim Wawrzynczak, Tarun Tuli, Jamie Ryu, Subrata Banik, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Usha P, Raj Astekar. Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66101 ) Change subject: mb/intel/mtlrvp: Enable EC and building ChromeOS ...................................................................... Patch Set 16: (1 comment) File src/mainboard/intel/mtlrvp/Kconfig: https://review.coreboot.org/c/coreboot/+/66101/comment/726eba03_1928053f PS4, Line 45: default MTL_EC_DETECT > > Current patch defaults the On-board EC to MTL_CHROME_EC (though having the option to config to MTL […] Many Thanks! As the code infra is currently not supporting both Chrome and Windows EC, the option was defaulted to CHROME_EC. Will give a try on this. -- To view, visit https://review.coreboot.org/c/coreboot/+/66101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I662d7f79050d35e152d97dc5c2118a4af56223bc Gerrit-Change-Number: 66101 Gerrit-PatchSet: 16 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Tue, 29 Nov 2022 19:45:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jamie Ryu <jamie.m.ryu(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Harsha B R <harsha.b.r(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/ti/am335x: Fix building omap header with clang
by Arthur Heymans (Code Review) 29 Nov '22

29 Nov '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70161 ) Change subject: soc/ti/am335x: Fix building omap header with clang ...................................................................... soc/ti/am335x: Fix building omap header with clang Clang needs the target and the linker defined explicitly. Change-Id: Id6ba42b470349a4b138a65b2a037f16a65982ef7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/ti/am335x/Makefile.inc 1 file changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/70161/1 diff --git a/src/soc/ti/am335x/Makefile.inc b/src/soc/ti/am335x/Makefile.inc index e09a0f7..ec70802 100644 --- a/src/soc/ti/am335x/Makefile.inc +++ b/src/soc/ti/am335x/Makefile.inc @@ -24,6 +24,10 @@ omap-header-generic-ccopts += -D__COREBOOT_ARM_ARCH__=7 +ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) +CFLAGS_omap-header += -fuse-ld=$(LD_omap-header) +endif + real-target: $(obj)/MLO header_ld := $(call src-to-obj,omap-header,$(dir)/header.ld) @@ -31,9 +35,10 @@ get_header_size= \ $(shell echo $$(wc -c < $(objcbfs)/bootblock.bin)) +# This does not work well with clang so explicitly use GCC $(obj)/omap-header.bin: $$(omap-header-objs) $(objcbfs)/bootblock.bin @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC_omap-header) -nostdlib -nostartfiles -static -include $(obj)/config.h \ + $(CC_omap-header) $(CFLAGS_omap-header) -nostdlib -nostartfiles -static -include $(obj)/config.h \ -Wl,--defsym,header_load_size=$(strip \ $(call get_header_size,$(obj)/coreboot.rom) \ ) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/70161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6ba42b470349a4b138a65b2a037f16a65982ef7 Gerrit-Change-Number: 70161 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/ti/am335x: Change and optimize memlayout
by Arthur Heymans (Code Review) 29 Nov '22

29 Nov '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70160 ) Change subject: soc/ti/am335x: Change and optimize memlayout ...................................................................... soc/ti/am335x: Change and optimize memlayout Clang builds are slightly larget than GCC builds so increase the size of both bootblock and romstage. The technical reference manual mentions no upper limit to the size of the bootblock in the TI header so increasing the bootblock size is allowed. Change-Id: I8719bc3728d4cc8dba8d939cc154c3fc0884d47b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/ti/beaglebone/board.fmd M src/soc/ti/am335x/memlayout.ld 2 files changed, 25 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/70160/1 diff --git a/src/mainboard/ti/beaglebone/board.fmd b/src/mainboard/ti/beaglebone/board.fmd index 0656b85..26a210f 100644 --- a/src/mainboard/ti/beaglebone/board.fmd +++ b/src/mainboard/ti/beaglebone/board.fmd @@ -1,6 +1,6 @@ FLASH@0x000 32M { BIOS@0x0 109K { - BOOTBLOCK@0x0 20K + BOOTBLOCK@0x0 22K } PAYLOAD { diff --git a/src/soc/ti/am335x/memlayout.ld b/src/soc/ti/am335x/memlayout.ld index 8d1e8d6..e3e783e 100644 --- a/src/soc/ti/am335x/memlayout.ld +++ b/src/soc/ti/am335x/memlayout.ld @@ -7,15 +7,14 @@ SECTIONS { SRAM_START(0x402f0400) - BOOTBLOCK(0x402f0400, 20K) - FMAP_CACHE(0x402f0400+20K, 2K) - CBFS_MCACHE(0x402f0400+20K+2K, 8K) - TTB(0x402F8000, 16K) - ROMSTAGE(0x402F8000+16K, 40K) + BOOTBLOCK(., 22K) + FMAP_CACHE(., 2K) + CBFS_MCACHE(., 8K) + ROMSTAGE(., 42K) + PRERAM_CBFS_CACHE(., 20K) - PRERAM_CBFS_CACHE(0x402F8000+16K+40K, 20K) - - STACK(0x4030be00, 4K) + STACK(., 4K) + TTB(0x4030c000, 16K) SRAM_END(0x40310000) DRAM_START(0x80000000) -- To view, visit https://review.coreboot.org/c/coreboot/+/70160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8719bc3728d4cc8dba8d939cc154c3fc0884d47b Gerrit-Change-Number: 70160 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: Makefile.inc: Optimize even more for size with clang
by Arthur Heymans (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Martin L Roth. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70159 ) Change subject: Makefile.inc: Optimize even more for size with clang ...................................................................... Makefile.inc: Optimize even more for size with clang This results in even smaller binaries. Change-Id: Ic94a48fc47c289da8414cad82b2c092bf288e6e9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/70159/1 diff --git a/Makefile.inc b/Makefile.inc index ef565c2..8a540b0 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -490,7 +490,11 @@ CFLAGS_common += -Og ADAFLAGS_common += -Og else +ifeq ($(CONFIG_COMPILER_CLANG),y) # Also enable with GCC 12 +CFLAGS_common += -Oz +else CFLAGS_common += -Os +endif ADAFLAGS_common += -Os endif -- To view, visit https://review.coreboot.org/c/coreboot/+/70159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic94a48fc47c289da8414cad82b2c092bf288e6e9 Gerrit-Change-Number: 70159 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: google/veyron: Fix add type to function definition
by Arthur Heymans (Code Review) 29 Nov '22

29 Nov '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70138 ) Change subject: google/veyron: Fix add type to function definition ...................................................................... google/veyron: Fix add type to function definition Function definitions without a type a deprecated in all versions of C. Change-Id: I2efb42e653b0deb56ba6b0c9789764a9cabc552e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/veyron/bootblock.c M src/mainboard/google/veyron_mickey/bootblock.c M src/mainboard/google/veyron_rialto/bootblock.c 3 files changed, 15 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/70138/1 diff --git a/src/mainboard/google/veyron/bootblock.c b/src/mainboard/google/veyron/bootblock.c index 0d11462..6b0cc81 100644 --- a/src/mainboard/google/veyron/bootblock.c +++ b/src/mainboard/google/veyron/bootblock.c @@ -14,7 +14,7 @@ #include "board.h" -void bootblock_mainboard_early_init() +void bootblock_mainboard_early_init(void) { if (CONFIG(CONSOLE_SERIAL)) { assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE); diff --git a/src/mainboard/google/veyron_mickey/bootblock.c b/src/mainboard/google/veyron_mickey/bootblock.c index d9358a3..261d7e5 100644 --- a/src/mainboard/google/veyron_mickey/bootblock.c +++ b/src/mainboard/google/veyron_mickey/bootblock.c @@ -14,7 +14,7 @@ #include "board.h" -void bootblock_mainboard_early_init() +void bootblock_mainboard_early_init(void) { if (CONFIG(CONSOLE_SERIAL)) { assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE); diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c index 5230378..a0ce1ab 100644 --- a/src/mainboard/google/veyron_rialto/bootblock.c +++ b/src/mainboard/google/veyron_rialto/bootblock.c @@ -14,7 +14,7 @@ #include "board.h" -void bootblock_mainboard_early_init() +void bootblock_mainboard_early_init(void) { if (CONFIG(CONSOLE_SERIAL)) { assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE); -- To view, visit https://review.coreboot.org/c/coreboot/+/70138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2efb42e653b0deb56ba6b0c9789764a9cabc552e Gerrit-Change-Number: 70138 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/nvidia/tegra210: Fix flushing SPI fifo
by Arthur Heymans (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Julius Werner. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70137 ) Change subject: soc/nvidia/tegra210: Fix flushing SPI fifo ...................................................................... soc/nvidia/tegra210: Fix flushing SPI fifo This will avoid clearing the other bits in fifo_status. Change-Id: I7917b3f8d9af6056ed872b7e48cef9c3deba5119 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/nvidia/tegra210/spi.c 1 file changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/70137/1 diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index 0f38df2..e6f667a 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -331,7 +331,7 @@ uint32_t fifo_status = read32(&spi->regs->fifo_status); fifo_status |= flush_mask; - write32(&spi->regs->fifo_status, flush_mask); + write32(&spi->regs->fifo_status, fifo_status); while (read32(&spi->regs->fifo_status) & flush_mask) ; -- To view, visit https://review.coreboot.org/c/coreboot/+/70137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7917b3f8d9af6056ed872b7e48cef9c3deba5119 Gerrit-Change-Number: 70137 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: arch/arm/eabi_compat.c: Add eabi_clrX and eabi_memcyX
by Arthur Heymans (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Martin L Roth, Julius Werner, Arthur Heymans. Hello build bot (Jenkins), Julius Werner, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69743 to look at the new patch set (#10). Change subject: arch/arm/eabi_compat.c: Add eabi_clrX and eabi_memcyX ...................................................................... arch/arm/eabi_compat.c: Add eabi_clrX and eabi_memcyX Clang generated code uses this for zero initialized variables. Change-Id: I460a0096918141c1cf8826bdf1853a3aa3aecff8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/arm/eabi_compat.c 1 file changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/69743/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/69743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I460a0096918141c1cf8826bdf1853a3aa3aecff8 Gerrit-Change-Number: 69743 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: ec/google/chromeec: Add packed attribute to structs in union
by Arthur Heymans (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Martin L Roth, Caveh Jalali, Julius Werner, Arthur Heymans, Boris Mittelberg. Hello build bot (Jenkins), Caveh Jalali, Julius Werner, Elyes Haouas, Boris Mittelberg, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69742 to look at the new patch set (#7). Change subject: ec/google/chromeec: Add packed attribute to structs in union ...................................................................... ec/google/chromeec: Add packed attribute to structs in union Clang warns about structs inside a union also needing the packed attribute. This files is copied from the chromeec project, so it adds comment next to the coreboot specific changes as a reference. TEST: google/vilboz remains the same with BUILD_TIMELESS=1 and gcc. Change-Id: I8b5233618081db86caedcb2d14870974e109ed9b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/ec/google/chromeec/ec_commands.h 1 file changed, 20 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/69742/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/69742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b5233618081db86caedcb2d14870974e109ed9b Gerrit-Change-Number: 69742 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Add romstage and configure LP5 memory parts
by Harsha B R (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Ashish Kumar Mishra, Subrata Banik, Rizwan Qureshi, Krishna P Bhat D, Ronak Kanabar, Usha P. Harsha B R has uploaded a new patch set (#12) to the change originally created by Ashish Kumar Mishra. ( https://review.coreboot.org/c/coreboot/+/69741 ) Change subject: mb/intel/mtlrvp: Add romstage and configure LP5 memory parts ...................................................................... mb/intel/mtlrvp: Add romstage and configure LP5 memory parts This patch adds initial romstage code and spd data for LP5 memory parts for MTL-RVP. This also configures memory based on the board id. BUG=b:224325352 TEST=Able to boot to intel/mtlrvp Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Change-Id: I15b352eb246aed23da273e56490c7094eae9d176 Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> --- M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/mtlrvp/Makefile.inc M src/mainboard/intel/mtlrvp/romstage_fsp_params.c A src/mainboard/intel/mtlrvp/spd/Makefile.inc A src/mainboard/intel/mtlrvp/spd/empty.spd.hex A src/mainboard/intel/mtlrvp/spd/hynix_mtlrvp_lp5.spd.hex A src/mainboard/intel/mtlrvp/spd/micron_mtlrvp_lp5.spd.hex M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp/memory.c 8 files changed, 208 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/69741/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/69741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15b352eb246aed23da273e56490c7094eae9d176 Gerrit-Change-Number: 69741 Gerrit-PatchSet: 12 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts
by Harsha B R (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Ashish Kumar Mishra, Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, Angel Pons, Krishna P Bhat D, Tarun Tuli, Jamie Ryu, Tim Wawrzynczak, Harsha B R, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Usha P, Raj Astekar. Harsha B R has uploaded a new patch set (#8) to the change originally created by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/66190 ) Change subject: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts ...................................................................... mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts This patch adds initial romstage code and spd data for DDR5 memory parts for MTL-RVP. This also configures memory based on the board id. BUG=b:224325352 TEST=Able to boot to intel/mtlrvp Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58 Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> --- M src/mainboard/intel/mtlrvp/Makefile.inc A src/mainboard/intel/mtlrvp/romstage_fsp_params.c M src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h A src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp/Makefile.inc A src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp/memory.c 5 files changed, 122 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/66190/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/66190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58 Gerrit-Change-Number: 66190 Gerrit-PatchSet: 8 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2022