coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

1 participants
7286 discussions

[XL] Change in coreboot[master]: G505S AtomBIOS ROMs: known good binaries with a script to check their...
by Martin L Roth (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Mike Banon. Martin L Roth has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/58748 ) Change subject: G505S AtomBIOS ROMs: known good binaries with a script to check their SHA256 ...................................................................... Removed Verified+1 by build bot (Jenkins) <no-reply(a)coreboot.org> -- To view, visit https://review.coreboot.org/c/coreboot/+/58748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5de87f3c1e054da146ebb58b441e433700f94e45 Gerrit-Change-Number: 58748 Gerrit-PatchSet: 3 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: deleteVote

1 0

[M] Change in coreboot[master]: libpayload: Outsource delay function into own header
by Thomas Heijligen (Code Review) 29 Nov '22

29 Nov '22

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70139 ) Change subject: libpayload: Outsource delay function into own header ...................................................................... libpayload: Outsource delay function into own header For libflashrom we need the delay functions but when including the whole libpayload.h it has conflicting symbols. Change-Id: I6e4a669b8ba25836fb870d74c200985c1bfdb387 Signed-off-by: Thomas Heijligen <src(a)posteo.de> --- M payloads/libpayload/include/libpayload.h A payloads/libpayload/include/libpayload/delay.h M payloads/libpayload/include/stddef.h 3 files changed, 71 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/70139/1 diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 1587118..221be46 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -68,6 +68,7 @@ #include <sysinfo.h> #include <pci.h> #include <archive.h> +#include <libpayload/delay.h> #define BIT(x) (1ul << (x)) @@ -510,54 +511,12 @@ /* Timer functions. */ /* Defined by each architecture. */ -unsigned int get_cpu_speed(void); uint64_t timer_hz(void); uint64_t timer_raw_value(void); uint64_t timer_us(uint64_t base); -void arch_ndelay(uint64_t n); /* Generic. */ /** - * Delay for a specified number of nanoseconds. - * - * @param ns Number of nanoseconds to delay for. - */ -static inline void ndelay(unsigned int ns) -{ - arch_ndelay((uint64_t)ns); -} - -/** - * Delay for a specified number of microseconds. - * - * @param us Number of microseconds to delay for. - */ -static inline void udelay(unsigned int us) -{ - arch_ndelay((uint64_t)us * NSECS_PER_USEC); -} - -/** - * Delay for a specified number of milliseconds. - * - * @param ms Number of milliseconds to delay for. - */ -static inline void mdelay(unsigned int ms) -{ - arch_ndelay((uint64_t)ms * NSECS_PER_MSEC); -} - -/** - * Delay for a specified number of seconds. - * - * @param s Number of seconds to delay for. - */ -static inline void delay(unsigned int s) -{ - arch_ndelay((uint64_t)s * NSECS_PER_SEC); -} - -/** * @defgroup readline Readline functions * This interface provides a simple implementation of the standard readline() * and getline() functions. They read a line of input from the console. diff --git a/payloads/libpayload/include/libpayload/delay.h b/payloads/libpayload/include/libpayload/delay.h new file mode 100644 index 0000000..96d029c --- /dev/null +++ b/payloads/libpayload/include/libpayload/delay.h @@ -0,0 +1,57 @@ +#ifndef LIBPAYLOAD_DELAY_H +#define LIBPAYLOAD_DELAY_H + +#include <stdint.h> + +#define NSECS_PER_SEC 1000000000 +#define USECS_PER_SEC 1000000 +#define MSECS_PER_SEC 1000 +#define NSECS_PER_MSEC (NSECS_PER_SEC / MSECS_PER_SEC) +#define NSECS_PER_USEC (NSECS_PER_SEC / USECS_PER_SEC) +#define USECS_PER_MSEC (USECS_PER_SEC / MSECS_PER_SEC) + +unsigned int get_cpu_speed(void); + +void arch_ndelay(uint64_t n); + +/** + * Delay for a specified number of nanoseconds. + * + * @param ns Number of nanoseconds to delay for. + */ +static inline void ndelay(unsigned int ns) +{ + arch_ndelay((uint64_t)ns); +} + +/** + * Delay for a specified number of microseconds. + * + * @param us Number of microseconds to delay for. + */ +static inline void udelay(unsigned int us) +{ + arch_ndelay((uint64_t)us * NSECS_PER_USEC); +} + +/** + * Delay for a specified number of milliseconds. + * + * @param ms Number of milliseconds to delay for. + */ +static inline void mdelay(unsigned int ms) +{ + arch_ndelay((uint64_t)ms * NSECS_PER_MSEC); +} + +/** + * Delay for a specified number of seconds. + * + * @param s Number of seconds to delay for. + */ +static inline void delay(unsigned int s) +{ + arch_ndelay((uint64_t)s * NSECS_PER_SEC); +} + +#endif /* LIBPAYLOAD_DELAY_H */ diff --git a/payloads/libpayload/include/stddef.h b/payloads/libpayload/include/stddef.h index 9003ac9..81aaa17 100644 --- a/payloads/libpayload/include/stddef.h +++ b/payloads/libpayload/include/stddef.h @@ -26,11 +26,4 @@ typedef __SIZE_TYPE__ ssize_t; #undef unsigned -#define NSECS_PER_SEC 1000000000 -#define USECS_PER_SEC 1000000 -#define MSECS_PER_SEC 1000 -#define NSECS_PER_MSEC (NSECS_PER_SEC / MSECS_PER_SEC) -#define NSECS_PER_USEC (NSECS_PER_SEC / USECS_PER_SEC) -#define USECS_PER_MSEC (USECS_PER_SEC / MSECS_PER_SEC) - #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/70139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e4a669b8ba25836fb870d74c200985c1bfdb387 Gerrit-Change-Number: 70139 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: libpayload: strings.h: Use builtin __ffs instead of included one
by Thomas Heijligen (Code Review) 29 Nov '22

29 Nov '22

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70118 ) Change subject: libpayload: strings.h: Use builtin __ffs instead of included one ...................................................................... libpayload: strings.h: Use builtin __ffs instead of included one Change-Id: Ie4d0b1b19ce6524341449df8bfabc66bff7bd97e Signed-off-by: Thomas Heijligen <src(a)posteo.de> --- M payloads/libpayload/include/strings.h 1 file changed, 11 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/70118/1 diff --git a/payloads/libpayload/include/strings.h b/payloads/libpayload/include/strings.h index e83d6c1..f8873b2 100644 --- a/payloads/libpayload/include/strings.h +++ b/payloads/libpayload/include/strings.h @@ -29,8 +29,6 @@ #ifndef _STRINGS_H #define _STRINGS_H -#include <libpayload.h> - -static inline int ffs(int i) { return __ffs(i) + 1; } +#define ffs(x) __builtin_ffs(x) #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/70118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4d0b1b19ce6524341449df8bfabc66bff7bd97e Gerrit-Change-Number: 70118 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: libpayload: bin/lpgcc allow to call without files
by Thomas Heijligen (Code Review) 29 Nov '22

29 Nov '22

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70117 ) Change subject: libpayload: bin/lpgcc allow to call without files ...................................................................... libpayload: bin/lpgcc allow to call without files Change-Id: I9e037ff44c0a6d0585d8a6f8aeabae6e651142e2 Signed-off-by: Thomas Heijligen <src(a)posteo.de> --- M payloads/libpayload/bin/lpgcc 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/70117/1 diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index 5e418e8..35fa558 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -229,5 +229,5 @@ # header to be placed below 0x2000 in the resulting image. See: # http://www.gnu.org/software/grub/manual/multiboot/html_node/OS-image-format… - $DEFAULT_CC $_LDFLAGS $HEAD_O $CMDLINE $_CFLAGS -lpayload $_LIBGCC + $DEFAULT_CC $_LDFLAGS $HEAD_O $CMDLINE $_CFLAGS -lpayload -xnone $_LIBGCC fi -- To view, visit https://review.coreboot.org/c/coreboot/+/70117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e037ff44c0a6d0585d8a6f8aeabae6e651142e2 Gerrit-Change-Number: 70117 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: commonlib/bsd, libpayload: Do not include helpers.h in stddef.h
by Thomas Heijligen (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Julius Werner. Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70116 ) Change subject: commonlib/bsd, libpayload: Do not include helpers.h in stddef.h ...................................................................... commonlib/bsd, libpayload: Do not include helpers.h in stddef.h `stddef.h` should only provide the definitions defined by ISO or Posix. The included `commonlib/bsd/helpers.h` provide a lot of non standard definitions that may interfere with definitions from the application. Change-Id: Ia71edbc3ffe6694ff4b971decf3a41f915264bc8 Signed-off-by: Thomas Heijligen <src(a)posteo.de> --- M payloads/libpayload/arch/x86/boot_media.c M payloads/libpayload/include/stddef.h M src/commonlib/bsd/cbfs_mcache.c M src/commonlib/bsd/cbfs_private.c 4 files changed, 21 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/70116/1 diff --git a/payloads/libpayload/arch/x86/boot_media.c b/payloads/libpayload/arch/x86/boot_media.c index 99fb4e3..76da39b 100644 --- a/payloads/libpayload/arch/x86/boot_media.c +++ b/payloads/libpayload/arch/x86/boot_media.c @@ -3,6 +3,7 @@ #include <arch/virtual.h> #include <boot_device.h> #include <commonlib/bsd/cb_err.h> +#include <commonlib/bsd/helpers.h> #include <stddef.h> #include <string.h> #include <sysinfo.h> diff --git a/payloads/libpayload/include/stddef.h b/payloads/libpayload/include/stddef.h index fb6ec9b..9003ac9 100644 --- a/payloads/libpayload/include/stddef.h +++ b/payloads/libpayload/include/stddef.h @@ -2,7 +2,10 @@ #define _STDDEF_H #include <arch/types.h> -#include <commonlib/bsd/helpers.h> + +#if !defined(offsetof) +#define offsetof(type, member) __builtin_offsetof(type, member) +#endif #ifndef __WCHAR_TYPE__ #define __WCHAR_TYPE__ int diff --git a/src/commonlib/bsd/cbfs_mcache.c b/src/commonlib/bsd/cbfs_mcache.c index 29ba110..8714cc0 100644 --- a/src/commonlib/bsd/cbfs_mcache.c +++ b/src/commonlib/bsd/cbfs_mcache.c @@ -2,6 +2,7 @@ #include <assert.h> #include <commonlib/bsd/cbfs_private.h> +#include <commonlib/bsd/helpers.h> /* * A CBFS metadata cache is an in memory data structure storing CBFS file headers (= metadata). diff --git a/src/commonlib/bsd/cbfs_private.c b/src/commonlib/bsd/cbfs_private.c index b9221fc..7ad2986 100644 --- a/src/commonlib/bsd/cbfs_private.c +++ b/src/commonlib/bsd/cbfs_private.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */ #include <commonlib/bsd/cbfs_private.h> +#include <commonlib/bsd/helpers.h> #include <assert.h> static enum cb_err read_next_header(cbfs_dev_t dev, size_t *offset, struct cbfs_file *buffer, -- To view, visit https://review.coreboot.org/c/coreboot/+/70116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia71edbc3ffe6694ff4b971decf3a41f915264bc8 Gerrit-Change-Number: 70116 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: libpayload/string: add strndup() function
by Thomas Heijligen (Code Review) 29 Nov '22

29 Nov '22

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70115 ) Change subject: libpayload/string: add strndup() function ...................................................................... libpayload/string: add strndup() function Change-Id: Ie509e49f21fb537692704ac6527efa09649164e3 Signed-off-by: Thomas Heijligen <src(a)posteo.de> --- M payloads/libpayload/include/string.h M payloads/libpayload/libc/string.c 2 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/70115/1 diff --git a/payloads/libpayload/include/string.h b/payloads/libpayload/include/string.h index 393881d..e87dea5 100644 --- a/payloads/libpayload/include/string.h +++ b/payloads/libpayload/include/string.h @@ -59,6 +59,7 @@ char *strchr(const char *s, int c); char *strrchr(const char *s, int c); char *strdup(const char *s); +char *strndup(const char *s, size_t size); char *strstr(const char *h, const char *n); char *strsep(char **stringp, const char *delim); size_t strspn(const char *s, const char *a); diff --git a/payloads/libpayload/libc/string.c b/payloads/libpayload/libc/string.c index 46c3c01..d1594f7 100644 --- a/payloads/libpayload/libc/string.c +++ b/payloads/libpayload/libc/string.c @@ -322,6 +322,27 @@ } /** + * Duplicate a string with a max length of size + * + * @param s The string to duplicate. + * @param size The max length of the string + * @return A pointer to the copy of the original string. + */ +char *strndup(const char *s, size_t size) +{ + size_t n = strlen(s); + n = n < size ? n : size; + char *p = malloc(n + 1); + + if (p != NULL) { + strncpy(p, s, n); + p[n] = 0; + } + return p; +} + + +/** * Find a substring within a string. * * @param h The haystack string. -- To view, visit https://review.coreboot.org/c/coreboot/+/70115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie509e49f21fb537692704ac6527efa09649164e3 Gerrit-Change-Number: 70115 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: mb/intel/mtlrvp: Add romstage and configure LP5 memory parts
by Harsha B R (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Ashish Kumar Mishra, Subrata Banik, Rizwan Qureshi, Krishna P Bhat D, Ronak Kanabar, Usha P. Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69741 ) Change subject: mb/intel/mtlrvp: Add romstage and configure LP5 memory parts ...................................................................... Patch Set 11: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69741/comment/c00bb8f5_9e8a821d PS10, Line 13: FW_NAME=mtlrvp_p emerge-rex coreboot chromeos-bootimage > Note: building the MTLRVP can't be a test statement, the purpose of the test is to ensure the code t […] Ack File src/mainboard/intel/mtlrvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/69741/comment/38c720c1_59fffe31 PS10, Line 23: spd_index = 1; > https://github.com/coreboot/coreboot/blob/master/src/mainboard/intel/adlrvp…. […] Many Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/69741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15b352eb246aed23da273e56490c7094eae9d176 Gerrit-Change-Number: 69741 Gerrit-PatchSet: 11 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Tue, 29 Nov 2022 18:55:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

1 0

[XL] Change in coreboot[master]: mb/intel/mtlrvp: Configure devicetree and GPIOs for MTL-RVP
by Harsha B R (Code Review) 29 Nov '22

29 Nov '22

1 0

[M] Change in coreboot[master]: G505S dGPU support: scripts for applying the unofficial (not-merged-y...
by Martin L Roth (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Mike Banon. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58745 ) Change subject: G505S dGPU support: scripts for applying the unofficial (not-merged-yet) patches ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > If you're pushing patches to the coreboot repo that can't possibly be merged, like this one, can you […] Maybe mark them as WIP or even abandon them so that people don't spend time reviewing them as well... -- To view, visit https://review.coreboot.org/c/coreboot/+/58745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25e1ec5e8bd32cf32d606e5272a4d0383a57ba81 Gerrit-Change-Number: 58745 Gerrit-PatchSet: 4 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Tue, 29 Nov 2022 18:53:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

1 0

[XL] Change in coreboot[master]: mb/intel/mtlrvp: Configure devicetree and GPIOs for MTL-RVP
by Harsha B R (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Subrata Banik, Haribalaraman Ramasubramanian, Krishna P Bhat D, Ronak Kanabar, Eric Lai. Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69396 ) Change subject: mb/intel/mtlrvp: Configure devicetree and GPIOs for MTL-RVP ...................................................................... Patch Set 19: (5 comments) File src/mainboard/intel/mtlrvp/variants/mtlrvp_p/devicetree.cb: https://review.coreboot.org/c/coreboot/+/69396/comment/b014015b_b4ac2c6b PS18, Line 1: # UPDATEME: Current setting is for VP > what is VP? Ack https://review.coreboot.org/c/coreboot/+/69396/comment/eb96e500_5809a39f PS18, Line 34: register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C port1 > can I have access to the schematics to review this code? Will come back on this. https://review.coreboot.org/c/coreboot/+/69396/comment/2a21d10c_4bc3eddf PS18, Line 61: register "gpio_pm[COMM_0]" = "0" : register "gpio_pm[COMM_1]" = "0" : register "gpio_pm[COMM_3]" = "0" : register "gpio_pm[COMM_4]" = "0" : register "gpio_pm[COMM_5]" = "0" > u don't need to set something to zero IMO. To confirm, Is the suggestion here to skip the initialization of the registers with value 0 ? File src/mainboard/intel/mtlrvp/variants/mtlrvp_p/gpio.c: https://review.coreboot.org/c/coreboot/+/69396/comment/552fb510_86bbf8e2 PS18, Line 10: /* Pad configuration in ramstage*/ : static const struct pad_config mtlmrvp_gpio_table[] = { : /* TODO: Add GPIO configuration for RVP-M */ : }; > keep this separate now, please add MTL-P support alone. Done https://review.coreboot.org/c/coreboot/+/69396/comment/99f2b416_19be8149 PS18, Line 412: case MTLM_LP5_RVP: : printk(BIOS_DEBUG, "configuring MTLM RVP gpios\n"); : gpio_configure_pads(mtlmrvp_gpio_table, ARRAY_SIZE(mtlmrvp_gpio_table)); > same Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3173c3f32b36d24467431df3652badd70efeab93 Gerrit-Change-Number: 69396 Gerrit-PatchSet: 19 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 29 Nov 2022 18:52:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2022