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Change in coreboot[master]: asus/a88xm-e: add the PIRQ routing table
by Mike Banon (Code Review) 29 Nov '22

29 Nov '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48426 ) Change subject: asus/a88xm-e: add the PIRQ routing table ...................................................................... asus/a88xm-e: add the PIRQ routing table Add the PIRQ routing table for this board. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I8fe3fb03ca0e7a2fecb92efeaf621925b198a39f --- M src/mainboard/asus/a88xm-e/Kconfig M src/mainboard/asus/a88xm-e/irq_tables.c 2 files changed, 68 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/48426/1 diff --git a/src/mainboard/asus/a88xm-e/Kconfig b/src/mainboard/asus/a88xm-e/Kconfig index 17fbe28..c889497 100644 --- a/src/mainboard/asus/a88xm-e/Kconfig +++ b/src/mainboard/asus/a88xm-e/Kconfig @@ -42,7 +42,7 @@ config IRQ_SLOT_COUNT int - default 11 + default 21 config VGA_BIOS_ID string diff --git a/src/mainboard/asus/a88xm-e/irq_tables.c b/src/mainboard/asus/a88xm-e/irq_tables.c index 7ca1c4b..47dbb11 100644 --- a/src/mainboard/asus/a88xm-e/irq_tables.c +++ b/src/mainboard/asus/a88xm-e/irq_tables.c @@ -1,84 +1,75 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/pirq_routing.h> -#include <console/console.h> -#include <device/pci_def.h> -#include <string.h> -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x14 << 3) | 0x3, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x1022, /* Vendor */ + 0x780e, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x14, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* IOMMU: 0:00.02 - IRQ 3 */ + {0x00, (0x00 << 3) | 0x2, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0} }, 0x0, 0x0}, + /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ + /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ + {0x00, (0x01 << 3) | 0x0, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ + {0x00, (0x02 << 3) | 0x0, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0} }, 0x0, 0x0}, + /* PCIe GPP to 2:00.00: 0:04.00 - IRQ 3 */ + {0x00, (0x04 << 3) | 0x0, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0} }, 0x0, 0x0}, + /* PCIe GPP to 3:00.00: 0:05.00 - IRQ 3 */ + {0x00, (0x05 << 3) | 0x0, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0} }, 0x0, 0x0}, + /* PCIe GPP to Eth 4:00.00: 0:06.00 - IRQ 4 */ + {0x00, (0x06 << 3) | 0x0, {{0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0}, {0x01, 0xccf0} }, 0x0, 0x0}, + /* USB XHCI: 0:10.00 - IRQ 5 */ + {0x00, (0x10 << 3) | 0x0, {{0x03, 0xccf0}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* SATA: 0:11.00 - IRQ 7 */ + {0x00, (0x11 << 3) | 0x0, {{0x04, 0xccf0}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* USB OHCI1: 0:12.00 - IRQ 5 */ + /* USB EHCI1: 0:12.02 - IRQ 4 */ + {0x00, (0x12 << 3) | 0x0, {{0x03, 0xccf0}, {0x02, 0xccf0}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* USB OHCI2: 0:13.00 - IRQ 5 */ + /* USB EHCI2: 0:13.02 - IRQ 4 */ + {0x00, (0x16 << 3) | 0x0, {{0x03, 0xccf0}, {0x02, 0xccf0}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* USB OHCI3: 0:16.00 - IRQ 5 */ + /* USB EHCI3: 0:16.02 - IRQ 4 */ + {0x00, (0x13 << 3) | 0x0, {{0x03, 0xccf0}, {0x02, 0xccf0}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ + /* USB OHCI4: 0:14.05 - IRQ 5 */ + {0x00, (0x14 << 3) | 0x0, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0} }, 0x0, 0x0}, + /* Southbridge PCI Port: 0:14.04 - IRQ 11 */ + {0x00, (0x14 << 3) | 0x4, {{0x05, 0xccf0}, {0x06, 0xccf0}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* Southbridge PCIe Port 1: 0:15.00 - IRQ 4 */ + {0x00, (0x15 << 3) | 0x0, {{0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0}, {0x01, 0xccf0} }, 0x0, 0x0}, + /* Southbridge PCIe Port 2: 0:15.01 - IRQ 5 */ + {0x00, (0x15 << 3) | 0x1, {{0x03, 0xccf0}, {0x04, 0xccf0}, {0x01, 0xccf0}, {0x02, 0xccf0} }, 0x0, 0x0}, + /* Southbridge PCIe Port 3: 0:15.02 - IRQ 7 */ + {0x00, (0x15 << 3) | 0x2, {{0x04, 0xccf0}, {0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0} }, 0x0, 0x0}, + /* Southbridge PCIe Port 4: 0:15.03 - IRQ 3 */ + {0x00, (0x15 << 3) | 0x3, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0} }, 0x0, 0x0}, + /* Discrete Graphics (dGPU) 1:00.00 behind a 0:02.00 PCIe GPP - IRQ 3 */ + {0x01, (0x00 << 3) | 0x0, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0} }, 0x1, 0x0}, + /* 2:00.00 behind a 0:04.00 PCIe GPP - IRQ 3 */ + {0x02, (0x00 << 3) | 0x0, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0} }, 0x2, 0x0}, + /* 3:00.00 behind a 0:05.00 PCIe GPP - IRQ 4 */ + {0x03, (0x00 << 3) | 0x0, {{0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0}, {0x01, 0xccf0} }, 0x3, 0x0}, + /* Onboard Ethernet (Eth) 4:00.00 behind a 0:06.00 PCIe GPP - IRQ 4 */ + {0x04, (0x00 << 3) | 0x0, {{0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0}, {0x01, 0xccf0} }, 0x4, 0x0} + } +}; unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr = ALIGN_UP(addr, 16); - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->slots); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - { - const u8 *const v = (u8 *)(pirq); - for (i = 0; i < pirq->size; i++) - sum += v[i]; - } - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) - pirq->checksum = sum; - - printk(BIOS_INFO, "%s done.\n", __func__); - - return (unsigned long)pirq_info; + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } -- To view, visit https://review.coreboot.org/c/coreboot/+/48426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fe3fb03ca0e7a2fecb92efeaf621925b198a39f Gerrit-Change-Number: 48426 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: asus/a88xm-e: properly program the IRQ tables
by Mike Banon (Code Review) 29 Nov '22

29 Nov '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48424 ) Change subject: asus/a88xm-e: properly program the IRQ tables ...................................................................... asus/a88xm-e: properly program the IRQ tables IRQ programming should be outside the obsolete MP table generation, just like the proper way done for asus/am1i-a AMD fam16h - closest example for ASUS A88XM-E: all the fam15h boards have these "bad IRQs". OS like Linux still finds a way, but Kolibri can't see the IRQ table. With this change applied: * A88XM-E boots fine to Linux - no angry IRQ-related messages at dmesg; * KolibriOS sees 16 IRQs in a table and could successfully attach a driver to Realtek RTL8168 onboard Ethernet controller with an IRQ 7. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I9a6ab9e24a828ebaffe87205a2ce0ebd811a935d --- M src/mainboard/asus/a88xm-e/mainboard.c M src/mainboard/asus/a88xm-e/mptable.c 2 files changed, 207 insertions(+), 69 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/48424/1 diff --git a/src/mainboard/asus/a88xm-e/mainboard.c b/src/mainboard/asus/a88xm-e/mainboard.c index 2e08188..5caf224 100644 --- a/src/mainboard/asus/a88xm-e/mainboard.c +++ b/src/mainboard/asus/a88xm-e/mainboard.c @@ -6,26 +6,54 @@ #include <device/device.h> #include <southbridge/amd/common/amd_pci_util.h> -static const u8 mainboard_picr_data[] = { - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, - 0x1F, 0x1F, 0x09, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, -}; -static const u8 mainboard_intr_data[84] = { - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, - 0x1F, 0x1F, 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x12, 0x13, +#include <southbridge/amd/agesa/hudson/pci_devs.h> +#include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> +#include <northbridge/amd/agesa/family15tn/pci_devs.h> + +extern const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE]; +extern const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE]; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ picr_data[PIRQ_A] if it uses PIN A for its hardware INT. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D} }, */ + {IOMMU_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* IOMMU: 0:00.02 - IRQ 3 */ + {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ + {ACTL_DEVFN, {PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC} }, /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to 2:00.00: 0:04.00 - IRQ 3 */ + {NB_PCIE_PORT4_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* PCIe GPP to 3:00.00: 0:05.00 - IRQ 4 */ + {NB_PCIE_PORT5_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* PCIe GPP to Eth 4:00.00: 0:06.00 - IRQ 4 */ + {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB XHCI: 0:10.00 - IRQ 5 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* SATA: 0:11.00 - IRQ 7 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI1: 0:12.00 - IRQ 5 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC} }, /* USB EHCI1: 0:12.02 - IRQ 4 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI2: 0:13.00 - IRQ 5 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC} }, /* USB EHCI2: 0:13.02 - IRQ 4 */ + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI3: 0:16.00 - IRQ 5 */ + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC} }, /* USB EHCI3: 0:16.02 - IRQ 4 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ + {SB_PCI_PORT_DEVFN, {PIRQ_E, PIRQ_F, PIRQ_NC, PIRQ_NC} }, /* Southbridge PCI Port: 0:14.04 - IRQ 11 */ + {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC} }, /* USB OHCI4: 0:14.05 - IRQ 5 */ + {SB_PCIE_PORT1_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* Southbridge PCIe Port 1: 0:15.00 - IRQ 4 */ + {SB_PCIE_PORT2_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B} }, /* Southbridge PCIe Port 2: 0:15.01 - IRQ 5 */ + {SB_PCIE_PORT3_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C} }, /* Southbridge PCIe Port 3: 0:15.02 - IRQ 7 */ + {SB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} } /* Southbridge PCIe Port 4: 0:15.03 - IRQ 3 */ }; /* PIRQ Setup */ static void pirq_setup(void) { + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); intr_data_ptr = mainboard_intr_data; picr_data_ptr = mainboard_picr_data; } @@ -36,6 +64,7 @@ msr_t msr; printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + /* Initialize the PIRQ data structures for consumption */ pirq_setup(); msr = rdmsr(LS_CFG_MSR); diff --git a/src/mainboard/asus/a88xm-e/mptable.c b/src/mainboard/asus/a88xm-e/mptable.c index b9e743c..5d9731f 100644 --- a/src/mainboard/asus/a88xm-e/mptable.c +++ b/src/mainboard/asus/a88xm-e/mptable.c @@ -1,10 +1,61 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/io.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> +#include <stdint.h> #include <string.h> #include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/hudson.h> +#include <drivers/generic/ioapic/chip.h> + +/* + * Based on 51205_Bolton_FCH_BIOS_Dev_Guide.pdf. Acronyms: + * + * SCI - System Controller Interrupt, + * SMBUS - System Management Bus, + * ASF - Advanced Synchronization Facility, + * HDA - HD Audio, + * SD - SD Flash Controller, + * GEC - Gigabit Ethernet Controller, + * PerMon - Performance Monitor, + * IMC - Integrated Memory Controller, + * GPP - PCIe General Purpose Ports. + */ + +const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, + /* Misc-nil,0,1,2, INTA-INTD from Serial irq */ + [0x08] = 0xAA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + /* SCI, SMBUS0, ASF, HDA, SD, GEC, PerMon */ + [0x10] = 0x09, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, + /* IMC INT0-INT5 */ + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + /* USB Devs: 18 INTA#,B#; 19 INTA#,B#; 22 INTA#,B#; 20 INTC# */ + [0x30] = 0x05, 0x04, 0x05, 0x04, 0x05, 0x04, 0x05, + /* IDE, SATA */ + [0x40] = 0x1F, 0x07, + /* GPP Int0-Int3 */ + [0x50] = 0x1F, 0x1F, 0x1F, 0x1F +}; + +const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x1F, 0x1F, + /* Misc-nil,0,1,2, INTA-INTD from Serial irq */ + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + /* SCI, SMBUS0, ASF, HDA, SD, GEC, PerMon */ + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, + /* IMC INT0-INT5 */ + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + /* USB Devs: 18 INTA#,B#; 19 INTA#,B#; 22 INTA#,B#; 20 INTC# */ + [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, + /* IDE, SATA */ + [0x40] = 0x1F, 0x13, + /* GPP Int0-Int3 */ + [0x50] = 0x1F, 0x1F, 0x1F, 0x1F +}; static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { @@ -37,92 +88,150 @@ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8); + /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); + /* + * Type 1: Bus Entries: + * Bus ID, Bus Type + */ + // mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; my_smp_write_bus(mc, bus_isa, "ISA "); - /* I/O APICs: APIC ID Version State Address */ + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,\ - bus_isa, (intr), (apicid), (pin)) + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source Bus ID, + * Source Bus IRQ, Dest APIC ID, Dest PIN# + */ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\ - (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - /* IOMMU */ - PCI_INT(0x0, 0x0, 0x0, 0x10); - PCI_INT(0x0, 0x0, 0x1, 0x11); - PCI_INT(0x0, 0x0, 0x2, 0x12); - PCI_INT(0x0, 0x0, 0x3, 0x13); + /* IOMMU: 0:00.02 - IRQ 3 */ + PCI_INT(0x0, 0x00, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x0, 0x00, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x00, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x00, 0x3, intr_data_ptr[PIRQ_D]); - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); + /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_A]); + /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_B]); - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); + /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ + PCI_INT(0x0, 0x02, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x0, 0x02, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x02, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x02, 0x3, intr_data_ptr[PIRQ_D]); + /* PCIe GPP to 2:00.00: 0:04.00 - IRQ 3 */ + PCI_INT(0x0, 0x04, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x0, 0x04, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x04, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x04, 0x3, intr_data_ptr[PIRQ_D]); + /* PCIe GPP to 3:00.00: 0:05.00 - IRQ 4 */ + PCI_INT(0x0, 0x05, 0x0, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x05, 0x1, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x05, 0x2, intr_data_ptr[PIRQ_D]); + PCI_INT(0x0, 0x05, 0x3, intr_data_ptr[PIRQ_A]); + /* PCIe GPP to Eth 4:00.00: 0:06.00 - IRQ 4 */ + PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x06, 0x1, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x06, 0x2, intr_data_ptr[PIRQ_D]); + PCI_INT(0x0, 0x06, 0x3, intr_data_ptr[PIRQ_A]); - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ + /* USB XHCI: 0:10.00 - IRQ 5 */ + PCI_INT(0x0, 0x10, 0x0, intr_data_ptr[PIRQ_C]); + /* SATA: 0:11.00 - IRQ 7 */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); + /* USB OHCI1: 0:12.00 - IRQ 5 */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); + /* USB EHCI1: 0:12.02 - IRQ 4 */ + PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); + /* USB OHCI2: 0:13.00 - IRQ 5 */ + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); + /* USB EHCI2: 0:13.02 - IRQ 4 */ + PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); + /* USB OHCI3: 0:16.00 - IRQ 5 */ + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); + /* USB EHCI3: 0:16.02 - IRQ 4 */ + PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]); + /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); + /* USB OHCI4: 0:14.05 - IRQ 5 */ + PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_C]); /* PCI slots */ struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); + /* PCI slot 0 */ + PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); + PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); } - /* PCIe Lan */ - PCI_INT(0x0, 0x06, 0x0, 0x13); + /* Southbridge PCIe Port 1: 0:15.00 - IRQ 4 */ + PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_B]); + /* Southbridge PCIe Port 2: 0:15.01 - IRQ 5 */ + PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_C]); + /* Southbridge PCIe Port 3: 0:15.02 - IRQ 7 */ + PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_D]); + /* Southbridge PCIe Port 4: 0:15.03 - IRQ 3 */ + PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); + /* Discrete Graphics (dGPU) 1:00.00 behind a 0:02.00 PCIe GPP - IRQ 3 */ + PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x1, 0x0, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x1, 0x0, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x1, 0x0, 0x3, intr_data_ptr[PIRQ_D]); - /* Local Ints: Type IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* 2:00.00 behind a 0:04.00 PCIe GPP - IRQ 3 */ + PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x2, 0x0, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x2, 0x0, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x2, 0x0, 0x3, intr_data_ptr[PIRQ_D]); + + /* 3:00.00 behind a 0:05.00 PCIe GPP - IRQ 4 */ + PCI_INT(0x3, 0x0, 0x0, intr_data_ptr[PIRQ_B]); + PCI_INT(0x3, 0x0, 0x1, intr_data_ptr[PIRQ_C]); + PCI_INT(0x3, 0x0, 0x2, intr_data_ptr[PIRQ_D]); + PCI_INT(0x3, 0x0, 0x3, intr_data_ptr[PIRQ_A]); + + /* Onboard Ethernet (Eth) 4:00.00 behind a 0:06.00 PCIe GPP - IRQ 4 */ + PCI_INT(0x4, 0x0, 0x0, intr_data_ptr[PIRQ_B]); + PCI_INT(0x4, 0x0, 0x1, intr_data_ptr[PIRQ_C]); + PCI_INT(0x4, 0x0, 0x2, intr_data_ptr[PIRQ_D]); + PCI_INT(0x4, 0x0, 0x3, intr_data_ptr[PIRQ_A]); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)) + + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a6ab9e24a828ebaffe87205a2ce0ebd811a935d Gerrit-Change-Number: 48424 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: lenovo/g505s: add the PIRQ routing table
by build bot (Jenkins) (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Alexander Couzens, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58752 ) Change subject: lenovo/g505s: add the PIRQ routing table ...................................................................... Patch Set 4: Verified+1 (1 comment) File src/mainboard/lenovo/g505s/irq_tables.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164823): https://review.coreboot.org/c/coreboot/+/58752/comment/8538fbf4_b1bf7dd3 PS4, Line 22: /* bus, dev | fn, {{link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap} }, slot, rfu */ line length of 121 exceeds 118 columns -- To view, visit https://review.coreboot.org/c/coreboot/+/58752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92ed902e119208e5607003c9e691c35d87a2e50d Gerrit-Change-Number: 58752 Gerrit-PatchSet: 4 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 29 Nov 2022 18:22:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: util/crossgcc: Add option to get packages from coreboot's mirror
by Martin L Roth (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Felix Singer, Patrick Georgi, Paul Menzel, Angel Pons. Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Paul Menzel, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70053 to look at the new patch set (#3). Change subject: util/crossgcc: Add option to get packages from coreboot's mirror ...................................................................... util/crossgcc: Add option to get packages from coreboot's mirror coreboot has been keeping a mirror of all the toolchain packages used for releases for quite a while now. This adds an option to fetch the packages from the coreboot mirror directly to buildgcc. This can help with both our releases and when one of the various servers experiences interruptions or changes a path. To do this, the URL and filename needed to be split apart, which led to quite a few changes in the buildgcc script. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I7df58dca152e7bfe9fde34d290e05b52515b20d9 --- M util/crossgcc/Makefile.inc M util/crossgcc/buildgcc 2 files changed, 83 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/70053/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/70053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7df58dca152e7bfe9fde34d290e05b52515b20d9 Gerrit-Change-Number: 70053 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: commonlib/helpers.h: use unsigned literals in definitions
by Sergii Dmytruk (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Krystian Hebel. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70106 ) Change subject: commonlib/helpers.h: use unsigned literals in definitions ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/70106/comment/951c9048_19f315a3 PS1, Line 21: so if result of : multiplication is negative If result of multiplying two positive integers is negative, further integer promotions don't matter much, because you've already got an undefined behaviour. I'd think of marking these constants as `LL` or `ULL`, otherwise the problem will repeat itself for `4295*MHz` some time later. The advantage of `LL` is that UBSan or something like it should report such an overflow, while wrapping of `ULL` is well defined. -- To view, visit https://review.coreboot.org/c/coreboot/+/70106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie60a6ee82db80328e44639175272cc8097f36c3b Gerrit-Change-Number: 70106 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Tue, 29 Nov 2022 18:07:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal para...
by Raul Rangel (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Jason Glenesk, Jason Nien, EricKY Cheng, Matt DeVillier, Chris Wang, Martin Roth, Tim Van Patten, Fred Reitberger, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68649 ) Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters ...................................................................... Patch Set 31: (1 comment) File src/soc/amd/mendocino/root_complex.c: https://review.coreboot.org/c/coreboot/+/68649/comment/68e5dbc8_c929eb1e PS16, Line 393: #else > > IMO we need to refactor the parameter code and allow us to specify the parameters we want to chang […] Agree'd. We would need to use the default as our base, and the other tables as override values. Just like we do for the GPIO config. Agree'd we can do this as a follow up. -- To view, visit https://review.coreboot.org/c/coreboot/+/68649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8 Gerrit-Change-Number: 68649 Gerrit-PatchSet: 31 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 29 Nov 2022 18:04:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Comment-In-Reply-To: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [WIP] vc/amd/fsp/mendocino/FspmUpd: don't use pointers for usb_phy co...
by Fred Reitberger (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70135 ) Change subject: [WIP] vc/amd/fsp/mendocino/FspmUpd: don't use pointers for usb_phy config ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Not working on chausie when 64-bit is enabled. Seems to get stuck at the start of fsp-m (no more console output, even with a serial fsp-m). 32-bit build still booted to OS. -- To view, visit https://review.coreboot.org/c/coreboot/+/70135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I419fef73d2881e323487bc7fe641b2ac4041cb17 Gerrit-Change-Number: 70135 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 29 Nov 2022 17:57:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/acpi: Implement DTTS Proposal
by Tim Van Patten (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Raul Rangel, Jason Nien, EricKY Cheng, Matt DeVillier, Paul Menzel, Eric Lai, Martin Roth, Eric Peers, LeilaCY Lin, Jason Glenesk, Caveh Jalali, Tim Wawrzynczak, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68471 ) Change subject: soc/amd/common/acpi: Implement DTTS Proposal ...................................................................... Patch Set 71: (1 comment) File src/soc/amd/common/acpi/dtts.asl: https://review.coreboot.org/c/coreboot/+/68471/comment/425dff92_505f6137 PS71, Line 13: // Set table A as default table after power on device : If (\_SB.PRTN == 7) : { : \_SB.DDEF() : Store (0, \_SB.PRTN) : Return (Zero) : } > Jut an FYI: The values from the "default" table will be passed into FSP and FSP will perform the ini […] Adding to this, the FSP update work is being tracked in b/245942343. That bug is currently only for adding the following: ``` vrm_current_limit_mA; vrm_maximum_current_limit_mA; vrm_soc_current_limit_mA; ``` I'll point that bug to this CL though, so we can make sure everything is added. -- To view, visit https://review.coreboot.org/c/coreboot/+/68471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Gerrit-Change-Number: 68471 Gerrit-PatchSet: 71 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 29 Nov 2022 17:55:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/meteorlake: Refactor `pmc_lockdown_cfg` function
by Subrata Banik (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Tarun Tuli, Eran Mitrani, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70132 ) Change subject: soc/intel/meteorlake: Refactor `pmc_lockdown_cfg` function ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3622748d8fecef69c60bb3fe9bfe68fc126764b7 Gerrit-Change-Number: 70132 Gerrit-PatchSet: 5 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 29 Nov 2022 17:52:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/zork: Select VBOOT by default
by Matt DeVillier (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Jason Nien, Martin Roth, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69763 ) Change subject: mb/google/zork: Select VBOOT by default ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/zork/Kconfig: https://review.coreboot.org/c/coreboot/+/69763/comment/e2095292_26d7faa2 PS2, Line 108: > would be good to add a comment that points out that this is done due to psp verstage being mandatory […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2447bf69baefd5560a0153dcd3d9b87b0a91a3f9 Gerrit-Change-Number: 69763 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 29 Nov 2022 17:50:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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coreboot-gerrit November 2022