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Change subject: soc/amd/mendocino: Update XHCI GPE to use constant
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Patch Set 5: Code-Review+1
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Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters
......................................................................
Patch Set 31:
(1 comment)
File src/soc/amd/mendocino/root_complex.c:
https://review.coreboot.org/c/coreboot/+/68649/comment/56309812_d9f5a44b
PS16, Line 393: #else
> IMO we need to refactor the parameter code and allow us to specify the parameters we want to change in the device tree.
I like the idea of simplifying in this area and reducing duplication of values, but it needs to be done carefully. For example, low/no battery will throttle the current limits (among others), while the thermal tables will modify other limits. In that case, this type of scenario could occur:
1. Normal Mode, fully unthrottled
1. Thermal limit reached, throttle based on tables B-E
1. Battery drains, throttle SOC
1. Charger is plugged in, battery charges, unthrottle the SOC
Step (4) is where the complexity comes in: which parameters need to be restored (and to what values) when there is overlap of modified values between the tables (e.g., `sustained_power_limit_mW`)? Setting every value for each table means we don't need to know which table was previously applied, since none of the old values will persist.
In this case, using your example tables, we need to apply both `stt_default_config` (to restore everything, including the VRM limits) and then the appropriate thermal table to apply the desired `sustained_power_limit_mW` (among others). Currently, we only support setting one (full) table at a time, so that logic would need to be updated as well.
It's just code, so anything is possible. I'd prefer to leave this as a follow-on improvement though, so we can make progress here and then refactor once we have all of the requirements.
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Change subject: util/crossgcc: Add option to get packages from coreboot's mirror
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/70053/comment/8368464b_6d95e829
PS1, Line 7: util/crossgcc: Add option to get packages from coreboot's mirror
> Thank you. I started this one too, to use a local GNU (FTP) mirror [1], and GCC mirror [2]. […]
I'm not in favor about adding a flag to override individual URLs, but we could look at letting the BASEURLs be overridden in the environment.
We could also look at adding a list of mirrors to try.
I'll look at adding those options in a follow-on patch.
https://review.coreboot.org/c/coreboot/+/70053/comment/98fca387_f80b3013
PS1, Line 12:
> Maybe mention, that sometimes there are problems with the GNU FTP mirrors.
Done
Patchset:
PS1:
> It's not just this patch. Others of mine are also affected. […]
This was a server issue. It's fixed now.
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Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
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Change subject: util/crossgcc: Add option to get packages from coreboot's mirror
......................................................................
util/crossgcc: Add option to get packages from coreboot's mirror
coreboot has been keeping a mirror of all the toolchain packages used
for releases for quite a while now. This adds an option to fetch the
packages from the coreboot mirror directly to buildgcc.
This can help with both our releases and when one of the various
servers experiences interruptions or changes a path.
To do this, the URL and filename needed to be split apart, which led to
quite a few changes in the buildgcc script.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I7df58dca152e7bfe9fde34d290e05b52515b20d9
---
M util/crossgcc/Makefile.inc
M util/crossgcc/buildgcc
2 files changed, 83 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/70053/2
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Change subject: soc/intel/meteorlake: Refactor `pmc_lockdown_cfg` function
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Patch Set 5:
This change is ready for review.
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Change subject: util/xcompile: Add --no-warn-rwx-segments to arm64 LD params
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Felix, Please go ahead and take over the patch, I haven't had time to work on it.
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Change subject: Documentation: Add wake source info to device tree documentation
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Patch Set 6: Code-Review+2
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Change subject: Documentation: Add wake source info to device tree documentation
......................................................................
Patch Set 5:
(1 comment)
File Documentation/drivers/dt_entries.md:
https://review.coreboot.org/c/coreboot/+/67385/comment/6be1c686_60d4edc7
PS5, Line 233: feasible. The other option is to wake a wake capable GPIO as describes below.
> 'wake a wake' is confusing, can we say use a wake capable GPIO or something similar?
Done
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I'd like you to reexamine a change. Please visit
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Change subject: Documentation: Add wake source info to device tree documentation
......................................................................
Documentation: Add wake source info to device tree documentation
The device tree documentation was promoting using a GPIO wake event and
a GPE wake event. We should only ever have one. This wasn't actually
causing a problem because the wake bit was set on the `irq` property,
but the IO-APIC can't actually wake the system, so it was a no-op.
This change fixes up the markdown so it's formatted correctly, and also
adds a section explaining what the different wake configurations are.
BUG=b:243700486
TEST=mdformat
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ifcdbd5371408784bf9b81c1ade90263de8c60e0f
---
M Documentation/drivers/dt_entries.md
1 file changed, 113 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/67385/6
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