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[S] Change in coreboot[master]: sb/intel: Use boolean for c4onc3_enable
by Elyes Haouas (Code Review) 29 Nov '22

29 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70112 ) Change subject: sb/intel: Use boolean for c4onc3_enable ...................................................................... sb/intel: Use boolean for c4onc3_enable Change-Id: Ib4a5ea5f71579610721c91e8a7412da615c0d150 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/devicetree.cb M src/mainboard/lenovo/t400/devicetree.cb M src/mainboard/lenovo/t60/devicetree.cb M src/mainboard/lenovo/x200/devicetree.cb M src/mainboard/lenovo/x60/devicetree.cb M src/mainboard/roda/rk9/devicetree.cb M src/southbridge/intel/i82801gx/chip.h M src/southbridge/intel/i82801ix/chip.h M src/southbridge/intel/i82801jx/chip.h 9 files changed, 15 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/70112/1 diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index bcce778..6b36f3e 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -56,8 +56,6 @@ register "ide_enable_primary" = "1" register "ide_enable_secondary" = "1" - register "c4onc3_enable" = "1" - register "c3_latency" = "0x23" register "p_cnt_throttling_supported" = "1" diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 57f1f37..4634c71 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -64,8 +64,6 @@ register "sata_traffic_monitor" = "0" # Set c-state support - register "c4onc3_enable" = "1" - register "c5_enable" = "1" register "c6_enable" = "1" # Set thermal throttling to 75%. diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index dd24736..0c2ba23 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -61,7 +61,6 @@ register "gpe0_en" = "0x11000006" register "alt_gp_smi_en" = "0x1000" - register "c4onc3_enable" = "1" register "c3_latency" = "0x23" register "p_cnt_throttling_supported" = "1" diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 059dc00..e0eefe7 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -63,7 +63,6 @@ register "sata_traffic_monitor" = "0" # Set c-state support - register "c4onc3_enable" = "1" register "c5_enable" = "1" register "c6_enable" = "1" diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index f42b628..2f94328 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -54,8 +54,6 @@ register "gpe0_en" = "0x11000006" register "alt_gp_smi_en" = "0x1000" - register "c4onc3_enable" = "1" - register "c3_latency" = "0x23" register "p_cnt_throttling_supported" = "1" diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb index c9c1896..fbb026b 100644 --- a/src/mainboard/roda/rk9/devicetree.cb +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -51,7 +51,6 @@ register "sata_traffic_monitor" = "0" # Set c-state support - register "c4onc3_enable" = "0" register "c5_enable" = "1" register "c6_enable" = "1" diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 02da70a..6711ef79 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -63,7 +63,7 @@ /* Enable linear PCIe Root Port function numbers starting at zero */ bool pcie_port_coalesce; - int c4onc3_enable:1; + bool c4onc3_enable:true; bool docking_supported:true; int p_cnt_throttling_supported:1; int c3_latency; diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h index ec7b977..968a81f 100644 --- a/src/southbridge/intel/i82801ix/chip.h +++ b/src/southbridge/intel/i82801ix/chip.h @@ -3,7 +3,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82801IX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801IX_CHIP_H -#include <stdint.h> +#include <types.h> enum { THTL_DEF = 0, THTL_87_5 = 1, THTL_75_0 = 2, THTL_62_5 = 3, @@ -58,7 +58,7 @@ unsigned int sata_clock_request : 1; unsigned int sata_traffic_monitor : 1; - unsigned int c4onc3_enable:1; + bool c4onc3_enable:true; unsigned int c5_enable : 1; unsigned int c6_enable : 1; diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index ae31d4f..e36cce9 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -3,7 +3,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82801JX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801JX_CHIP_H -#include <stdint.h> +#include <types.h> enum { THTL_DEF = 0, THTL_87_5 = 1, THTL_75_0 = 2, THTL_62_5 = 3, @@ -44,7 +44,7 @@ uint8_t sata_port_map : 6; unsigned int sata_clock_request : 1; - unsigned int c4onc3_enable:1; + bool c4onc3_enable:true; unsigned int c5_enable : 1; unsigned int c6_enable : 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/70112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4a5ea5f71579610721c91e8a7412da615c0d150 Gerrit-Change-Number: 70112 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: util/ectool/Makefile : improve cross-compilation support
by Paul Menzel (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Nico Huber, maciej.gabryelski(a)3mdeb.com, Martin L Roth, Michał Kotyla. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70102 ) Change subject: util/ectool/Makefile : improve cross-compilation support ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/70102/comment/3f1ae7a4_3299f595 PS1, Line 7: util/ectool/Makefile : Please remove the space before the colon. https://review.coreboot.org/c/coreboot/+/70102/comment/2efc74e2_c438dee5 PS1, Line 11: buildsystem like Yocto Please add a dot/period at the end of sentences. File util/ectool/Makefile: https://review.coreboot.org/c/coreboot/+/70102/comment/a864555e_bfe5750b PS1, Line 3: CC ?= gcc Do you have more information regarding this. I did this in the past, but found out, that passing it as a “make variable” (and not environment) it can be easily overridden, so stayed away from it. So, make CC=clang works already. Why should `CC=clang make` be supported too? Please elaborate in the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/70102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5c88bde0ae00f0211a250906cbdedfe4f59c67b Gerrit-Change-Number: 70102 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kotyla Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: maciej.gabryelski(a)3mdeb.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: maciej.gabryelski(a)3mdeb.com Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Kotyla Gerrit-Comment-Date: Tue, 29 Nov 2022 16:11:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: sb/intel: Use boolean for docking_supported
by Elyes Haouas (Code Review) 29 Nov '22

29 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70111 ) Change subject: sb/intel: Use boolean for docking_supported ...................................................................... sb/intel: Use boolean for docking_supported Change-Id: I1df5a0bd914c11993ce291939f68848bcce0c638 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/compulab/intense_pc/devicetree.cb M src/mainboard/getac/p470/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb M src/mainboard/hp/z220_series/devicetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/t60/devicetree.cb M src/mainboard/lenovo/x201/devicetree.cb M src/mainboard/lenovo/x230/variants/x230/overridetree.cb M src/mainboard/lenovo/x60/devicetree.cb M src/mainboard/msi/ms7707/devicetree.cb M src/mainboard/roda/rk886ex/devicetree.cb M src/southbridge/intel/bd82x6x/chip.h M src/southbridge/intel/i82801gx/chip.h M util/autoport/main.go 22 files changed, 29 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/70111/1 diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index 6ea033e..beda6e6 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -25,7 +25,7 @@ device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "docking_supported" = "0" + register "docking_supported" = "false" register "gen1_dec" = "0x000c0681" register "gen2_dec" = "0x000c1641" register "gen3_dec" = "0x001c0301" diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 0f7d0a8..78371bf 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -33,7 +33,7 @@ subsystemid 0x1849 0x0152 end chip southbridge/intel/bd82x6x - register "docking_supported" = "0" + register "docking_supported" = "false" register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0241" register "gen3_dec" = "0x000c0251" diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index 6979615..af21a72 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -31,7 +31,7 @@ subsystemid 0x8086 0x7270 inherit chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "docking_supported" = "1" + register "docking_supported" = "true" register "gen1_dec" = "0x0000164d" register "gen2_dec" = "0x000c0681" register "gen3_dec" = "0x000406f1" diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index 9a91b81..fd551cb 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -45,7 +45,6 @@ register "ide_enable_secondary" = "0x0" register "c3_latency" = "85" - register "docking_supported" = "1" register "p_cnt_throttling_supported" = "1" register "gen1_dec" = "0x001c02e1" diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 98e48ef..3ea65e5 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -24,7 +24,7 @@ device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "docking_supported" = "0" + register "docking_supported" = "false" register "gen1_dec" = "0x00fc0601" register "gen2_dec" = "0x00fc0801" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb index 7244acd..4084d8d 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb @@ -11,7 +11,7 @@ device pci 02.0 off end # Internal graphics chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH - register "docking_supported" = "0" + register "docking_supported" = "false" # mailbox at 0x200/0x201 and PM1 at 0x220 register "gen1_dec" = "0x007c0201" register "gen2_dec" = "0x000c0101" diff --git a/src/mainboard/hp/z220_series/devicetree.cb b/src/mainboard/hp/z220_series/devicetree.cb index bcacf71..d5f2f2e 100644 --- a/src/mainboard/hp/z220_series/devicetree.cb +++ b/src/mainboard/hp/z220_series/devicetree.cb @@ -25,7 +25,7 @@ device pci 06.0 off end # Extra x4 port on north bridge chip southbridge/intel/bd82x6x # Intel Series 7 PCH - register "docking_supported" = "0" + register "docking_supported" = "false" register "gen1_dec" = "0x00fc0601" register "gen2_dec" = "0x00fc0801" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 6c2dabe..88adf5b 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -30,7 +30,7 @@ device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "docking_supported" = "1" + register "docking_supported" = "true" register "gen1_dec" = "0x007c1611" register "gen2_dec" = "0x00040069" register "gen3_dec" = "0x000c0701" diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index f7d65ca..dda8393 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -28,7 +28,7 @@ device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "docking_supported" = "1" + register "docking_supported" = "true" register "gen1_dec" = "0x00000000" register "gen2_dec" = "0x000c0701" register "gen3_dec" = "0x000c0069" diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 200cabb..6bd90fb 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -48,7 +48,7 @@ register "gen3_dec" = "0x1c1681" # EC ? register "gen4_dec" = "0x040069" # ? - register "docking_supported" = "1" + register "docking_supported" = "true" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 141faa9..7931284 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -28,7 +28,7 @@ subsystemid 0x17aa 0x21f3 inherit chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "docking_supported" = "1" + register "docking_supported" = "true" register "gen1_dec" = "0x000c15e1" register "gen2_dec" = "0x007c1601" register "gen3_dec" = "0x000c06a1" diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 739d01d..b3635b1 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -59,7 +59,7 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" - register "docking_supported" = "1" + register "docking_supported" = "true" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 5cfa207..afbd3ba 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -60,7 +60,7 @@ register "superspeed_capable_ports" = "0xf" register "xhci_overcurrent_mapping" = "0x04000201" - register "docking_supported" = "1" + register "docking_supported" = "true" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 7709a87..dd24736 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -63,7 +63,6 @@ register "c4onc3_enable" = "1" register "c3_latency" = "0x23" - register "docking_supported" = "1" register "p_cnt_throttling_supported" = "1" register "gen1_dec" = "0x007c1601" diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index fc7c470..e9f60b0 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -48,7 +48,7 @@ register "gen3_dec" = "0x1c1681" register "gen4_dec" = "0x040069" - register "docking_supported" = "1" + register "docking_supported" = "true" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb index 978d017..06b905e 100644 --- a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb +++ b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb @@ -1,7 +1,7 @@ chip northbridge/intel/sandybridge device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH - register "docking_supported" = "1" + register "docking_supported" = "true" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" device pci 1c.2 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 8620062..f42b628 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -57,7 +57,6 @@ register "c4onc3_enable" = "1" register "c3_latency" = "0x23" - register "docking_supported" = "1" register "p_cnt_throttling_supported" = "1" register "gen1_dec" = "0x007c1601" diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index 8e5df58..d8590a8 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -16,7 +16,7 @@ device pci 02.0 off end # Internal graphics chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "docking_supported" = "0" + register "docking_supported" = "false" register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0a01" register "pcie_port_coalesce" = "true" diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 6b9dbd9..978fb04 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -40,7 +40,6 @@ register "gpe0_en" = "0x20800007" register "c3_latency" = "0x23" - register "docking_supported" = "1" register "p_cnt_throttling_supported" = "1" register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED" diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 30c2675..6aa18c4 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -63,7 +63,7 @@ /* Override PCIe ASPM */ uint8_t pcie_aspm[8]; - int docking_supported; + bool docking_supported; uint8_t pcie_hotplug_map[8]; diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 09a7126..02da70a 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -64,7 +64,7 @@ bool pcie_port_coalesce; int c4onc3_enable:1; - int docking_supported:1; + bool docking_supported:true; int p_cnt_throttling_supported:1; int c3_latency; diff --git a/util/autoport/main.go b/util/autoport/main.go index 9b0b436..254c464 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -137,9 +137,9 @@ func FormatBool(inp bool) string { if inp { - return "1" + return "true" } else { - return "0" + return "false" } } -- To view, visit https://review.coreboot.org/c/coreboot/+/70111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1df5a0bd914c11993ce291939f68848bcce0c638 Gerrit-Change-Number: 70111 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: [WIP] vc/amd/fsp/cezanne/FspmUpd: don't use pointers for usb_phy conf...
by Felix Held (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Jason Glenesk, Matt DeVillier. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69897 ) Change subject: [WIP] vc/amd/fsp/cezanne/FspmUpd: don't use pointers for usb_phy configuration ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > This should work for mendocino too i'll port this forward to mendocino. initially wrote that for cezanne, but turned out that my majolica with non-chrome apu runs into some issue before it releases the x86 cores from reset, so it's still untested. if it'll work on mendocino, i'd be confident enough that it'll also work on cezanne -- To view, visit https://review.coreboot.org/c/coreboot/+/69897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81f3a38344f91cecb4fe5431ed211834e5ed599c Gerrit-Change-Number: 69897 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Tue, 29 Nov 2022 16:07:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal para...
by Raul Rangel (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Jason Glenesk, Jason Nien, EricKY Cheng, Matt DeVillier, Chris Wang, Martin Roth, Tim Van Patten, Fred Reitberger, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68649 ) Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters ...................................................................... Patch Set 31: Code-Review+2 (1 comment) File src/soc/amd/mendocino/root_complex.c: https://review.coreboot.org/c/coreboot/+/68649/comment/747da3e1_6b5feb6a PS16, Line 393: #else > Hi Tim, […] Thanks for checking on that Chris. IMO we need to refactor the parameter code and allow us to specify the parameters we want to change in the device tree. i.e., ``` stt_default_config = "{ {ALIB_DPTC_THERMAL_CONTROL_LIMIT_ID, xxxx}, {ALIB_DPTC_VRM_MAXIMUM_CURRENT_LIMIT, xxxx}, }" no_battery_config = "{ {ALIB_DPTC_VRM_MAXIMUM_CURRENT_LIMIT, xxxx}, }" ``` Maybe this can be a refactor someone wants to take on ? :) -- To view, visit https://review.coreboot.org/c/coreboot/+/68649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8 Gerrit-Change-Number: 68649 Gerrit-PatchSet: 31 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 29 Nov 2022 16:04:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Comment-In-Reply-To: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Update PMC register definition
by Kapil Porwal (Code Review) 29 Nov '22

29 Nov '22

Kapil Porwal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70134 ) Change subject: soc/intel/meteorlake: Update PMC register definition ...................................................................... soc/intel/meteorlake: Update PMC register definition Update GEN_PMCON_B and PMSYNC_TPR_CFG register definition. BUG=none TEST=Boot to OS on google/rex. Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I9508ecb8fd89fc6519317cf006f177b54d8e6b26 --- M src/soc/intel/meteorlake/include/soc/pmc.h 1 file changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/70134/1 diff --git a/src/soc/intel/meteorlake/include/soc/pmc.h b/src/soc/intel/meteorlake/include/soc/pmc.h index a56c290..e0a113b 100644 --- a/src/soc/intel/meteorlake/include/soc/pmc.h +++ b/src/soc/intel/meteorlake/include/soc/pmc.h @@ -51,6 +51,7 @@ #define SLEEP_AFTER_POWER_FAIL (1 << 0) #define GEN_PMCON_B 0x1024 +#define ST_FDIS_LOCK (1 << 21) #define SLP_STR_POL_LOCK (1 << 18) #define ACPI_BASE_LOCK (1 << 17) #define PM_DATA_BAR_DIS (1 << 16) @@ -96,7 +97,7 @@ #define DSX_EN_LAN_WAKE_PIN (1 << 0) #define DSX_CFG_MASK (0x1f << 0) -#define PMSYNC_TPR_CFG 0x18C4 +#define PMSYNC_TPR_CFG 0x18D4 #define PCH2CPU_TPR_CFG_LOCK (1 << 31) #define PCH2CPU_TT_EN (1 << 26) -- To view, visit https://review.coreboot.org/c/coreboot/+/70134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9508ecb8fd89fc6519317cf006f177b54d8e6b26 Gerrit-Change-Number: 70134 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: [WIP] soc/amd/cezanne: Add support for 64bit builds
by Fred Reitberger (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Jason Glenesk, Matt DeVillier, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69898 ) Change subject: [WIP] soc/amd/cezanne: Add support for 64bit builds ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77d468983f0e3feaa6cd589ef9a54af8892b48ce Gerrit-Change-Number: 69898 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 29 Nov 2022 16:01:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [WIP] vc/amd/fsp/cezanne/FspmUpd: don't use pointers for usb_phy conf...
by Fred Reitberger (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Jason Glenesk, Matt DeVillier, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69897 ) Change subject: [WIP] vc/amd/fsp/cezanne/FspmUpd: don't use pointers for usb_phy configuration ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: This should work for mendocino too -- To view, visit https://review.coreboot.org/c/coreboot/+/69897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81f3a38344f91cecb4fe5431ed211834e5ed599c Gerrit-Change-Number: 69897 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 29 Nov 2022 16:01:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/amd/chausie: change AMD_FWM_POSITION_INDEX for non-chromeos case
by Felix Held (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Jason Glenesk, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70133 to look at the new patch set (#3). Change subject: mb/amd/chausie: change AMD_FWM_POSITION_INDEX for non-chromeos case ...................................................................... mb/amd/chausie: change AMD_FWM_POSITION_INDEX for non-chromeos case Commit 2c102232e8f7 ("mb/amd/chausie,google/skyrim: increase RW_MRC_CACHE size to 120 kByte") increased the MRC cache size, but with the change the default AMD_FWM_POSITION_INDEX which is 5 for the 16MByte flash size, the amdfw part won't be placed on the expected position, since the cbfs header is in that exact location and cbfstool places the amdfw part right after that. Change the AMD_FWM_POSITION_INDEX to 4 for the non-chromeos builds to work around this. TEST=Non-chromeos chausie build now boots and doesn't fail any more before releasing the x86 cores from reset Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I89fe1d0672139e04070f05c6c8fa8955edcfc7ee --- M src/mainboard/amd/chausie/Kconfig 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/70133/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/70133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89fe1d0672139e04070f05c6c8fa8955edcfc7ee Gerrit-Change-Number: 70133 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/amd/chausie: change AMD_FWM_POSITION_INDEX for non-chromeos case
by Fred Reitberger (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Jason Glenesk, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70133 ) Change subject: mb/amd/chausie: change AMD_FWM_POSITION_INDEX for non-chromeos case ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89fe1d0672139e04070f05c6c8fa8955edcfc7ee Gerrit-Change-Number: 70133 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 29 Nov 2022 15:57:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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