coreboot-gerrit November 2022

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[S] Change in coreboot[master]: tests/Makefile.common: Allow to disable test framework with parameter
by Jakub Czapiga (Code Review) 29 Nov '22

29 Nov '22

Jakub Czapiga has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/70107 ) Change subject: tests/Makefile.common: Allow to disable test framework with parameter ...................................................................... tests/Makefile.common: Allow to disable test framework with parameter Test framework can be used as a base for other test-like utilities - for example look at screenshoot utility in depthcharge. Sometimes CMocka is not required and even makes things problematic. Thanks to this patch one can set -no_test_framework parameter to instruct framework not to include and link selected test against CMocka library. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I01dc7c6c50e6ae2f7f71bd6752c2d5f2cc7c3cdc --- M tests/Makefile.common 1 file changed, 24 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/70107/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01dc7c6c50e6ae2f7f71bd6752c2d5f2cc7c3cdc Gerrit-Change-Number: 70107 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: util/cbmem: Provide a way to override coreboot path
by Martin L Roth (Code Review) 29 Nov '22

29 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69686 ) Change subject: util/cbmem: Provide a way to override coreboot path ...................................................................... util/cbmem: Provide a way to override coreboot path Right now cbmem uses a fix path to reach coreboot src path (../../). This makes it impossible to compile cbmem out of the coreboot tree (e.g. copy just the cbmem directory elsewhere and compile). This patch adapts the technique from cbfstool and adds a variable called 'TOP' which points to coreboot root directory and which can be overridden at build time by providing it to make as an argument. This will enable a stand-alone build of cbmem. Change-Id: I2732f75310e10716e5aa74e094e0bf628ad22f0b Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69686 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M util/cbmem/Makefile 1 file changed, 24 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile index a170875..9219a08 100644 --- a/util/cbmem/Makefile +++ b/util/cbmem/Makefile @@ -2,7 +2,8 @@ ## SPDX-License-Identifier: GPL-2.0-only PROGRAM = cbmem -ROOT = ../../src +TOP ?= $(abspath ../..) +ROOT = $(TOP)/src CC ?= $(CROSS_COMPILE)gcc INSTALL ?= /usr/bin/env install PREFIX ?= /usr/local -- To view, visit https://review.coreboot.org/c/coreboot/+/69686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2732f75310e10716e5aa74e094e0bf628ad22f0b Gerrit-Change-Number: 69686 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: mb/system76/tgl-h: Convert oryp8 to a variant
by Tim Crawford (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Jeremy Soller. Hello build bot (Jenkins), Jeremy Soller, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67991 to look at the new patch set (#4). Change subject: mb/system76/tgl-h: Convert oryp8 to a variant ...................................................................... mb/system76/tgl-h: Convert oryp8 to a variant Change-Id: Ied55add6d7549f165d8b97032d7f21ede0ce2dde Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- D src/mainboard/system76/oryp8/Kconfig D src/mainboard/system76/oryp8/Kconfig.name D src/mainboard/system76/oryp8/Makefile.inc D src/mainboard/system76/oryp8/acpi/mainboard.asl D src/mainboard/system76/oryp8/acpi/sleep.asl D src/mainboard/system76/oryp8/board_info.txt D src/mainboard/system76/oryp8/bootblock.c D src/mainboard/system76/oryp8/cmos.default D src/mainboard/system76/oryp8/cmos.layout D src/mainboard/system76/oryp8/devicetree.cb D src/mainboard/system76/oryp8/dsdt.asl D src/mainboard/system76/oryp8/include/mainboard/gpio.h D src/mainboard/system76/oryp8/romstage.c M src/mainboard/system76/tgl-h/Kconfig M src/mainboard/system76/tgl-h/Kconfig.name M src/mainboard/system76/tgl-h/Makefile.inc M src/mainboard/system76/tgl-h/devicetree.cb M src/mainboard/system76/tgl-h/dsdt.asl M src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb M src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb A src/mainboard/system76/tgl-h/variants/oryp8/board_info.txt R src/mainboard/system76/tgl-h/variants/oryp8/data.vbt R src/mainboard/system76/tgl-h/variants/oryp8/gpio.c R src/mainboard/system76/tgl-h/variants/oryp8/gpio_early.c R src/mainboard/system76/tgl-h/variants/oryp8/hda_verb.c A src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb R src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c A src/mainboard/system76/tgl-h/variants/oryp8/romstage.c R src/mainboard/system76/tgl-h/variants/oryp8/tas5825m.c 29 files changed, 156 insertions(+), 506 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/67991/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/67991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied55add6d7549f165d8b97032d7f21ede0ce2dde Gerrit-Change-Number: 67991 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/system76: Rename gaze16 to tgl-h
by Tim Crawford (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Jeremy Soller. Hello build bot (Jenkins), Jeremy Soller, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67990 to look at the new patch set (#3). Change subject: mb/system76: Rename gaze16 to tgl-h ...................................................................... mb/system76: Rename gaze16 to tgl-h Change-Id: Icbf9348447b9e7acc0caa8082cf5dd00853da37a Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- R src/mainboard/system76/tgl-h/Kconfig R src/mainboard/system76/tgl-h/Kconfig.name R src/mainboard/system76/tgl-h/Makefile.inc R src/mainboard/system76/tgl-h/acpi/mainboard.asl R src/mainboard/system76/tgl-h/acpi/sleep.asl R src/mainboard/system76/tgl-h/board_info.txt R src/mainboard/system76/tgl-h/bootblock.c R src/mainboard/system76/tgl-h/cmos.default R src/mainboard/system76/tgl-h/cmos.layout R src/mainboard/system76/tgl-h/devicetree.cb R src/mainboard/system76/tgl-h/dsdt.asl R src/mainboard/system76/tgl-h/include/variant/gpio.h R src/mainboard/system76/tgl-h/include/variant/romstage.h R src/mainboard/system76/tgl-h/ramstage.c R src/mainboard/system76/tgl-h/romstage.c A src/mainboard/system76/tgl-h/variants/gaze16-3050/board_info.txt R src/mainboard/system76/tgl-h/variants/gaze16-3050/data.vbt R src/mainboard/system76/tgl-h/variants/gaze16-3050/gpio.c R src/mainboard/system76/tgl-h/variants/gaze16-3050/gpio_early.c R src/mainboard/system76/tgl-h/variants/gaze16-3050/hda_verb.c R src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb R src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c R src/mainboard/system76/tgl-h/variants/gaze16-3050/romstage.c A src/mainboard/system76/tgl-h/variants/gaze16-3060/board_info.txt R src/mainboard/system76/tgl-h/variants/gaze16-3060/data.vbt R src/mainboard/system76/tgl-h/variants/gaze16-3060/gpio.c R src/mainboard/system76/tgl-h/variants/gaze16-3060/gpio_early.c R src/mainboard/system76/tgl-h/variants/gaze16-3060/hda_verb.c R src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb R src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c R src/mainboard/system76/tgl-h/variants/gaze16-3060/romstage.c 31 files changed, 15 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/67990/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/67990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbf9348447b9e7acc0caa8082cf5dd00853da37a Gerrit-Change-Number: 67990 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: [WIP][DO NOT MERGE] ssdtgen: ACPI SSDT generator
by build bot (Jenkins) (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Martin L Roth. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70110 ) Change subject: [WIP][DO NOT MERGE] ssdtgen: ACPI SSDT generator ...................................................................... Patch Set 1: (3 comments) File ssdtgen/Makefile.inc: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164784): https://review.coreboot.org/c/coreboot/+/70110/comment/19879514_7d56b596 PS1, Line 26: # User should provide path to devicetree and optionaly to chipset and override devicetree 'optionaly' may be misspelled - perhaps 'optionally'? File ssdtgen/ssdtgen_main.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164784): https://review.coreboot.org/c/coreboot/+/70110/comment/88284a2f_f4d59dd0 PS1, Line 61: if (dev && dev->chip_ops && dev->chip_ops->enable_dev) { braces {} are not necessary for single statement blocks File ssdtgen/ssdtgen_sys.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164784): https://review.coreboot.org/c/coreboot/+/70110/comment/39217b9c_6c5731f2 PS1, Line 51: trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/70110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78766cd1f47e24b2cd7f9b5cf1cca066441ead06 Gerrit-Change-Number: 70110 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Tue, 29 Nov 2022 15:11:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: tests/Makefile.common: Allow to override tests defconfig
by build bot (Jenkins) (Code Review) 29 Nov '22

29 Nov '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70109 ) Change subject: tests/Makefile.common: Allow to override tests defconfig ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164783): https://review.coreboot.org/c/coreboot/+/70109/comment/a607a6c4_6c3ef941 PS1, Line 8: Possible repeated word: 'might' -- To view, visit https://review.coreboot.org/c/coreboot/+/70109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If53b9a54ef7389dd979dfe772e6946439f7d6a62 Gerrit-Change-Number: 70109 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Nov 2022 15:10:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: tests/Makefile.common: Allow to disable test framework with parameter
by build bot (Jenkins) (Code Review) 29 Nov '22

29 Nov '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70107 ) Change subject: tests/Makefile.common: Allow to disable test framework with parameter ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164781): https://review.coreboot.org/c/coreboot/+/70107/comment/ed4cef7d_751f3399 PS1, Line 12: can set -no_test_framework parameter to instruct framework not to include Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/70107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01dc7c6c50e6ae2f7f71bd6752c2d5f2cc7c3cdc Gerrit-Change-Number: 70107 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Nov 2022 15:10:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: [WIP][DO NOT MERGE] ssdtgen: ACPI SSDT generator
by Jakub Czapiga (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Martin L Roth. Jakub Czapiga has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70110 ) Change subject: [WIP][DO NOT MERGE] ssdtgen: ACPI SSDT generator ...................................................................... [WIP][DO NOT MERGE] ssdtgen: ACPI SSDT generator Work in progress. TODO: - Documentation - Better help - Dynamic/config-based mocks - Modular devicetree (multi-override in sconfig?) - Cleanup Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I78766cd1f47e24b2cd7f9b5cf1cca066441ead06 --- M Makefile A ssdtgen/Makefile.inc A ssdtgen/devicetree.cb A ssdtgen/fw_config.c A ssdtgen/mock/fsp/util.h A ssdtgen/mock/gpio.c A ssdtgen/mock/soc/gpio.h A ssdtgen/mock/soc/nvs.h A ssdtgen/ssdtgen.h A ssdtgen/ssdtgen_main.c A ssdtgen/ssdtgen_sys.c 11 files changed, 442 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/70110/1 diff --git a/Makefile b/Makefile index 58cd85b..a83d273 100644 --- a/Makefile +++ b/Makefile @@ -115,20 +115,29 @@ ifneq ($(filter %clean lint% help% what-jenkins-does,$(MAKECMDGOALS)),) NOMKDIR:=1 UNIT_TEST:=1 +SSDTGEN:=1 endif endif -ifneq ($(filter help%, $(MAKECMDGOALS)), ) +ifneq ($(filter help%,$(MAKECMDGOALS)),) NOCOMPILE:=1 UNIT_TEST:=1 +SSDTGEN:=1 else -ifneq ($(filter %-test %-tests %coverage-report, $(MAKECMDGOALS)),) -ifneq ($(filter-out %-test %-tests %coverage-report, $(MAKECMDGOALS)),) +ifneq ($(filter %-test %-tests %coverage-report,$(MAKECMDGOALS)),) +ifneq ($(filter-out %-test %-tests %coverage-report,$(MAKECMDGOALS)),) $(error Cannot mix unit-tests targets with other targets) endif UNIT_TEST:=1 NOCOMPILE:= endif +ifneq ($(filter %ssdtgen,$(MAKECMDGOALS)),) +ifneq ($(filter-out %ssdtgen,$(MAKECMDGOALS)),) +$(error Cannot mix ssdtgen targets with other targets) +endif +SSDTGEN:=1 +NOCOMPILE:= +endif endif $(xcompile): util/xcompile/xcompile @@ -148,6 +157,7 @@ include $(TOPLEVEL)/util/testing/Makefile.inc -include $(TOPLEVEL)/site-local/Makefile.inc include $(TOPLEVEL)/tests/Makefile.inc +include $(TOPLEVEL)/ssdtgen/Makefile.inc real-all: @echo "Error: Trying to build, but NOCOMPILE is set." >&2 @echo " Please file a bug with the following information:" @@ -158,8 +168,10 @@ else ifneq ($(UNIT_TEST),1) +ifneq ($(SSDTGEN),1) include $(DOTCONFIG) endif +endif # The toolchain requires xcompile to determine the ARCH_SUPPORTED, so we can't # wait for make to generate the file. @@ -191,8 +203,10 @@ endif ifneq ($(UNIT_TEST),1) +ifneq ($(SSDTGEN),1) include toolchain.inc endif +endif strip_quotes = $(strip $(subst ",,$(subst \",,$(1)))) # fix makefile syntax highlighting after strip macro \" ")) @@ -294,10 +308,14 @@ subdirs:=$(TOPLEVEL) postinclude-hooks := -# Don't iterate through Makefile.incs under src/ when building tests +# Don't iterate through Makefile.incs under src/ when building tests or ssdtgen ifneq ($(UNIT_TEST),1) +ifneq ($(SSDTGEN),1) $(eval $(call evaluate_subdirs)) else +include $(TOPLEVEL)/ssdtgen/Makefile.inc +endif +else include $(TOPLEVEL)/tests/Makefile.inc endif diff --git a/ssdtgen/Makefile.inc b/ssdtgen/Makefile.inc new file mode 100644 index 0000000..601497f --- /dev/null +++ b/ssdtgen/Makefile.inc @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# Import SCONFIG utility required by this file +subdirs := $(top)/util/sconfig +$(call evaluate_subdirs) + +testobj := $(obj)/ssdtgen +ssdtgenobj := $(testobj)/ssdtgen + +ifeq ($(SSDT_CONFIG),) +$(error SSDT_CONFIG= not provided) +endif +TEST_DEFAULT_CONFIG := $(SSDT_CONFIG) +include $(TEST_DEFAULT_CONFIG) + +# Build info file. To satisfy sources +build_h := $(ssdtgenobj)/build.h + +$(build_h): $$(shell $$(build_h_check)) + @printf " GEN build.h\n" + mkdir -p $(dir $@) + $(top)/util/genbuild_h/genbuild_h.sh /dev/null >$@ 2>/dev/null; + + +# Devicetree configuration +# User should provide path to devicetree and optionaly to chipset and override devicetree +# in DEVICETREE, CHIPSET_DEVICETREE and OVERRIDE_DEVICETREE +ifeq ($(DEVICETREE),) +$(error DEVICETREE= unset, but required) +endif +SCONFIG_OPTIONS := --mainboard_devtree=$(DEVICETREE) + +ifneq ($(OVERRIDE_DEVICETREE),) +SCONFIG_OPTIONS += --override_devtree=$(OVERRIDE_DEVICETREE) +endif + +ifneq ($(CHIPSET_DEVICETREE),) +SCONFIG_OPTIONS += --chipset_devtree=$(CHIPSET_DEVICETREE) +endif + +DEVICETREE_STATIC_C := $(ssdtgenobj)/static.c +SCONFIG_OPTIONS += --output_c=$(DEVICETREE_STATIC_C) + +DEVICETREE_STATIC_H := $(ssdtgenobj)/static.h +SCONFIG_OPTIONS += --output_h=$(DEVICETREE_STATIC_H) + +DEVICETREE_DEVICENAMES_H := $(ssdtgenobj)/static_devices.h +SCONFIG_OPTIONS += --output_d=$(DEVICETREE_DEVICENAMES_H) + +DEVICETREE_FWCONFIG_H := $(ssdtgenobj)/static_fw_config.h +SCONFIG_OPTIONS += --output_f=$(DEVICETREE_FWCONFIG_H) + +$(DEVICETREE_STATIC_C): $(DEVICETREE) $(OVERRIDE_DEVICETREE) $(CHIPSET_DEVICETREE) $(objutil)/sconfig/sconfig $(build_h) + @printf " SCONFIG $(subst $(src)/,,$(<))\n" + mkdir -p $(dir $(DEVICETREE_STATIC_C)) + $(objutil)/sconfig/sconfig $(SCONFIG_OPTIONS) + +# Get all chips to load appropriate files +chips := $(shell cat $(DEVICETREE) $(OVERRIDE_DEVICETREE) $(CHIPSET_DEVICETREE) \ + | perl -lne '/^\s*chip\s+((\w+\/?)+)\s*$$/ && print $1' | sort | uniq) + + +# Get ramstage sources +$(call add-class,ramstage) + +subdirs-y := src/lib src/device src/acpi +subdirs-y += $(addprefix src/,$(chips)) +subdirs-$(CONFIG_HAVE_SMI_HANDLER) += src/cpu/x86/smm + +subdirs := $(addprefix $(top)/,$(subdirs-y)) +$(call evaluate_subdirs) + +# Use testing framework +include $(top)/tests/Makefile.common + + +# Test framework is not needed +ssdtgen-no_test_framework := yes + +# ACPI tables are generated in ramstage +ssdtgen-stage := ramstage + +# Main generator code +ssdtgen-srcs += ssdtgen/ssdtgen_main.c +ssdtgen-syssrcs += ssdtgen/ssdtgen_sys.c + +# Mocks +ssdtgen-srcs += ssdtgen/fw_config.c + +# SoC ACPI GPIO +ssdtgen-srcs += $(if $(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI), src/soc/intel/common/block/acpi/gpio.c) +ssdtgen-srcs += $(if $(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_GPIO), src/soc/amd/common/block/acpi/gpio.c) + +# Include configurad sources, exclude conflicting files +files-to-exclude := src/lib/hardwaremain.c \ + src/lib/fmap.c \ + src/lib/malloc.c + +ssdtgen-srcs += $(filter-out $(files-to-exclude), \ + $(filter %.c,$(ramstage-srcs))) + +ssdtgen-mocks += fw_config_get fw_config_probe +ssdtgen-cflags += -Issdtgen/mock +ssdtgen-srcs += ssdtgen/mock/gpio.c + +# Provide include path to generated devicetree files +ssdtgen-cflags += -I$(ssdtgenobj) + +ssdtgen-cflags += -Os + +# Generated source file lives in build directory, +# so object file has to match pattern and thus has double nested object path +ssdtgen-objs += $(ssdtgenobj)/$(ssdtgenobj)/static.o + +ssdtgen-srcobjs += $(addprefix $(ssdtgenobj)/, \ + $(patsubst %.c,%.o,$(filter src/%,$(ssdtgen-srcs)))) +ssdtgen-objs += $(addprefix $(ssdtgenobj)/, \ + $(patsubst %.c,%.o,$(ssdtgen-srcs))) +ssdtgen-syslibcobjs += $(addprefix $(ssdtgenobj)/, \ + $(patsubst %.c,%.o,$(ssdtgen-syssrcs))) + +ssdtgen-bin := $(ssdtgenobj)/ssdtgenerator + +$(eval $(call TEST_CC_template,ssdtgen)) + +DEPENDENCIES += $(addsuffix .d,$(basename $(ssdtgen-objs) $(ssdtgen-syslibcobjs))) +-include $(DEPENDENCIES) + +.PHONY: ssdtgen clean-ssdtgen ssdtgen-help + +ssdtgen: $(ssdtgen-bin) + @mkdir -p $(testobj)/output/ + $(ssdtgen-bin) -o $(testobj)/output/ssdt.bin + @echo 'SSDT generated' + +clean-sstdgen: + rm -rf $(testobj) + +help-ssdtgen help:: + @echo '*** coreboot ACPI SSDT generator targets ***' + @echo ' ssdtgen - Build and run ACPI SSDT Generator' # TODO + @echo ' clean-ssdt - Remove all SSDT Generator artifacts' + @echo + diff --git a/ssdtgen/devicetree.cb b/ssdtgen/devicetree.cb new file mode 100644 index 0000000..8673761 --- /dev/null +++ b/ssdtgen/devicetree.cb @@ -0,0 +1,24 @@ + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(31)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""1234KZ"" + register "name" = ""KZM22"" + register "desc" = ""MyOwnDevice Co."" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(32)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""kzm, test dev"" + register "property_list[0].integer" = "1" + device i2c 1b on end + end diff --git a/ssdtgen/fw_config.c b/ssdtgen/fw_config.c new file mode 100644 index 0000000..ca6bd9c --- /dev/null +++ b/ssdtgen/fw_config.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <fw_config.h> + + +#if !defined(FW_CONFIG_VALUE) +# define FW_CONFIG_VALUE UNDEFINED_FW_CONFIG +#endif + +static uint64_t fw_config_value = FW_CONFIG_VALUE; + +uint64_t fw_config_get(void) +{ + return fw_config_value; +} + +#if CONFIG(FW_CONFIG) + +bool fw_config_probe(const struct fw_config *match) +{ + /* If fw_config is not provisioned, then there is nothing to match. */ + if (!fw_config_is_provisioned()) + return false; + + /* Compare to system value. */ + return (fw_config_get() & match->mask) == match->value; +} + +#endif diff --git a/ssdtgen/mock/fsp/util.h b/ssdtgen/mock/fsp/util.h new file mode 100644 index 0000000..92d6d69 --- /dev/null +++ b/ssdtgen/mock/fsp/util.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SSDTGEN_MOCK_FSP_UTIL_H_ +#define SSDTGEN_MOCK_FSP_UTIL_H_ + +static inline void lb_string_platform_blob_version(struct lb_header *header) +{ + +} + +#endif /* SSDTGEN_MOCK_FSP_UTIL_H_ */ diff --git a/ssdtgen/mock/gpio.c b/ssdtgen/mock/gpio.c new file mode 100644 index 0000000..30c6226 --- /dev/null +++ b/ssdtgen/mock/gpio.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> + +int gpio_get(gpio_t gpio) +{ + return 0; +} diff --git a/ssdtgen/mock/soc/gpio.h b/ssdtgen/mock/soc/gpio.h new file mode 100644 index 0000000..6a53afe --- /dev/null +++ b/ssdtgen/mock/soc/gpio.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SSDTGEN_MOCK_SOC_GPIO_H_ +#define SSDTGEN_MOCK_SOC_GPIO_H_ + +#include <inttypes.h> + +typedef uint32_t gpio_t; + +#endif /* SSDTGEN_MOCK_SOC_GPIO_H_ */ diff --git a/ssdtgen/mock/soc/nvs.h b/ssdtgen/mock/soc/nvs.h new file mode 100644 index 0000000..b6fdfdc --- /dev/null +++ b/ssdtgen/mock/soc/nvs.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SSDTGEN_MOCK_SOC_NVS_H +#define SSDTGEN_MOCK_SOC_NVS_H + +#include <stdint.h> + +struct __packed global_nvs { + /* Miscellaneous */ + u16 unused_was_osys; /* 0x00 - 0x01 Operating System */ + u8 smif; /* 0x02 - SMI function call ("TRAP") */ + u8 unused_was_pcnt; /* 0x03 - Processor Count */ + u8 ppcm; /* 0x04 - Max PPC State */ + u8 tlvl; /* 0x05 - Throttle Level Limit */ + u8 lids; /* 0x06 - LID State */ + u8 unused_was_pwrs; /* 0x07 - AC Power State */ + u32 cbmc; /* 0x08 - 0xb coreboot Memory Console */ + u64 pm1i; /* 0x0c - 0x13 PM1 wake status bit */ + u64 gpei; /* 0x14 - 0x1b GPE wake status bit */ + u8 dpte; /* 0x1c - Enable DPTF */ + u64 nhla; /* 0x1d - 0x24 NHLT Address */ + u32 nhll; /* 0x25 - 0x28 NHLT Length */ + u16 unused_was_cid1; /* 0x29 - 0x2a Wifi Country Identifier */ + u16 u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */ + u16 u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */ + u8 uior; /* 0x2f - UART debug controller init on S3 resume */ + u64 hest_log_addr; /* 0x30 - 0x37 err log addr (used in SMM, not ASL code) */ +}; + +#endif diff --git a/ssdtgen/ssdtgen.h b/ssdtgen/ssdtgen.h new file mode 100644 index 0000000..507ab3b --- /dev/null +++ b/ssdtgen/ssdtgen.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <inttypes.h> + +int ssdtgen_parse_args(int argc, char **argv); + +int ssdtgen_save(uint8_t *buf, size_t size); diff --git a/ssdtgen/ssdtgen_main.c b/ssdtgen/ssdtgen_main.c new file mode 100644 index 0000000..91174eb --- /dev/null +++ b/ssdtgen/ssdtgen_main.c @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <console/console.h> +#include <device/device.h> +#include <timer.h> + +#include "ssdtgen.h" + + +/* Temporary mocks TODO: Move to appropriate files */ + +int printk(int msg_level, const char *fmt, ...) +{ + return 0; +} + +int vprintk(int msg_level, const char *fmt, va_list args) +{ + return 0; +} + +void mock_assert(const int result, const char *expression, const char *const file, + const int line) +{ +} + +void smm_region(uintptr_t *start, size_t *size) +{ + *size = 0; + *start = 0; +} + +void do_board_reset(void) +{ + // TODO: Might need implementation +} + +void cmos_post_path(const struct device *dev) +{ + +} + +void timer_monotonic_get(struct mono_time *mt) +{ + mt->microseconds = 0; +} + +/* End of temporary mocks */ + +/* Pre-allocated buffer for generated AML */ +static uint8_t acpigen_data_buf[16 * MiB]; + +int main(int argc, char **argv) +{ + all_devices = &dev_root; + + /* Enable all devices */ + struct device *dev; + for (dev = all_devices; dev; dev = dev->next) { + if (dev && dev->chip_ops && dev->chip_ops->enable_dev) { + dev->chip_ops->enable_dev(dev); + } + } + + const int result = ssdtgen_parse_args(argc, argv); + if (result) + return result; + + acpi_header_t *ssdt_table = (acpi_header_t *)&acpigen_data_buf; + acpi_create_ssdt_generator(ssdt_table, ACPI_TABLE_CREATOR); + + return ssdtgen_save(acpigen_data_buf, ssdt_table->length); +} diff --git a/ssdtgen/ssdtgen_sys.c b/ssdtgen/ssdtgen_sys.c new file mode 100644 index 0000000..493921b --- /dev/null +++ b/ssdtgen/ssdtgen_sys.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <errno.h> +#include <inttypes.h> +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> + + +char *output_file = NULL; + +static void print_usage(const char *name, int exit_code) +{ + printf("usage: %s [OPTIONS]\n", name); + printf("Options:\n" + " -o <path> SSDT table output file path\n" + " -h print this help\n" + "\n"); + exit(exit_code); +} + +int ssdtgen_parse_args(int argc, char **argv) +{ + int c = 0; + opterr = 0; + + while ((c = getopt(argc, argv, "ho:")) != -1) { + switch (c) { + case 'o': + output_file = optarg; + break; + case 'h': + print_usage(argv[0], 0); + break; + case '?': + default: + print_usage(argv[0], 1); + break; + } + } + + if (!output_file) + print_usage(argv[0], 1); + + return 0; +} + +int ssdtgen_save(uint8_t *buf, size_t size) +{ + FILE *f = fopen(output_file, "wb"); + + if (!f) { + perror("Failed to open output file"); + return 1; + } + + if (fwrite(buf, sizeof(uint8_t), size, f) != size) { + perror("Failed to write full contents to file"); + return 1; + } + + fclose(f); + return 0; +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/70110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78766cd1f47e24b2cd7f9b5cf1cca066441ead06 Gerrit-Change-Number: 70110 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: tests/Makefile.common: Allow to override tests defconfig
by Jakub Czapiga (Code Review) 29 Nov '22

29 Nov '22

Jakub Czapiga has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70109 ) Change subject: tests/Makefile.common: Allow to override tests defconfig ...................................................................... tests/Makefile.common: Allow to override tests defconfig Some tools based on test framework might might require defconfig other than tests default one. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: If53b9a54ef7389dd979dfe772e6946439f7d6a62 --- M tests/Makefile.common 1 file changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/70109/1 diff --git a/tests/Makefile.common b/tests/Makefile.common index 8a4bc9a..cda7bf5 100644 --- a/tests/Makefile.common +++ b/tests/Makefile.common @@ -18,7 +18,7 @@ OBJCOPY ?= objcopy OBJDUMP ?= objdump -TEST_DEFAULT_CONFIG := $(top)/configs/config.emulation_qemu_x86_i440fx +TEST_DEFAULT_CONFIG ?= $(top)/configs/config.emulation_qemu_x86_i440fx TEST_DOTCONFIG := $(testobj)/.config TEST_KCONFIG_AUTOHEADER := $(testobj)/config.src.h TEST_KCONFIG_AUTOCONFIG := $(testobj)/auto.conf -- To view, visit https://review.coreboot.org/c/coreboot/+/70109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If53b9a54ef7389dd979dfe772e6946439f7d6a62 Gerrit-Change-Number: 70109 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: tests: Support linking with system libc
by Jakub Czapiga (Code Review) 29 Nov '22

29 Nov '22

Jakub Czapiga has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70108 ) Change subject: tests: Support linking with system libc ...................................................................... tests: Support linking with system libc This patch allows for linking selected files with system libc. This allows for creating libraries interacting with filesystem, standard I/O and other parts of system. Until now it was only possible using CMocka proxy functions or functions not masked by code under test. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I652362ba61a25e974d706357fc36479ccee763e4 --- M tests/Makefile.common M tests/Makefile.inc 2 files changed, 48 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/70108/1 diff --git a/tests/Makefile.common b/tests/Makefile.common index fe46aeb..8a4bc9a 100644 --- a/tests/Makefile.common +++ b/tests/Makefile.common @@ -27,17 +27,20 @@ TEST_KCONFIG_TRISTATE := $(testobj)/tristate.conf # Include order should be same as in real build -TEST_CFLAGS := -include $(src)/include/kconfig.h \ +TEST_INCLUDES := -include $(src)/include/kconfig.h \ -include $(src)/include/rules.h \ -include $(src)/commonlib/bsd/include/commonlib/bsd/compiler.h # Include generic test mock headers, before original ones -TEST_CFLAGS += -I$(testsrc)/include/mocks -I$(testsrc)/include +TEST_INCLUDES += -I$(testsrc)/include/mocks -I$(testsrc)/include -TEST_CFLAGS += -I$(src) -I$(src)/include -I$(src)/commonlib/include \ +TEST_INCLUDES += -I$(src) -I$(src)/include -I$(src)/commonlib/include \ -I$(src)/commonlib/bsd/include -I$(src)/arch/x86/include \ -I$(top)/3rdparty/vboot/firmware/include +# Path for Kconfig autoheader +TEST_INCLUDES += -I$(dir $(TEST_KCONFIG_AUTOHEADER)) + # Note: This is intentionally just a subset of the warnings in the toplevel # Makefile.inc. We don't need to be as strict with test code, and things like # -Wmissing-prototypes just make working with the test framework cumbersome. @@ -48,9 +51,6 @@ TEST_CFLAGS += -Wno-array-compare -Wno-packed-not-aligned -Wno-trigraphs TEST_CFLAGS += -Wno-unused-but-set-variables -# Path for Kconfig autoheader -TEST_CFLAGS += -I$(dir $(TEST_KCONFIG_AUTOHEADER)) - TEST_CFLAGS += -std=gnu11 -Os -ffunction-sections -fdata-sections -fno-builtin TEST_CFLAGS += -D__TEST__ @@ -66,7 +66,14 @@ TEST_LDFLAGS += -no-pie # Extra attributes for unit tests, declared per test -attributes := srcs cflags config mocks no_test_framework stage +# srcs - sources linked with coreboot libc symbols +# syssrcs - sources linked with system libc, no coreboot includes +# cflags - attribute with additional CFLAGS +# config - Kconfig and defines override (`gcc -D` style) +# mocks - list of symbols to mock +# no_test_framework - set to `1` not to link test framework +# stage - name of stage e.g. romstage, bootblock, etc. (default: ramstage) +attributes := srcs cflags config-file config mocks no_test_framework stage # Copy attributes of one test to another. # $1 - input test name @@ -113,12 +120,15 @@ # Give us a way to distinguish between coreboot source files and test files in code. $($(1)-srcobjs): TEST_CFLAGS += -D__TEST_SRCOBJ__ +# Add coreboot, vboot, kconfig etc. includes only to non-system libc linked objects +$(filter-out $($(1)-syslibcobjs),$($(1)-objs)): TEST_CFLAGS += $(TEST_INCLUDES) + # Compile sources and apply mocking/wrapping of selected symbols. # For each listed mock add new symbol with prefix `__real_`, # and pointing to the same section:address. $($(1)-objs): $(testobj)/$(1)/%.o: $$$$*.c $$($(1)-config-file) mkdir -p $$(dir $$@) - $(HOSTCC) $(HOSTCFLAGS) $$(TEST_CFLAGS) $($(1)-cflags) -MMD \ + $(HOSTCC) $(HOSTCFLAGS) $$(TEST_CFLAGS) $$(TEST_INCLUDES) $($(1)-cflags) -MMD \ -MF $$(basename $$(a)).d -MT $$@ -c $$< -o $$@.orig objcopy_wrap_flags=''; \ for sym in $$($(1)-mocks); do \ @@ -132,13 +142,20 @@ done ; \ $(OBJCOPY) $$@.orig $$$$objcopy_wrap_flags $$@ -# Link against Cmocka if not disabled -$(addsuffix $$(filter-out n 0,$($(1)-no_test_framework)),$($(1)-objs)): TEST_CFLAGS += -I$(cmockasrc)/include -$($(1)-bin)$$(filter-out n 0,$($(1)-no_test_framework)): TEST_LDFLAGS += -L$(cmockaobj)/src -lcmocka -Wl,-rpath=$(cmockaobj)/src -$($(1)-bin)$$(filter-out n 0,$($(1)-no_test_framework)): TEST_CFLAGS += -I$(cmockasrc)/include -$($(1)-bin)$$(filter-out n 0,$($(1)-no_test_framework)): $(CMOCKA_LIB) +# Compile system-side sources linked with system libc, without mocking symbols +# or code-under-test includes. +$($(1)-syslibcobjs): $(testobj)/$(1)/%.o: $$$$*.c $$($(1)-config-file) + mkdir -p $$(dir $$@) + $(HOSTCC) $(HOSTCFLAGS) $$(TEST_CFLAGS) $($(1)-cflags) -MMD \ + -MF $$(basename $$(a)).d -MT $$@ -c $$< -o $$@ -$($(1)-bin): $($(1)-objs) +# Link against Cmocka if not disabled +$(addsuffix $(filter-out n 0,$($(1)-no_test_framework)),$($(1)-objs)): TEST_CFLAGS += -I$(cmockasrc)/include +$($(1)-bin)$(filter-out n 0,$($(1)-no_test_framework)): TEST_LDFLAGS += -L$(cmockaobj)/src -lcmocka -Wl,-rpath=$(cmockaobj)/src +$($(1)-bin)$(filter-out n 0,$($(1)-no_test_framework)): TEST_CFLAGS += -I$(cmockasrc)/include +$($(1)-bin)$(filter-out n 0,$($(1)-no_test_framework)): $(CMOCKA_LIB) + +$($(1)-bin): $($(1)-objs) $($(1)-syslibcobjs) $(HOSTCC) $$^ $($(1)-cflags) $$(TEST_LDFLAGS) -o $$@ endef diff --git a/tests/Makefile.inc b/tests/Makefile.inc index 90f01d1..04792c1 100644 --- a/tests/Makefile.inc +++ b/tests/Makefile.inc @@ -51,6 +51,8 @@ $(foreach test, $(alltests), \ $(eval $(test)-srcobjs := $(addprefix $(testobj)/$(test)/, \ $(patsubst %.c,%.o,$(filter src/%,$($(test)-srcs))))) \ + $(eval $(test)-syslibcobjs := $(addprefix $(testobj)/$(test)/, \ + $(patsubst %.c,%.o,$($(test)-syssrcs)))) \ $(eval $(test)-objs := $(addprefix $(testobj)/$(test)/, \ $(patsubst %.c,%.o,$($(test)-srcs))))) $(foreach test, $(alltests), \ -- To view, visit https://review.coreboot.org/c/coreboot/+/70108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I652362ba61a25e974d706357fc36479ccee763e4 Gerrit-Change-Number: 70108 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2022