Attention is currently required from: Martin L Roth, Caveh Jalali, Paul Menzel, Julius Werner, Boris Mittelberg.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69742 )
Change subject: ec/google/chromeec: Add packed attribute to structs in union
......................................................................
Patch Set 7:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69742/comment/545415e1_a38ebb7c
PS6, Line 7: Fix clang warnings
> Maybe: […]
Done
https://review.coreboot.org/c/coreboot/+/69742/comment/a2aeb37e_63611b90
PS6, Line 15: BUILD_TIMELESSS
> TIMELESS
Done
--
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Gerrit-Change-Number: 69742
Gerrit-PatchSet: 7
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com>
Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org>
Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr>
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Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69509 )
(
4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: Revert "src/arch/x86: Use core apic id to get cpu_index()"
......................................................................
Revert "src/arch/x86: Use core apic id to get cpu_index()"
This reverts commit 095c931cf12924da9011b47aa64f4a6f11d89f13.
Previously cpu_info() was implemented with a struct on top of an
aligned stack. As FSP changed the stack value cpu_info() could not be
used in FSP context (which PPI is). Now cpu_info() uses GDT segments,
which FSP does not touch so it can be used.
This also exports cpu_infos from cpu.c as it's a convenient way to get
the struct device * for a certain index.
TESTED on aldrvp: FSP-S works and is able to run code on APs.
Change-Id: I3a40156ba275b572d7d1913d8c17c24b4c8f6d78
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69509
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/arch/x86/cpu.c
M src/arch/x86/include/arch/cpu.h
M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
M src/soc/intel/xeon_sp/cpx/cpu.c
M src/soc/intel/xeon_sp/skx/cpu.c
5 files changed, 45 insertions(+), 50 deletions(-)
Approvals:
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c
index 9fc5233..face248 100644
--- a/src/arch/x86/cpu.c
+++ b/src/arch/x86/cpu.c
@@ -318,33 +318,9 @@
mp_park_aps();
}
-/*
- * Previously cpu_index() implementation assumes that cpu_index()
- * function will always getting called from coreboot context
- * (ESP stack pointer will always refer to coreboot).
- *
- * But with MP_SERVICES_PPI implementation in coreboot this
- * assumption might not be true, where FSP context (stack pointer refers
- * to FSP) will request to get cpu_index().
- *
- * Hence new logic to use cpuid to fetch lapic id and matches with
- * cpus_default_apic_id[] variable to return correct cpu_index().
- */
-int cpu_index(void)
-{
- int i;
- int lapic_id = initial_lapicid();
-
- for (i = 0; i < CONFIG_MAX_CPUS; i++) {
- if (cpu_get_apic_id(i) == lapic_id)
- return i;
- }
- return -1;
-}
-
/* cpu_info() looks at address 0 at the base of %gs for a pointer to struct cpu_info */
static struct per_cpu_segment_data segment_data[CONFIG_MAX_CPUS];
-static struct cpu_info cpu_infos[CONFIG_MAX_CPUS];
+struct cpu_info cpu_infos[CONFIG_MAX_CPUS];
enum cb_err set_cpu_info(unsigned int index, struct device *cpu)
{
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index c7c6b4e..18bc961 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -161,6 +161,13 @@
return ci;
}
+static inline unsigned long cpu_index(void)
+{
+ struct cpu_info *ci;
+ ci = cpu_info();
+ return ci->index;
+}
+
struct cpuinfo_x86 {
uint8_t x86; /* CPU family */
uint8_t x86_vendor; /* CPU vendor */
@@ -212,20 +219,6 @@
*/
uint32_t cpu_get_feature_flags_edx(void);
-/*
- * Previously cpu_index() implementation assumes that cpu_index()
- * function will always getting called from coreboot context
- * (ESP stack pointer will always refer to coreboot).
- *
- * But with MP_SERVICES_PPI implementation in coreboot this
- * assumption might not be true, where FSP context (stack pointer refers
- * to FSP) will request to get cpu_index().
- *
- * Hence new logic to use cpuid to fetch lapic id and matches with
- * cpus_default_apic_id[] variable to return correct cpu_index().
- */
-int cpu_index(void);
-
#define DETERMINISTIC_CACHE_PARAMETERS_CPUID_IA 0x04
#define DETERMINISTIC_CACHE_PARAMETERS_CPUID_AMD 0x8000001d
diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
index 66bbc2f..d286ee3 100644
--- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
+++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
@@ -31,16 +31,17 @@
int apicid;
uint8_t package, core, thread;
- if (cpu_index() < 0)
+ if (processor_number >= MIN(get_cpu_count(), CONFIG_MAX_CPUS))
+ return FSP_NOT_FOUND;
+
+ extern struct cpu_info cpu_infos[];
+ struct cpu_info *info = &cpu_infos[processor_number];
+ if (!info)
return FSP_DEVICE_ERROR;
if (processor_info_buffer == NULL)
return FSP_INVALID_PARAMETER;
-
- if (processor_number >= get_cpu_count())
- return FSP_NOT_FOUND;
-
- apicid = cpu_get_apic_id(processor_number);
+ apicid = info->cpu->path.apic.apic_id;
if (apicid < 0)
return FSP_DEVICE_ERROR;
@@ -66,7 +67,7 @@
efi_return_status_t mp_startup_all_aps(efi_ap_procedure procedure,
bool run_serial, efi_uintn_t timeout_usec, void *argument)
{
- if (cpu_index() < 0)
+ if (!cpu_info())
return FSP_DEVICE_ERROR;
if (procedure == NULL)
@@ -84,7 +85,7 @@
efi_return_status_t mp_startup_all_cpus(efi_ap_procedure procedure,
efi_uintn_t timeout_usec, void *argument)
{
- if (cpu_index() < 0)
+ if (!cpu_info())
return FSP_DEVICE_ERROR;
if (procedure == NULL)
@@ -119,7 +120,7 @@
efi_return_status_t mp_startup_this_ap(efi_ap_procedure procedure,
efi_uintn_t processor_number, efi_uintn_t timeout_usec, void *argument)
{
- if (cpu_index() < 0)
+ if (!cpu_info())
return FSP_DEVICE_ERROR;
if (processor_number > get_cpu_count())
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c
index 4ecfad0..8a7dd2a 100644
--- a/src/soc/intel/xeon_sp/cpx/cpu.c
+++ b/src/soc/intel/xeon_sp/cpx/cpu.c
@@ -79,7 +79,7 @@
{
msr_t msr;
- printk(BIOS_SPEW, "%s dev: %s, cpu: %d, apic_id: 0x%x\n",
+ printk(BIOS_SPEW, "%s dev: %s, cpu: %lu, apic_id: 0x%x\n",
__func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id);
/*
diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c
index d2e4af1..24984e1 100644
--- a/src/soc/intel/xeon_sp/skx/cpu.c
+++ b/src/soc/intel/xeon_sp/skx/cpu.c
@@ -59,7 +59,7 @@
{
msr_t msr;
- printk(BIOS_INFO, "%s dev: %s, cpu: %d, apic_id: 0x%x\n",
+ printk(BIOS_INFO, "%s dev: %s, cpu: %lu, apic_id: 0x%x\n",
__func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id);
assert(chip_config);
--
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Gerrit-Change-Number: 69509
Gerrit-PatchSet: 6
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
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Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com>
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Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com>
Gerrit-MessageType: merged
Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69510 )
(
6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: soc/intel/alderlake/acpi.c: Don't look up coreboot CPU index
......................................................................
soc/intel/alderlake/acpi.c: Don't look up coreboot CPU index
The coreboot CPU index for a lapic is arbitrary: it depends on which
CPU obtains a spinlock first. Simply using an increasing index will
result in consistent ACPI tables across each boot.
Change-Id: Iaaaef213b32b33e3ec9f4874d576896c2335211c
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69510
Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/intel/alderlake/acpi.c
1 file changed, 21 insertions(+), 9 deletions(-)
Approvals:
build bot (Jenkins): Verified
Kyösti Mälkki: Looks good to me, approved
Werner Zeh: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c
index 1c820c2..c874067 100644
--- a/src/soc/intel/alderlake/acpi.c
+++ b/src/soc/intel/alderlake/acpi.c
@@ -279,6 +279,7 @@
acpigen_emit_byte(RETURN_OP);
acpigen_write_package(num_entries);
+ size_t cpu_index = 0;
for (dev = all_devices; dev; dev = dev->next) {
min_sleep_state = get_min_sleep_state(dev);
if (min_sleep_state == NONE)
@@ -294,15 +295,8 @@
break;
case DEVICE_PATH_APIC:
- /* Lookup CPU id */
- for (size_t i = 0; i < CONFIG_MAX_CPUS; i++) {
- if (cpu_get_apic_id(i) == dev->path.apic.apic_id) {
- snprintf(path, sizeof(path),
- CONFIG_ACPI_CPU_STRING, i);
- break;
- }
- }
-
+ snprintf(path, sizeof(path), CONFIG_ACPI_CPU_STRING,
+ cpu_index++);
acpigen_emit_namestring(path);
break;
--
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Gerrit-Change-Id: Iaaaef213b32b33e3ec9f4874d576896c2335211c
Gerrit-Change-Number: 69510
Gerrit-PatchSet: 8
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
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Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Gerrit-MessageType: merged
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70016 )
(
6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: drivers/net/r8168: Add support for ACPI DmaProperty
......................................................................
drivers/net/r8168: Add support for ACPI DmaProperty
BUG=b:259716145
TEST=Verified SSDT on google/osiris.
Before:
Scope (\_SB.PCI0.RP01)
{
Device (RLTK)
{
Name (_HID, "R8168") // _HID: Hardware ID
Name (_UID, 0xD0E889DD) // _UID: Unique ID
Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name
Name (_ADR, 0x00000000) // _ADR: Address
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x07,
0x03
})
}
}
After:
Scope (\_SB.PCI0.RP01)
{
Device (RLTK)
{
Name (_HID, "R8168") // _HID: Hardware ID
Name (_UID, 0xD0E889DD) // _UID: Unique ID
Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name
Name (_ADR, 0x00000000) // _ADR: Address
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x07,
0x03
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
Package (0x01)
{
Package (0x02)
{
"DmaProperty",
One
}
}
})
}
}
Signed-off-by: Kapil Porwal <kapilporwal(a)google.com>
Change-Id: I647230082362b1093b63793a201eba23a6289121
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70016
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/drivers/net/chip.h
M src/drivers/net/r8168.c
2 files changed, 69 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
diff --git a/src/drivers/net/chip.h b/src/drivers/net/chip.h
index f253cae..203707c 100644
--- a/src/drivers/net/chip.h
+++ b/src/drivers/net/chip.h
@@ -34,6 +34,10 @@
/* Allow kernel driver to enable ASPM L1.2. */
bool enable_aspm_l1_2;
+
+ /* When set to true, this will add a _DSD which contains a single
+ property, `DmaProperty`, set to 1, under the ACPI Device. */
+ bool add_acpi_dma_property;
};
#endif /* __DRIVERS_R8168_CHIP_H__ */
diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c
index 32e0275..5d19d69 100644
--- a/src/drivers/net/r8168.c
+++ b/src/drivers/net/r8168.c
@@ -400,6 +400,9 @@
if (config->wake)
acpigen_write_PRW(config->wake, 3);
+ if (config->add_acpi_dma_property)
+ acpi_device_add_dma_property(NULL);
+
acpigen_pop_len(); /* Device */
acpigen_pop_len(); /* Scope */
--
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Gerrit-Change-Number: 70016
Gerrit-PatchSet: 10
Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com>
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Gerrit-MessageType: merged
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70028 )
(
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: soc/intel/cmn/block/pcie/rtd3: Add support for ACPI DmaProperty
......................................................................
soc/intel/cmn/block/pcie/rtd3: Add support for ACPI DmaProperty
BUG=b:259716145
TEST=Verified SSDT on google/rex.
Signed-off-by: Kapil Porwal <kapilporwal(a)google.com>
Change-Id: I921b06e8d35ddac0bc8175b13a33c84515b282a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70028
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/intel/common/block/pcie/rtd3/chip.h
M src/soc/intel/common/block/pcie/rtd3/rtd3.c
2 files changed, 25 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
diff --git a/src/soc/intel/common/block/pcie/rtd3/chip.h b/src/soc/intel/common/block/pcie/rtd3/chip.h
index 8b62406..ff22adc 100644
--- a/src/soc/intel/common/block/pcie/rtd3/chip.h
+++ b/src/soc/intel/common/block/pcie/rtd3/chip.h
@@ -40,6 +40,10 @@
*/
int srcclk_pin;
+ /* When set to true, this will add a _DSD which contains a single
+ property, `DmaProperty`, set to 1, under the ACPI Device. */
+ bool add_acpi_dma_property;
+
/*
* Add device property indicating the device provides an external PCI port
* for the OS to apply security restrictions.
diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c
index 85ee24f..2c60eff 100644
--- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c
+++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c
@@ -484,6 +484,11 @@
acpi_dp_add_integer(pkg, PCIE_EXTERNAL_PORT_PROPERTY, 1);
acpi_dp_add_package(dsd, pkg);
}
+
+ /* Indicate to the OS if the device has DMA property. */
+ if (config->add_acpi_dma_property)
+ acpi_device_add_dma_property(dsd);
+
acpi_dp_write(dsd);
/*
--
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