coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

1 participants
7286 discussions

[M] Change in coreboot[master]: cpu/x86/smm: Add PCI BAR store functionality
by Martin Roth (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Arthur Heymans, Robert Zieba, Raul Rangel, Nico Huber, Angel Pons, Karthik Ramasubramanian, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67931 ) Change subject: cpu/x86/smm: Add PCI BAR store functionality ...................................................................... Patch Set 5: (4 comments) File src/cpu/x86/Kconfig: https://review.coreboot.org/c/coreboot/+/67931/comment/c27c5d1a_9b0ad586 PS5, Line 195: : config SMM_PCI_BAR_STORE : bool : depends on SMM_CHIPSET_STORE : help : This option enables support for storing PCI BARs in SMRAM so they : can't be tampered with. : : config SMM_PCI_BAR_STORE_NUM_SLOTS : int : default 8 : help : Number of slots available to store PCI BARs in SMRAM > I think the BAR store part of this is generic enough to leave in. […] Robert, that makes sense to me. I think that this is a useful feature for x86 in general just to verify that any BAR based address we're using hasn't changed. File src/cpu/x86/smm/pci_bar_store.c: https://review.coreboot.org/c/coreboot/+/67931/comment/6e28bd21_dc863c32 PS5, Line 7: smm_pci_query_stored_bar > I don't think we need anything this complicated. […] Raul, you're right that we don't in this case, but is there an argument against making it generic? https://review.coreboot.org/c/coreboot/+/67931/comment/df70ac61_67415c57 PS5, Line 30: pci_devfn_t pci_addr, > We are in ramstage and resource allocation has already been done. […] Definitely seems reasonable. https://review.coreboot.org/c/coreboot/+/67931/comment/3b0837f7_09aa33dd PS5, Line 58: smm_mainboard_pci_bar_store_init(&smm_runtime->chipset_store.pci_bar_store[0], : CONFIG_SMM_PCI_BAR_STORE_NUM_SLOTS); > Would the API make more sense the other way around. […] Also a good suggestion. -- To view, visit https://review.coreboot.org/c/coreboot/+/67931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23fb1e935dd1b89f1cc5c834cc2025f0fe5fda37 Gerrit-Change-Number: 67931 Gerrit-PatchSet: 5 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Nov 2022 17:25:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Robert Zieba <robertzieba(a)google.com> Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/intel/xeon_sp: Don't sort struct device cpus for numa
by Angel Pons (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Shuming Chu (Shuming), TangYiwei. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68912 ) Change subject: soc/intel/xeon_sp: Don't sort struct device cpus for numa ...................................................................... Patch Set 3: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68912/comment/dc0ed2e8_de1a685f PS3, Line 9: reassign reassign*s* https://review.coreboot.org/c/coreboot/+/68912/comment/ac74b3c2_926a7665 PS3, Line 12: break break*s* https://review.coreboot.org/c/coreboot/+/68912/comment/950c665e_1333c69e PS3, Line 15: This moves the sorting to of the lapic_ids to the srat table generation > This moves the sorting to of --> This moves the sorting of ? Yes, the `to` is spurious File src/soc/intel/xeon_sp/nb_acpi.c: https://review.coreboot.org/c/coreboot/+/68912/comment/97ee8c56_8e0acc46 PS3, Line 41: if (num_cpus > 1) We don't need these checks, bubblesort bails out early if there's less than 2 elements to sort. https://review.coreboot.org/c/coreboot/+/68912/comment/370b5e29_41ef8f3c PS3, Line 29: /* First all regular cpus, then all the threads */ : for (cpu = all_devices; cpu; cpu = cpu->next) { : if (!is_enabled_cpu(cpu)) : continue; : if (num_cpus >= ARRAY_SIZE(apic_ids)) : break; : /* Is this a thread? */ : if (cpu->path.apic.apic_id & 1) : continue; : apic_ids[num_cpus++] = cpu->path.apic.apic_id; : } : const uint32_t num_of_cores = num_cpus; : if (num_cpus > 1) : bubblesort(&apic_ids[0], num_of_cores, NUM_ASCENDING); Maybe rewrite this as a loop? ``` const uint32_t max_th_per_core = 2; uint32_t cpus_so_far = 0; for (uint32_t th_in_core = 0; th_in_core < max_th_per_core; th_in_core++) { for (cpu = all_devices; cpu; cpu = cpu->next) { if (!is_enabled_cpu(cpu)) continue; if (num_cpus >= ARRAY_SIZE(apic_ids)) break; /* Is this a thread? */ if (cpu->path.apic.apic_id % max_th_per_core != th_in_core) continue; apic_ids[num_cpus++] = cpu->path.apic.apic_id; } bubblesort(&apic_ids[cpus_so_far], num_cpus - cpus_so_far, NUM_ASCENDING); cpus_so_far = num_cpus; } ``` Yes, no idea if we'll ever have to deal with more than 2 threads per core. The compiler should be able to do loop unrolling if it thinks it's worth it. https://review.coreboot.org/c/coreboot/+/68912/comment/f1523c9e_c7daa9d9 PS3, Line 54: if (num_cpus > 1) What's the purpose of this check? Did you mean to check if `num_cpus - num_of_cores > 1` instead? You don't need any checks, `bubblesort()` bails out early if there's less than 2 elements to sort. https://review.coreboot.org/c/coreboot/+/68912/comment/f20c49ef_7f60227e PS3, Line 59: for (cpu = all_devices; cpu; cpu = cpu->next) { : if (!is_enabled_cpu(cpu)) : continue; : if (cpu->path.apic.apic_id == apic_ids[i]) : break; : } Hmmm, having to re-do this search is a bit inefficient... The problem seems to be that the `bubblesort()` function doesn't allow sorting `struct device *` according to the value of some member. Making a generic sort function in C would involve void pointers and function pointers: ``` typedef void (*comparator_func_t)(void *, void *); void generic_bubblesort(void *array[], size_t len, comparator_func_t fn); ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/68912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I372bcea1932d28e9bf712cc712f19a76fe3199b1 Gerrit-Change-Number: 68912 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Tue, 01 Nov 2022 17:25:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/common: provide display hook in PEP for ECs
by Michael Niewöhner (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Felix Singer, Michał Żygowski, Tim Wawrzynczak, Michał Kopeć, Michael Niewöhner. Hello Felix Singer, build bot (Jenkins), Michał Żygowski, Tim Wawrzynczak, Michał Kopeć, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68789 to look at the new patch set (#4). Change subject: soc/intel/common: provide display hook in PEP for ECs ...................................................................... soc/intel/common: provide display hook in PEP for ECs This will be used in the follow-up changes. Change-Id: Icbfd294cdd238e63eb947c227a9cf73daca702ef Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/common/block/acpi/pep.c 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/68789/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/68789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbfd294cdd238e63eb947c227a9cf73daca702ef Gerrit-Change-Number: 68789 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: util/scripts: Add script to run abuild on specific SOCs
by Martin L Roth (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Martin L Roth, Elyes Haouas. Hello build bot (Jenkins), Fred Reitberger, Elyes Haouas, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68956 to look at the new patch set (#2). Change subject: util/scripts: Add script to run abuild on specific SOCs ...................................................................... util/scripts: Add script to run abuild on specific SOCs This finds all the boards using a specified Kconfig option and runs both CrOS and non-CrOS abuilds on them to make sure they're working. Nobody wants to run the full what-jenkins-does build on their host machine. Hopefully this can help get some tests run locally before pushing to coreboot.org. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ifc71c28bf64a805f203a815a9468ff9fe882aad3 --- A util/scripts/testsoc 1 file changed, 197 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/68956/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc71c28bf64a805f203a815a9468ff9fe882aad3 Gerrit-Change-Number: 68956 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

1 0

[XL] Change in coreboot[master]: ec/clevo/it5570e: add driver for EC used on various Clevo laptops
by Michael Niewöhner (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Felix Singer, Michał Żygowski, Tim Wawrzynczak, Michał Kopeć, Angel Pons, Arthur Heymans. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68791 ) Change subject: ec/clevo/it5570e: add driver for EC used on various Clevo laptops ...................................................................... Patch Set 6: (1 comment) File src/ec/clevo/it5570e/ssdt.c: https://review.coreboot.org/c/coreboot/+/68791/comment/144f6343_75f5d12a PS4, Line 119: goto pop; > You can also avoid gotos by checking for errors before you begin writing anything to the tables. We *want* to write the function in any case bc it's always called. I don't see a reason to avoid `goto` here, tbh. Coreboot coding style guidelines don't forbid it. https://doc.coreboot.org/contributing/coding_style.html?highlight=goto#cent… -- To view, visit https://review.coreboot.org/c/coreboot/+/68791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8c0bee9002ad9edcd10c83b775fc723744caaa0 Gerrit-Change-Number: 68791 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 01 Nov 2022 17:17:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <inforichland(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/{lenovo,packardbell}: Enable MEI device
by Evgeny Zinoviev (Code Review) 01 Nov '22

01 Nov '22

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42412 ) Change subject: mb/{lenovo,packardbell}: Enable MEI device ...................................................................... mb/{lenovo,packardbell}: Enable MEI device Enable the MEI in device trees of some Ibex Peak, Cougar Point and Panther Point boards where they have been disabled. Change-Id: I4327d19d3ed1a93a6466057f6eceed49ab9441c5 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/packardbell/ms2290/devicetree.cb 8 files changed, 12 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/42412/1 diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index 6f4e608..9107f7c 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -51,7 +51,7 @@ register "spi_lvscc" = "0x2005" device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 2de774d..fa63971 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -56,7 +56,9 @@ register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - device pci 16.0 off end # MEI + device pci 16.0 on # MEI + subsystemid 0x17aa 0x215f + end device pci 16.2 on # IDE/SATA subsystemid 0x17aa 0x2161 end diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 5ac9cf5..795c372 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -69,7 +69,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index b3399c3..7a2f669 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -71,7 +71,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 40c706e..694f258 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -72,7 +72,7 @@ register "spi_lvscc" = "0x2005" device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index c84d7ea..b1a1131 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -68,7 +68,7 @@ register "spi_lvscc" = "0x2005" device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index bfb9da3..0c8fe79 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -68,7 +68,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index 50e648f..b614e83 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -48,7 +48,9 @@ register "alt_gp_smi_en" = "0x0000" register "gen1_dec" = "0x040069" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1025 0x0379 + end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R, only management boot device pci 16.3 off end # Management Engine KT -- To view, visit https://review.coreboot.org/c/coreboot/+/42412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4327d19d3ed1a93a6466057f6eceed49ab9441c5 Gerrit-Change-Number: 42412 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

3 8

[S] Change in coreboot[master]: mb/google/skyrim: Disable SD ASPM
by Paul Menzel (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Raul Rangel, Jason Nien, EricKY Cheng, Isaac Lee, Jon Murphy, Martin Roth, Eric Peers, Moises Garcia, Karthikeyan Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68940 ) Change subject: mb/google/skyrim: Disable SD ASPM ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68940/comment/949d0e14_f5d224aa PS6, Line 9: Disable ASPM on SD until b/245550573 is root-caused/fixed. Please summarize the bug, as not all people have access. -- To view, visit https://review.coreboot.org/c/coreboot/+/68940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If080cdb517a3f22aa89c8053fb6bba9e931c6f76 Gerrit-Change-Number: 68940 Gerrit-PatchSet: 6 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Tue, 01 Nov 2022 16:56:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XL] Change in coreboot[master]: ec/clevo/it5570e: add driver for EC used on various Clevo laptops
by Tim Wawrzynczak (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Felix Singer, Michał Żygowski, Michał Kopeć, Angel Pons, Arthur Heymans, Michael Niewöhner. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68791 ) Change subject: ec/clevo/it5570e: add driver for EC used on various Clevo laptops ...................................................................... Patch Set 6: (1 comment) File src/ec/clevo/it5570e/ssdt.c: https://review.coreboot.org/c/coreboot/+/68791/comment/293490ed_968b47cd PS4, Line 119: goto pop; > the whole function is only about the custom fan curve You can also avoid gotos by checking for errors before you begin writing anything to the tables. -- To view, visit https://review.coreboot.org/c/coreboot/+/68791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8c0bee9002ad9edcd10c83b775fc723744caaa0 Gerrit-Change-Number: 68791 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Tue, 01 Nov 2022 16:47:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/skyrim: Disable SD ASPM
by Tim Van Patten (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Raul Rangel, Jason Nien, EricKY Cheng, Isaac Lee, Jon Murphy, Martin Roth, Eric Peers, Moises Garcia, Karthikeyan Ramasubramanian. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68940 ) Change subject: mb/google/skyrim: Disable SD ASPM ...................................................................... Patch Set 6: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68940/comment/c42b5a00_7ea66fc1 PS6, Line 11: BUG=b:249914847 Please add `b:245550573`, since it's referenced in the TODO. -- To view, visit https://review.coreboot.org/c/coreboot/+/68940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If080cdb517a3f22aa89c8053fb6bba9e931c6f76 Gerrit-Change-Number: 68940 Gerrit-PatchSet: 6 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Tue, 01 Nov 2022 16:27:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/google/brask/variants/moli: remove fan setting
by 9elements QA (Code Review) 01 Nov '22

01 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69094 ) Change subject: mb/google/brask/variants/moli: remove fan setting ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/132683 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/132682 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/132681 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/132680 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/132679 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/132678 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/132677 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/132676 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/132675 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/132674 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/132673 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/132672 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/132671 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/132670 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/132669 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/132668 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8851800d30ebf4d948d6eaadda2387c8afe52d8 Gerrit-Change-Number: 69094 Gerrit-PatchSet: 3 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 16:23:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2022