coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Don't sort struct device cpus for numa
by Angel Pons (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Arthur Heymans, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Christian Walter, Shuming Chu (Shuming), TangYiwei. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68912 ) Change subject: soc/intel/xeon_sp: Don't sort struct device cpus for numa ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/xeon_sp/nb_acpi.c: https://review.coreboot.org/c/coreboot/+/68912/comment/a890a09d_f8ab8297 PS3, Line 59: for (cpu = all_devices; cpu; cpu = cpu->next) { : if (!is_enabled_cpu(cpu)) : continue; : if (cpu->path.apic.apic_id == apic_ids[i]) : break; : } > > Hmmm, having to re-do this search is a bit inefficient... […] The idea would be to have a generic bubblesort function, so that it can be used for anything. Although it's not like we need to sort a lot of things in coreboot. The thing is, it won't be type-safe because C doesn't have a type system, just numbers of varying sizes and purposes. In contrast, languages like Ada have an actual type system. [please do not take the "type system" stuff *too* seriously] -- To view, visit https://review.coreboot.org/c/coreboot/+/68912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I372bcea1932d28e9bf712cc712f19a76fe3199b1 Gerrit-Change-Number: 68912 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Tue, 01 Nov 2022 18:29:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/hatch: Add variant finalize support for hatch devices
by Nick Vaccaro (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Tarun Tuli, Eran Mitrani. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68821 ) Change subject: mb/google/hatch: Add variant finalize support for hatch devices ...................................................................... Patch Set 13: (1 comment) File src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h: https://review.coreboot.org/c/coreboot/+/68821/comment/1dd89076_8c3da99a PS13, Line 31: variant_finalize_gpio_table > Where is the code for this? I found it. Should this call not be preceded by "variant_" given that it's only applicable to kohaku's ramstage.c? Usually the "variant_" routines are called from a common place (SoC or mainboard) and support a __weak function for variants that don't imnplement it. This variant_ routine appears to only be used in Kohaku by Kohaku. -- To view, visit https://review.coreboot.org/c/coreboot/+/68821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9253ed4be1b08d0c7f65526c9b26dbcd00ffccc7 Gerrit-Change-Number: 68821 Gerrit-PatchSet: 13 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 18:23:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: drivers/ocp/dmi: Fix smbios type 11 get wrong ppin value for second s...
by Angel Pons (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Jonathan Zhang, Shuming Chu (Shuming), Arthur Heymans, TangYiwei. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68910 ) Change subject: drivers/ocp/dmi: Fix smbios type 11 get wrong ppin value for second socket ...................................................................... Patch Set 4: Code-Review+1 (2 comments) File src/drivers/ocp/dmi/smbios.c: https://review.coreboot.org/c/coreboot/+/68910/comment/73460a93_c672688e PS4, Line 259: get_logic_cpu(1), 100 * USECS_PER_MSEC) != > what if the return value of get_logic_cpu() is -1? Looks like it wouldn't do anything, but it would be wise to add a check. https://review.coreboot.org/c/coreboot/+/68910/comment/085b494f_473135d8 PS4, Line 264: /* Wait for read_remote_ppin() to finish because it's executed : in parallel */ For another patch: There's the `mp_run_on_aps_and_wait_for_complete()` function. -- To view, visit https://review.coreboot.org/c/coreboot/+/68910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9174522c57680a57e6e4629b4e81fd837c38d47a Gerrit-Change-Number: 68910 Gerrit-PatchSet: 4 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Tue, 01 Nov 2022 18:19:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Don't sort struct device cpus for numa
by Arthur Heymans (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Christian Walter, Angel Pons, Arthur Heymans, Shuming Chu (Shuming), TangYiwei. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68912 ) Change subject: soc/intel/xeon_sp: Don't sort struct device cpus for numa ...................................................................... Patch Set 3: (5 comments) Patchset: PS3: Thanks for reviewing! I think MADT code actually needs something similar. I also want to put the topology code inside common mp_init.c. It's common accros x86 CPUs. File src/soc/intel/xeon_sp/cpx/cpu.c: https://review.coreboot.org/c/coreboot/+/68912/comment/d385e81b_f911d095 PS3, Line 81: apic_id Should be package_id File src/soc/intel/xeon_sp/nb_acpi.c: https://review.coreboot.org/c/coreboot/+/68912/comment/a242c311_a3cfe66f PS3, Line 29: /* First all regular cpus, then all the threads */ : for (cpu = all_devices; cpu; cpu = cpu->next) { : if (!is_enabled_cpu(cpu)) : continue; : if (num_cpus >= ARRAY_SIZE(apic_ids)) : break; : /* Is this a thread? */ : if (cpu->path.apic.apic_id & 1) : continue; : apic_ids[num_cpus++] = cpu->path.apic.apic_id; : } : const uint32_t num_of_cores = num_cpus; : if (num_cpus > 1) : bubblesort(&apic_ids[0], num_of_cores, NUM_ASCENDING); > Maybe rewrite this as a loop? > > ``` > const uint32_t max_th_per_core = 2; > uint32_t cpus_so_far = 0; > for (uint32_t th_in_core = 0; th_in_core < max_th_per_core; th_in_core++) { > for (cpu = all_devices; cpu; cpu = cpu->next) { > if (!is_enabled_cpu(cpu)) > continue; > if (num_cpus >= ARRAY_SIZE(apic_ids)) > break; > /* Is this a thread? */ > if (cpu->path.apic.apic_id % max_th_per_core != th_in_core) > continue; > apic_ids[num_cpus++] = cpu->path.apic.apic_id; > } > bubblesort(&apic_ids[cpus_so_far], num_cpus - cpus_so_far, NUM_ASCENDING); > cpus_so_far = num_cpus; > } > ``` > > Yes, no idea if we'll ever have to deal with more than 2 threads per core. The compiler should be able to do loop unrolling if it thinks it's worth it. I want to put that information in struct path. It already has a tread_id entry. it can loop over thread_id. If no thread_id CPU is found a loop can break. That would allow for more than 2 threads per core_id. https://review.coreboot.org/c/coreboot/+/68912/comment/c1ff5175_d857a048 PS3, Line 54: if (num_cpus > 1) > What's the purpose of this check? Did you mean to check if `num_cpus - num_of_cores > 1` instead? You don't need any checks, `bubblesort()` bails out early if there's less than 2 elements to sort. copy pasta from MADT code. https://review.coreboot.org/c/coreboot/+/68912/comment/ce370a9e_1581b684 PS3, Line 59: for (cpu = all_devices; cpu; cpu = cpu->next) { : if (!is_enabled_cpu(cpu)) : continue; : if (cpu->path.apic.apic_id == apic_ids[i]) : break; : } > Hmmm, having to re-do this search is a bit inefficient... The problem seems to be that the `bubblesort()` function doesn't allow sorting `struct device *` according to the value of some member. Making a generic sort function in C would involve void pointers and function pointers: > > ``` > typedef void (*comparator_func_t)(void *, void *); > void generic_bubblesort(void *array[], size_t len, comparator_func_t fn); > ``` Using array of struct *path or struct *device and a comparator is indeed the way to go :-) -- To view, visit https://review.coreboot.org/c/coreboot/+/68912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I372bcea1932d28e9bf712cc712f19a76fe3199b1 Gerrit-Change-Number: 68912 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Tue, 01 Nov 2022 18:16:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/hatch: Add variant finalize support for hatch devices
by Nick Vaccaro (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Tarun Tuli, Eran Mitrani. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68821 ) Change subject: mb/google/hatch: Add variant finalize support for hatch devices ...................................................................... Patch Set 13: (1 comment) File src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h: https://review.coreboot.org/c/coreboot/+/68821/comment/4194a6d4_d987d230 PS13, Line 31: variant_finalize_gpio_table Where is the code for this? -- To view, visit https://review.coreboot.org/c/coreboot/+/68821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9253ed4be1b08d0c7f65526c9b26dbcd00ffccc7 Gerrit-Change-Number: 68821 Gerrit-PatchSet: 13 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 18:13:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Hook up GMA ACPI brightness controls
by Tim Crawford (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69076 to look at the new patch set (#2). Change subject: soc/intel/alderlake: Hook up GMA ACPI brightness controls ...................................................................... soc/intel/alderlake: Hook up GMA ACPI brightness controls Add function needed to generate ACPI backlight control SSDT, along with Kconfig values for accessing the registers. Tested by adding gfx register on system76/lemp11. Backlight controls work on Windows 10 and Linux 6.1. Change-Id: I1cc33bf0121ff44aea68a7e3615c5e58e2ab6ce2 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/chip.h A src/soc/intel/alderlake/graphics.c 4 files changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/69076/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cc33bf0121ff44aea68a7e3615c5e58e2ab6ce2 Gerrit-Change-Number: 69076 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/hatch: Kohaku - ensure FPMCU is power cycled on reset
by Nick Vaccaro (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Tarun Tuli, Eran Mitrani. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68819 ) Change subject: mb/google/hatch: Kohaku - ensure FPMCU is power cycled on reset ...................................................................... Patch Set 20: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e7e32f61c3ac1b3154d42821cc1dd4c5d3de303 Gerrit-Change-Number: 68819 Gerrit-PatchSet: 20 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Comment-Date: Tue, 01 Nov 2022 18:11:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: NOTFORMERGE/WIP/POC Use FDT as payload handoff instead lb_tables
by Arthur Heymans (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Martin L Roth, Stefan Reinauer, Julius Werner, Arthur Heymans. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68719 ) Change subject: NOTFORMERGE/WIP/POC Use FDT as payload handoff instead lb_tables ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Were there any discussions about this that I missed (if so would you mind linking to them)? Can you explain who needs this and why, what's the overall goal? (I know there have been vague discussions about various new firmware handoff formats from Arm and Intel and others, but if this is related to those I missed the parts where there was suddenly consensus on how it should look, and why that is FDT.) Most of the discussion happened verbally at osfc, so I can't point to any written communication. There is https://www.osfc.io/2022/talks/collaborative-firmware-payload-handoff-desig… if you have the time to listen to a talk. So if I have to summarize the idea's/goals: - Intel Universal scalable firmware suggested using UEFI HOBs as a handoff structure - coreboot won't do that as it's no improvement over coreboot tables - USF won't make coreboot tables a standard either - Maybe something new can be created that would fit both the needs of payload handoff and other binary information passing between programs (e.g. FSP)? - USF people suggested using CBOR to encode data to so that serialization/deserialization of data is explicit instead of using structs. - CBOR is an improvement for the data format, but not what coreboot/(other project) should tell the payload: i.e. what entries are needed - FDT was suggested as an alternative as it covers both explicit serialization/deserialization + what payload tell each other since the spec already exists, with a lot of existing compatible node strings. (e.g. I reuse simple-framebuffer from Linux here to hand of the framebuffer) Also most payloads and firmware have code for working with FDT. - (unrelated to payload handof but part of the discussions) Another idea is to also use FDT as an interface between coreboot and FSP. - a lot of payloads already have code to work with FDT so having FDT as a handoff structure would not be a lot of work - FDT should make compatibility between coreboot and payload easier when handoff entries are added or changed (plain structs are painful if they are updated as both payload and coreboot definitions need to match) - debugging the handoff structure is easier with FDT as you can use DTC in the OS userspace or coreboot code can also print out the full structure in human readable format. What are your thoughts? - Is it a good idea to use FDT and eventually replace coreboot tables. - If so, do we keep both for a while to make transitioning easier? I think maintaining two structures is not sustainable long term. - How should the 'entries' be structured? I made compatible nodes that map somewhat to existing coreboot table structs. -- To view, visit https://review.coreboot.org/c/coreboot/+/68719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id96d4e7805855d35392e78f8d7b3a1ff911105a3 Gerrit-Change-Number: 68719 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 01 Nov 2022 18:10:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: payloads/cbui: Add new payload CBUI
by Iman Bingi (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Iman Bingi, Martin L Roth, Julius Werner, Patrick Rudolph. Iman Bingi has uploaded a new patch set (#190) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/23586 ) Change subject: payloads/cbui: Add new payload CBUI ...................................................................... payloads/cbui: Add new payload CBUI Depends on libpayload and nuklear. Features: * Graphical menus with scrolling. * Text rendering engine (atm only bitmap font) * Support for keyboard and mouse * Support for USB and PS/2 devices * Ported coreinfo and nvramcui * Allows to modify NVRAM and RTC * Works as ELF payload * Works as Seabios secondary payload * Basic support for multiple languages * Hacky support for BIOS calls (depends on NASM) * Runs in qemu and on real hardware * Use linker script to allocate low memory Shortcomings: * Doesn't work in VGA text mode * Untested on UEFI * int32 relocates itself to low memory Licenses: * GPLv2 (CBUI + libpayload) * BSD (libpayload) * MIT (nuklear) TODO: * Test on as much platforms as possible * Link int32 into low memory This is Patrick Rudolph's original patch, updated by Ben Adu-Boahen to: * Add Read/Write module * This module allows read/write to any hardware component that is readable/writeable Note: This is work in progress Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Signed-off-by: Ben Adu-Boahen <imanbingy(a)gmail.com> --- M payloads/Kconfig M payloads/Makefile.inc A payloads/cbui/.gitignore A payloads/cbui/Kconfig A payloads/cbui/Makefile A payloads/cbui/NuklearUI/NuklearCheckbox.c A payloads/cbui/NuklearUI/NuklearCheckbox.h A payloads/cbui/NuklearUI/NuklearCombo.c A payloads/cbui/NuklearUI/NuklearCombo.h A payloads/cbui/NuklearUI/NuklearCommon.h A payloads/cbui/NuklearUI/NuklearDataGrid.c A payloads/cbui/NuklearUI/NuklearDataGrid.h A payloads/cbui/NuklearUI/NuklearDatePicker.c A payloads/cbui/NuklearUI/NuklearDatePicker.h A payloads/cbui/NuklearUI/NuklearFieldFile.c A payloads/cbui/NuklearUI/NuklearFieldFile.h A payloads/cbui/NuklearUI/NuklearFieldHex.c A payloads/cbui/NuklearUI/NuklearFieldHex.h A payloads/cbui/NuklearUI/NuklearFileChooser.c A payloads/cbui/NuklearUI/NuklearFileChooser.h A payloads/cbui/NuklearUI/NuklearGroup.c A payloads/cbui/NuklearUI/NuklearGroup.h A payloads/cbui/NuklearUI/NuklearHex.c A payloads/cbui/NuklearUI/NuklearHex.h A payloads/cbui/NuklearUI/NuklearIntegerRange.c A payloads/cbui/NuklearUI/NuklearIntegerRange.h A payloads/cbui/NuklearUI/NuklearLabel.c A payloads/cbui/NuklearUI/NuklearLabel.h A payloads/cbui/NuklearUI/NuklearObject.c A payloads/cbui/NuklearUI/NuklearObject.h A payloads/cbui/NuklearUI/NuklearRW.c A payloads/cbui/NuklearUI/NuklearRW.h A payloads/cbui/NuklearUI/NuklearRoot.c A payloads/cbui/NuklearUI/NuklearRwAcpi.c A payloads/cbui/NuklearUI/NuklearRwAcpi.h A payloads/cbui/NuklearUI/NuklearRwAtaAtapi.c A payloads/cbui/NuklearUI/NuklearRwAtaAtapi.h A payloads/cbui/NuklearUI/NuklearRwDimmSpd.c A payloads/cbui/NuklearUI/NuklearRwDimmSpd.h A payloads/cbui/NuklearUI/NuklearRwEc.c A payloads/cbui/NuklearUI/NuklearRwEc.h A payloads/cbui/NuklearUI/NuklearRwIo.c A payloads/cbui/NuklearUI/NuklearRwIo.h A payloads/cbui/NuklearUI/NuklearRwIoIndexData.c A payloads/cbui/NuklearUI/NuklearRwIoIndexData.h A payloads/cbui/NuklearUI/NuklearRwMemory.c A payloads/cbui/NuklearUI/NuklearRwMemory.h A payloads/cbui/NuklearUI/NuklearRwMemoryIndexData.c A payloads/cbui/NuklearUI/NuklearRwMemoryIndexData.h A payloads/cbui/NuklearUI/NuklearRwNvram.c A payloads/cbui/NuklearUI/NuklearRwNvram.h A payloads/cbui/NuklearUI/NuklearRwPci.c A payloads/cbui/NuklearUI/NuklearRwPci.h A payloads/cbui/NuklearUI/NuklearRwPciIndexData.c A payloads/cbui/NuklearUI/NuklearRwPciIndexData.h A payloads/cbui/NuklearUI/NuklearRwSuperIo.c A payloads/cbui/NuklearUI/NuklearRwSuperIo.h A payloads/cbui/NuklearUI/NuklearStyle.c A payloads/cbui/NuklearUI/NuklearStyle.h A payloads/cbui/NuklearUI/NuklearTabView.c A payloads/cbui/NuklearUI/NuklearTextView.c A payloads/cbui/NuklearUI/NuklearTextView.h A payloads/cbui/NuklearUI/NuklearTextfield.c A payloads/cbui/NuklearUI/NuklearTextfield.h A payloads/cbui/NuklearUI/NuklearTimePicker.c A payloads/cbui/NuklearUI/NuklearTimePicker.h A payloads/cbui/NuklearUI/NuklearUI.h A payloads/cbui/NuklearUI/NuklearVector.c A payloads/cbui/NuklearUI/NuklearVector.h A payloads/cbui/arch/x86/cpuid.c A payloads/cbui/arch/x86/cpuid.h A payloads/cbui/arch/x86/int32.h A payloads/cbui/arch/x86/int32.ld A payloads/cbui/arch/x86/int32.nasm A payloads/cbui/arch/x86/memcpy.c A payloads/cbui/arch/x86/memcpy.h A payloads/cbui/arch/x86/vga.c A payloads/cbui/arch/x86/vga.h A payloads/cbui/cbui.c A payloads/cbui/cbui.h A payloads/cbui/fsys/usbstorage.c A payloads/cbui/fsys/usbstorage.h A payloads/cbui/gfx/coreboot.c A payloads/cbui/gfx/coreboot.h A payloads/cbui/gfx/gfx.c A payloads/cbui/gfx/gfx.h A payloads/cbui/gfx/splash.c A payloads/cbui/gfx/splash.h A payloads/cbui/gfx/vbe.c A payloads/cbui/gfx/vbe.h A payloads/cbui/lang/de.c A payloads/cbui/lang/en.c A payloads/cbui/lang/lang.c A payloads/cbui/lang/lang.h A payloads/cbui/logo/cbui.png A payloads/cbui/lp.config A payloads/cbui/modules/bootlog_module.c A payloads/cbui/modules/cbfs_module.c A payloads/cbui/modules/cmos_module.c A payloads/cbui/modules/coreboot_module.c A payloads/cbui/modules/cpuinfo_module.c A payloads/cbui/modules/license_module.c A payloads/cbui/modules/modules.c A payloads/cbui/modules/modules.h A payloads/cbui/modules/nvram_module.c A payloads/cbui/modules/pci_module.c A payloads/cbui/modules/reboot_module.c A payloads/cbui/modules/rtc_module.c A payloads/cbui/modules/rw_module.c A payloads/cbui/modules/timestamps_module.c A payloads/cbui/modules/usb_module.c A payloads/cbui/smbios/smbios.c A payloads/cbui/smbios/smbios.h A payloads/cbui/smbios/smbios_oem.c A payloads/cbui/smbios/smbios_oem.h A payloads/cbui/smbios/smbios_output.c A payloads/cbui/smbios/smbios_output.h A payloads/cbui/util/stringbuffer.c A payloads/cbui/util/stringbuffer.h A payloads/libpayload/configs/defconfig-cbui 120 files changed, 24,842 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/23586/190 -- To view, visit https://review.coreboot.org/c/coreboot/+/23586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1 Gerrit-Change-Number: 23586 Gerrit-PatchSet: 190 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: mb/system76/adl-p: Add Lemur Pro 11 as a variant
by Tim Crawford (Code Review) 01 Nov '22

01 Nov '22

Attention is currently required from: Jeremy Soller. Hello build bot (Jenkins), Jeremy Soller, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/65384 to look at the new patch set (#15). Change subject: mb/system76/adl-p: Add Lemur Pro 11 as a variant ...................................................................... mb/system76/adl-p: Add Lemur Pro 11 as a variant The Lemur Pro 11 (lemp11) is an Alder Lake-U board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard, touchpad - DIMM slot (with NMSO480E82-3200EA00) - M.2 NVMe SSD (with MZVL2500HCJQ) - M.2 SATA SSD (with WDS100T2B0B) - All USB ports - SD card reader - Webcam - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - HDMI output - DisplayPort output over USB-C - Internal microphone - Internal speakers - Combined headset + mic 3.5mm audio - Booting Pop!_OS Linux 22.04 with kernel 5.18.5 - Internal flashing with flashrom v1.2-703-g76118a7c10ed Not working: - On-board RAM: Requires CB:65567 - Detection of devices in TBT slot on boot - S0ix suspend/resume Change-Id: Ic930df1ebacc8c7ef14dbb6c67a97eddb918b365 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/system76/lemp11.md M src/mainboard/system76/adl-p/Kconfig M src/mainboard/system76/adl-p/Kconfig.name M src/mainboard/system76/adl-p/Makefile.inc A src/mainboard/system76/adl-p/spd/samsung-P4AAF165WA-BCWDE.spd.hex A src/mainboard/system76/adl-p/variants/lemp11/board_info.txt A src/mainboard/system76/adl-p/variants/lemp11/data.vbt A src/mainboard/system76/adl-p/variants/lemp11/gpio.c A src/mainboard/system76/adl-p/variants/lemp11/gpio_early.c A src/mainboard/system76/adl-p/variants/lemp11/hda_verb.c A src/mainboard/system76/adl-p/variants/lemp11/overridetree.cb A src/mainboard/system76/adl-p/variants/lemp11/romstage.c 13 files changed, 592 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/65384/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/65384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic930df1ebacc8c7ef14dbb6c67a97eddb918b365 Gerrit-Change-Number: 65384 Gerrit-PatchSet: 15 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2022