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Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yu-Ping Wu, Yidi Lin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69089
to look at the new patch set (#6).
Change subject: soc/mediatek/mt8188: Disable input-gating for big-core SRAM
......................................................................
soc/mediatek/mt8188: Disable input-gating for big-core SRAM
The input-gating is an experimental feature (but unfortunately default
enabled) and would lead to crash on MT8188, so we have to disable it
in the firmware stage.
BUG=b:233720142
TEST=CPUfreq in kernel test pass.
Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca
Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com>
---
M src/soc/mediatek/mt8188/Makefile.inc
A src/soc/mediatek/mt8188/cpu_inputgating.c
A src/soc/mediatek/mt8188/include/soc/cpu_inputgating.h
M src/soc/mediatek/mt8188/soc.c
4 files changed, 45 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/69089/6
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Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yidi Lin, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69088
to look at the new patch set (#6).
Change subject: soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver
......................................................................
soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver
When enabling cpufreq-hw driver, MCUPM will conduct power tasks and
access some registers of the other hardware. There are some registers
configured as secure read/write due to the hardware design. So we
enable sideband to allow MCUPM to access the secure registers.
BUG=b:236331463
TEST=It works well after boot to login shell.
Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6
Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com>
---
M src/soc/mediatek/mt8188/devapc.c
M src/soc/mediatek/mt8188/include/soc/devapc.h
2 files changed, 24 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/69088/6
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Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yidi Lin, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69139
to look at the new patch set (#2).
Change subject: Revert "soc/mediatek/mt8188: Allow CPUfreq hardware to access MCUPM registers"
......................................................................
Revert "soc/mediatek/mt8188: Allow CPUfreq hardware to access MCUPM registers"
This reverts commit a8172c329fe309f3b5b409c1a59a227186400dd4.
In this patch, we allow MCUPM to access secure registers and set the
domain to DOMAIN_2.
Additional attribute settings are also required when a hardware is
set to a specific domain. Otherwise, there would be violation between
hardware. Since MT8188 is in bring-up stage, we simply enable access
register permission for the DOMAIN_0 by default. So remove the wrong
setting for MCUPM, SCP and SSPM.
We will complete DEVAPC setting when the settings are confirmed.
Change-Id: I5d9809f6e84b8d10bc2e6f2ea5a442e676ad3bf9
Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com>
---
M src/soc/mediatek/mt8188/devapc.c
M src/soc/mediatek/mt8188/include/soc/devapc.h
2 files changed, 23 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/69139/2
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69139 )
Change subject: Revert "soc/mediatek/mt8188: Allow CPUfreq hardware to access MCUPM registers"
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69139/comment/bff1a061_fd3313aa
PS1, Line 11: In this patch, we allow MCUPM to access secure registers and set the
: domain to DOMAIN_2.
nit: Is this about commit a8172c329fe309f3b5b409c1a59a227186400dd4 ? It's a bit confusing: "this patch" could mean CB:69139 (this) or CB:67724 (the reverted commit).
https://review.coreboot.org/c/coreboot/+/69139/comment/7e61c142_32f5e856
PS1, Line 21:
Signed-off-by is missing
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Ren Kuo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68523 )
Change subject: mb/google/nissa/var/craask: Modify PL2 setting to 25w
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/brya/variants/craask/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/68523/comment/a90a6d6f_4404c002
PS3, Line 158: }"
> Hi Peter, […]
Hi Vidya,
Only PL1 and PL2 are controllable via DPTF, right ?
The current initial setting is 78W ?
https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi…
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69120
to look at the new patch set (#13).
Change subject: sb/amd: Remove dropped platforms
......................................................................
sb/amd: Remove dropped platforms
This code is now unused by any platform.
Change-Id: I60afbde6ead70f0c887866fc351b4a6a15a89287
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/drivers/amd/agesa/state_machine.c
M src/northbridge/amd/agesa/state_machine.h
D src/southbridge/amd/agesa/Kconfig
D src/southbridge/amd/agesa/Makefile.inc
D src/southbridge/amd/agesa/hudson/Kconfig
D src/southbridge/amd/agesa/hudson/Makefile.inc
D src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl
D src/southbridge/amd/agesa/hudson/acpi/audio.asl
D src/southbridge/amd/agesa/hudson/acpi/fch.asl
D src/southbridge/amd/agesa/hudson/acpi/lpc.asl
D src/southbridge/amd/agesa/hudson/acpi/pci_int.asl
D src/southbridge/amd/agesa/hudson/acpi/pcie.asl
D src/southbridge/amd/agesa/hudson/acpi/smbus.asl
D src/southbridge/amd/agesa/hudson/acpi/usb.asl
D src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h
D src/southbridge/amd/agesa/hudson/amd_pci_int_types.h
D src/southbridge/amd/agesa/hudson/bootblock.c
D src/southbridge/amd/agesa/hudson/chip.h
D src/southbridge/amd/agesa/hudson/early_setup.c
D src/southbridge/amd/agesa/hudson/enable_usbdebug.c
D src/southbridge/amd/agesa/hudson/fadt.c
D src/southbridge/amd/agesa/hudson/hda.c
D src/southbridge/amd/agesa/hudson/hudson.c
D src/southbridge/amd/agesa/hudson/hudson.h
D src/southbridge/amd/agesa/hudson/ide.c
D src/southbridge/amd/agesa/hudson/imc.c
D src/southbridge/amd/agesa/hudson/imc.h
D src/southbridge/amd/agesa/hudson/lpc.c
D src/southbridge/amd/agesa/hudson/pci.c
D src/southbridge/amd/agesa/hudson/pci_devs.h
D src/southbridge/amd/agesa/hudson/pcie.c
D src/southbridge/amd/agesa/hudson/ramtop.c
D src/southbridge/amd/agesa/hudson/reset.c
D src/southbridge/amd/agesa/hudson/resume.c
D src/southbridge/amd/agesa/hudson/sata.c
D src/southbridge/amd/agesa/hudson/sd.c
D src/southbridge/amd/agesa/hudson/sm.c
D src/southbridge/amd/agesa/hudson/smbus.c
D src/southbridge/amd/agesa/hudson/smbus.h
D src/southbridge/amd/agesa/hudson/smbus_spd.c
D src/southbridge/amd/agesa/hudson/smi.c
D src/southbridge/amd/agesa/hudson/smi.h
D src/southbridge/amd/agesa/hudson/smi_util.c
D src/southbridge/amd/agesa/hudson/smihandler.c
D src/southbridge/amd/agesa/hudson/spi.c
D src/southbridge/amd/agesa/hudson/usb.c
D src/southbridge/amd/cimx/Kconfig
D src/southbridge/amd/cimx/Makefile.inc
D src/southbridge/amd/cimx/sb800/Amd.h
D src/southbridge/amd/cimx/sb800/AmdSbLib.h
D src/southbridge/amd/cimx/sb800/Kconfig
D src/southbridge/amd/cimx/sb800/Makefile.inc
D src/southbridge/amd/cimx/sb800/SBPLATFORM.h
D src/southbridge/amd/cimx/sb800/acpi/audio.asl
D src/southbridge/amd/cimx/sb800/acpi/fch.asl
D src/southbridge/amd/cimx/sb800/acpi/lpc.asl
D src/southbridge/amd/cimx/sb800/acpi/misc_io.asl
D src/southbridge/amd/cimx/sb800/acpi/pcie.asl
D src/southbridge/amd/cimx/sb800/acpi/smbus.asl
D src/southbridge/amd/cimx/sb800/acpi/usb.asl
D src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h
D src/southbridge/amd/cimx/sb800/amd_pci_int_types.h
D src/southbridge/amd/cimx/sb800/bootblock.c
D src/southbridge/amd/cimx/sb800/cfg.c
D src/southbridge/amd/cimx/sb800/cfg.h
D src/southbridge/amd/cimx/sb800/chip.h
D src/southbridge/amd/cimx/sb800/early.c
D src/southbridge/amd/cimx/sb800/fadt.c
D src/southbridge/amd/cimx/sb800/fan.c
D src/southbridge/amd/cimx/sb800/fan.h
D src/southbridge/amd/cimx/sb800/gpio_oem.h
D src/southbridge/amd/cimx/sb800/late.c
D src/southbridge/amd/cimx/sb800/lpc.c
D src/southbridge/amd/cimx/sb800/lpc.h
D src/southbridge/amd/cimx/sb800/pci_devs.h
D src/southbridge/amd/cimx/sb800/ramtop.c
D src/southbridge/amd/cimx/sb800/reset.c
D src/southbridge/amd/cimx/sb800/sb_cimx.h
D src/southbridge/amd/cimx/sb800/smbus.c
D src/southbridge/amd/cimx/sb800/smbus.h
D src/southbridge/amd/cimx/sb800/smbus_spd.c
D src/southbridge/amd/cimx/sb800/smbus_spd.h
D src/southbridge/amd/cimx/sb800/spi.c
M src/southbridge/amd/common/Makefile.inc
M src/southbridge/amd/pi/hudson/acpi/fch.asl
M src/southbridge/amd/pi/hudson/hudson.c
M src/vendorcode/amd/Makefile.inc
D src/vendorcode/amd/cimx/Makefile.inc
D src/vendorcode/amd/cimx/sb800/ACPILIB.c
D src/vendorcode/amd/cimx/sb800/ACPILIB.h
D src/vendorcode/amd/cimx/sb800/AMDLIB.c
D src/vendorcode/amd/cimx/sb800/AMDSBLIB.c
D src/vendorcode/amd/cimx/sb800/AMDSBLIB.h
D src/vendorcode/amd/cimx/sb800/AZALIA.c
D src/vendorcode/amd/cimx/sb800/DISPATCHER.c
D src/vendorcode/amd/cimx/sb800/EC.c
D src/vendorcode/amd/cimx/sb800/ECLIB.c
D src/vendorcode/amd/cimx/sb800/ECfan.h
D src/vendorcode/amd/cimx/sb800/ECfanLIB.c
D src/vendorcode/amd/cimx/sb800/ECfanc.c
D src/vendorcode/amd/cimx/sb800/GEC.c
D src/vendorcode/amd/cimx/sb800/Gpp.c
D src/vendorcode/amd/cimx/sb800/IOLIB.c
D src/vendorcode/amd/cimx/sb800/LEGACY.c
D src/vendorcode/amd/cimx/sb800/MEMLIB.c
D src/vendorcode/amd/cimx/sb800/Makefile.inc
D src/vendorcode/amd/cimx/sb800/OEM.h
D src/vendorcode/amd/cimx/sb800/PCILIB.c
D src/vendorcode/amd/cimx/sb800/PMIO2LIB.c
D src/vendorcode/amd/cimx/sb800/PMIOLIB.c
D src/vendorcode/amd/cimx/sb800/SATA.c
D src/vendorcode/amd/cimx/sb800/SB800.h
D src/vendorcode/amd/cimx/sb800/SBCMN.c
D src/vendorcode/amd/cimx/sb800/SBDEF.h
D src/vendorcode/amd/cimx/sb800/SBMAIN.c
D src/vendorcode/amd/cimx/sb800/SBPELIB.c
D src/vendorcode/amd/cimx/sb800/SBPort.c
D src/vendorcode/amd/cimx/sb800/SBSUBFUN.h
D src/vendorcode/amd/cimx/sb800/SBTYPE.h
D src/vendorcode/amd/cimx/sb800/SMM.c
D src/vendorcode/amd/cimx/sb800/SbModInf.c
D src/vendorcode/amd/cimx/sb800/USB.c
122 files changed, 13 insertions(+), 19,198 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/69120/13
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69117
to look at the new patch set (#8).
Change subject: {cpu/nb}/amd/family16: Remove platform
......................................................................
{cpu/nb}/amd/family16: Remove platform
This platform use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.
Change-Id: I589f30ccf81b6cf243ac7cbf8320a3f830649ad8
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/amd/agesa/Kconfig
M src/cpu/amd/agesa/Makefile.inc
D src/cpu/amd/agesa/family16kb/Kconfig
D src/cpu/amd/agesa/family16kb/Makefile.inc
D src/cpu/amd/agesa/family16kb/acpi/cpu.asl
D src/cpu/amd/agesa/family16kb/chip_name.c
D src/cpu/amd/agesa/family16kb/fixme.c
D src/cpu/amd/agesa/family16kb/model_16_init.c
D src/northbridge/amd/agesa/Makefile.inc
D src/northbridge/amd/agesa/family16kb/Kconfig
D src/northbridge/amd/agesa/family16kb/Makefile.inc
D src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl
D src/northbridge/amd/agesa/family16kb/acpi_tables.c
D src/northbridge/amd/agesa/family16kb/chip.h
D src/northbridge/amd/agesa/family16kb/dimmSpd.c
D src/northbridge/amd/agesa/family16kb/northbridge.c
D src/northbridge/amd/agesa/family16kb/pci_devs.h
D src/northbridge/amd/agesa/family16kb/state_machine.c
M src/vendorcode/amd/agesa/Kconfig
M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c
20 files changed, 14 insertions(+), 1,330 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/69117/8
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Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
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Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newpatchset
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69116
to look at the new patch set (#8).
Change subject: {cpu/nb}/amd/family15tn: Remove platform
......................................................................
{cpu/nb}/amd/family15tn: Remove platform
This platform use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.
Change-Id: I18eb1c1ccad16980a4e57318dec411b82c45b25a
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/amd/agesa/Kconfig
M src/cpu/amd/agesa/Makefile.inc
D src/cpu/amd/agesa/family15tn/Kconfig
D src/cpu/amd/agesa/family15tn/Makefile.inc
D src/cpu/amd/agesa/family15tn/acpi/cpu.asl
D src/cpu/amd/agesa/family15tn/chip_name.c
D src/cpu/amd/agesa/family15tn/fixme.c
D src/cpu/amd/agesa/family15tn/model_15_init.c
D src/cpu/amd/agesa/family15tn/udelay.c
M src/cpu/x86/smm/smmhandler.S
M src/northbridge/amd/agesa/Makefile.inc
D src/northbridge/amd/agesa/family15tn/Kconfig
D src/northbridge/amd/agesa/family15tn/Makefile.inc
D src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl
D src/northbridge/amd/agesa/family15tn/acpi_tables.c
D src/northbridge/amd/agesa/family15tn/chip.h
D src/northbridge/amd/agesa/family15tn/dimmSpd.c
D src/northbridge/amd/agesa/family15tn/iommu.c
D src/northbridge/amd/agesa/family15tn/northbridge.c
D src/northbridge/amd/agesa/family15tn/pci_devs.h
D src/northbridge/amd/agesa/family15tn/state_machine.c
21 files changed, 13 insertions(+), 1,407 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/69116/8
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I18eb1c1ccad16980a4e57318dec411b82c45b25a
Gerrit-Change-Number: 69116
Gerrit-PatchSet: 8
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newpatchset