coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

1 participants
7286 discussions

[XL] Change in coreboot[master]: mb/*/*: Remove AMD FAMILY15TN boards
by Elyes Haouas (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Arthur Heymans, Alexander Couzens. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69111 ) Change subject: mb/*/*: Remove AMD FAMILY15TN boards ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9efb5cb1149cc4cf6337c47af8a2f4c4b55f4368 Gerrit-Change-Number: 69111 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Wed, 02 Nov 2022 09:39:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: Revert "soc/mediatek/mt8188: Allow CPUfreq hardware to access MCUPM r...
by Liju-Clr Chen (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Angel Pons, Yu-Ping Wu. Liju-Clr Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69139 ) Change subject: Revert "soc/mediatek/mt8188: Allow CPUfreq hardware to access MCUPM registers" ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69139/comment/9a9dcfd2_de65fc72 PS1, Line 11: In this patch, we allow MCUPM to access secure registers and set the : domain to DOMAIN_2. > nit: Is this about commit a8172c329fe309f3b5b409c1a59a227186400dd4 ? It's a bit confusing: "this pat […] Done https://review.coreboot.org/c/coreboot/+/69139/comment/b47310bb_7760bdd6 PS1, Line 21: > Signed-off-by is missing Done Commit Message: https://review.coreboot.org/c/coreboot/+/69139/comment/7d388e9e_5e92848d PS3, Line 11: In the patch CB:67724, we allow MCUPM to access secure registers and set the > Line too long. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d9809f6e84b8d10bc2e6f2ea5a442e676ad3bf9 Gerrit-Change-Number: 69139 Gerrit-PatchSet: 4 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 02 Nov 2022 09:39:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

[XL] Change in coreboot[master]: mb/*/*: Remove AMD agesa family16 boards
by Elyes Haouas (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Arthur Heymans. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69113 ) Change subject: mb/*/*: Remove AMD agesa family16 boards ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43c7075fb6418a86c57c863edccbcb750f8ed402 Gerrit-Change-Number: 69113 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 02 Nov 2022 09:38:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: device/resource_allocator_v3: Drop code
by Arthur Heymans (Code Review) 02 Nov '22

02 Nov '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69140 ) Change subject: device/resource_allocator_v3: Drop code ...................................................................... device/resource_allocator_v3: Drop code No platform uses this anymore. Change-Id: Ifccb59ae45daa8fec41a9a2d46c628ff24a0c998 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/device/Kconfig M src/device/Makefile.inc D src/device/resource_allocator_v3.c 3 files changed, 13 insertions(+), 564 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/69140/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index c0ba3d1..88ba6ad 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -699,7 +699,6 @@ config PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G bool - depends on RESOURCE_ALLOCATOR_V4 default y if !PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G default n help @@ -922,28 +921,9 @@ maximum time a device could stretch clock bits before the transfer is aborted and an error returned. -config RESOURCE_ALLOCATOR_V3 - bool - default n - help - This config option enables resource allocator v3 which performs - top down allocation of resources in a single MMIO window. This is the - old resource allocator meant to be used only until the broken AMD - chipsets are fixed. DO NOT USE THIS FOR ANY NEW CHIPSETS! - -config RESOURCE_ALLOCATOR_V4 - bool - default n if RESOURCE_ALLOCATOR_V3 - default y if !RESOURCE_ALLOCATOR_V3 - help - This config option enables resource allocator v4 which uses multiple - ranges for allocating resources. This allows allocation of resources - above 4G boundary as well. - config RESOURCE_ALLOCATION_TOP_DOWN bool "Allocate resources from top down" default n - depends on RESOURCE_ALLOCATOR_V4 help Should be the default, but many platforms don't report resources correctly. Hence, the allocator might cause conflicts. diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 808648d..28acd73 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -59,8 +59,7 @@ ramstage-y += mmio.c ramstage-y += resource_allocator_common.c -ramstage-$(CONFIG_RESOURCE_ALLOCATOR_V3) += resource_allocator_v3.c -ramstage-$(CONFIG_RESOURCE_ALLOCATOR_V4) += resource_allocator_v4.c +ramstage-y += resource_allocator_v4.c ramstage-$(CONFIG_XHCI_UTILS) += xhci.c diff --git a/src/device/resource_allocator_v3.c b/src/device/resource_allocator_v3.c deleted file mode 100644 index 236e149..0000000 --- a/src/device/resource_allocator_v3.c +++ /dev/null @@ -1,542 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <device/device.h> -#include <post.h> - -/** - * Round a number up to an alignment. - * - * @param val The starting value. - * @param pow Alignment as a power of two. - * @return Rounded up number. - */ -static resource_t round(resource_t val, unsigned long pow) -{ - resource_t mask; - mask = (1ULL << pow) - 1ULL; - val += mask; - val &= ~mask; - return val; -} - -static const char *resource2str(struct resource *res) -{ - if (res->flags & IORESOURCE_IO) - return "io"; - if (res->flags & IORESOURCE_PREFETCH) - return "prefmem"; - if (res->flags & IORESOURCE_MEM) - return "mem"; - return "undefined"; -} - -/** - * This function is the guts of the resource allocator. - * - * The problem. - * - Allocate resource locations for every device. - * - Don't overlap, and follow the rules of bridges. - * - Don't overlap with resources in fixed locations. - * - Be efficient so we don't have ugly strategies. - * - * The strategy. - * - Devices that have fixed addresses are the minority so don't - * worry about them too much. Instead only use part of the address - * space for devices with programmable addresses. This easily handles - * everything except bridges. - * - * - PCI devices are required to have their sizes and their alignments - * equal. In this case an optimal solution to the packing problem - * exists. Allocate all devices from highest alignment to least - * alignment or vice versa. Use this. - * - * - So we can handle more than PCI run two allocation passes on bridges. The - * first to see how large the resources are behind the bridge, and what - * their alignment requirements are. The second to assign a safe address to - * the devices behind the bridge. This allows us to treat a bridge as just - * a device with a couple of resources, and not need to special case it in - * the allocator. Also this allows handling of other types of bridges. - * - * @param bus The bus we are traversing. - * @param bridge The bridge resource which must contain the bus' resources. - * @param type_mask This value gets ANDed with the resource type. - * @param type This value must match the result of the AND. - * @return TODO - */ -static void compute_resources(struct bus *bus, struct resource *bridge, - unsigned long type_mask, unsigned long type) -{ - const struct device *dev; - struct resource *resource; - resource_t base; - base = round(bridge->base, bridge->align); - - if (!bus) - return; - - printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d" - " limit: %llx\n", dev_path(bus->dev), resource2str(bridge), - base, bridge->size, bridge->align, - bridge->gran, bridge->limit); - - /* For each child which is a bridge, compute the resource needs. */ - for (dev = bus->children; dev; dev = dev->sibling) { - struct resource *child_bridge; - - if (!dev->link_list) - continue; - - /* Find the resources with matching type flags. */ - for (child_bridge = dev->resource_list; child_bridge; - child_bridge = child_bridge->next) { - struct bus* link; - - if (!(child_bridge->flags & IORESOURCE_BRIDGE) - || (child_bridge->flags & type_mask) != type) - continue; - - /* - * Split prefetchable memory if combined. Many domains - * use the same address space for prefetchable memory - * and non-prefetchable memory. Bridges below them need - * it separated. Add the PREFETCH flag to the type_mask - * and type. - */ - link = dev->link_list; - while (link && link->link_num != - IOINDEX_LINK(child_bridge->index)) - link = link->next; - - if (link == NULL) { - printk(BIOS_ERR, "link %ld not found on %s\n", - IOINDEX_LINK(child_bridge->index), - dev_path(dev)); - } - - compute_resources(link, child_bridge, - type_mask | IORESOURCE_PREFETCH, - type | (child_bridge->flags & - IORESOURCE_PREFETCH)); - } - } - - /* Remember we haven't found anything yet. */ - resource = NULL; - - /* - * Walk through all the resources on the current bus and compute the - * amount of address space taken by them. Take granularity and - * alignment into account. - */ - while ((dev = largest_resource(bus, &resource, type_mask, type))) { - - /* Size 0 resources can be skipped. */ - if (!resource->size) - continue; - - /* Propagate the resource alignment to the bridge resource. */ - if (resource->align > bridge->align) - bridge->align = resource->align; - - /* Propagate the resource limit to the bridge register. */ - if (bridge->limit > resource->limit) - bridge->limit = resource->limit; - - /* Warn if it looks like APICs aren't declared. */ - if ((resource->limit == 0xffffffff) && - (resource->flags & IORESOURCE_ASSIGNED)) { - printk(BIOS_ERR, - "Resource limit looks wrong! (no APIC?)\n"); - printk(BIOS_ERR, "%s %02lx limit %08llx\n", - dev_path(dev), resource->index, resource->limit); - } - - if (resource->flags & IORESOURCE_IO) { - /* - * Don't allow potential aliases over the legacy PCI - * expansion card addresses. The legacy PCI decodes - * only 10 bits, uses 0x100 - 0x3ff. Therefore, only - * 0x00 - 0xff can be used out of each 0x400 block of - * I/O space. - */ - if ((base & 0x300) != 0) { - base = (base & ~0x3ff) + 0x400; - } - /* - * Don't allow allocations in the VGA I/O range. - * PCI has special cases for that. - */ - else if ((base >= 0x3b0) && (base <= 0x3df)) { - base = 0x3e0; - } - } - /* Base must be aligned. */ - base = round(base, resource->align); - resource->base = base; - base += resource->size; - - printk(BIOS_SPEW, "%s %02lx * [0x%llx - 0x%llx] %s\n", - dev_path(dev), resource->index, resource->base, - resource->base + resource->size - 1, - resource2str(resource)); - } - - /* - * A PCI bridge resource does not need to be a power of two size, but - * it does have a minimum granularity. Round the size up to that - * minimum granularity so we know not to place something else at an - * address positively decoded by the bridge. - */ - bridge->size = round(base, bridge->gran) - - round(bridge->base, bridge->align); - - printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d" - " limit: %llx done\n", dev_path(bus->dev), - resource2str(bridge), - base, bridge->size, bridge->align, bridge->gran, bridge->limit); -} - -/** - * This function is the second part of the resource allocator. - * - * See the compute_resources function for a more detailed explanation. - * - * This function assigns the resources a value. - * - * @param bus The bus we are traversing. - * @param bridge The bridge resource which must contain the bus' resources. - * @param type_mask This value gets ANDed with the resource type. - * @param type This value must match the result of the AND. - * - * @see compute_resources - */ -static void __allocate_resources(struct bus *bus, struct resource *bridge, - unsigned long type_mask, unsigned long type) -{ - const struct device *dev; - struct resource *resource; - resource_t base; - base = bridge->base; - - if (!bus) - return; - - printk(BIOS_SPEW, "%s %s: base:%llx size:%llx align:%d gran:%d " - "limit:%llx\n", dev_path(bus->dev), - resource2str(bridge), - base, bridge->size, bridge->align, bridge->gran, bridge->limit); - - /* Remember we haven't found anything yet. */ - resource = NULL; - - /* - * Walk through all the resources on the current bus and allocate them - * address space. - */ - while ((dev = largest_resource(bus, &resource, type_mask, type))) { - - /* Propagate the bridge limit to the resource register. */ - if (resource->limit > bridge->limit) - resource->limit = bridge->limit; - - /* Size 0 resources can be skipped. */ - if (!resource->size) - continue; - - if (resource->flags & IORESOURCE_IO) { - /* - * Don't allow potential aliases over the legacy PCI - * expansion card addresses. The legacy PCI decodes - * only 10 bits, uses 0x100 - 0x3ff. Therefore, only - * 0x00 - 0xff can be used out of each 0x400 block of - * I/O space. - */ - if ((base & 0x300) != 0) { - base = (base & ~0x3ff) + 0x400; - } - /* - * Don't allow allocations in the VGA I/O range. - * PCI has special cases for that. - */ - else if ((base >= 0x3b0) && (base <= 0x3df)) { - base = 0x3e0; - } - } - - if ((round(base, resource->align) + resource->size - 1) <= - resource->limit) { - /* Base must be aligned. */ - base = round(base, resource->align); - resource->base = base; - resource->limit = resource->base + resource->size - 1; - resource->flags |= IORESOURCE_ASSIGNED; - resource->flags &= ~IORESOURCE_STORED; - base += resource->size; - } else { - printk(BIOS_ERR, "!! Resource didn't fit !!\n"); - printk(BIOS_ERR, " aligned base %llx size %llx " - "limit %llx\n", round(base, resource->align), - resource->size, resource->limit); - printk(BIOS_ERR, " %llx needs to be <= %llx " - "(limit)\n", (round(base, resource->align) + - resource->size) - 1, resource->limit); - printk(BIOS_ERR, " %s%s %02lx * [0x%llx - 0x%llx]" - " %s\n", (resource->flags & IORESOURCE_ASSIGNED) - ? "Assigned: " : "", dev_path(dev), - resource->index, resource->base, - resource->base + resource->size - 1, - resource2str(resource)); - } - - printk(BIOS_SPEW, "%s %02lx * [0x%llx - 0x%llx] %s\n", - dev_path(dev), resource->index, resource->base, - resource->size ? resource->base + resource->size - 1 : - resource->base, resource2str(resource)); - } - - /* - * A PCI bridge resource does not need to be a power of two size, but - * it does have a minimum granularity. Round the size up to that - * minimum granularity so we know not to place something else at an - * address positively decoded by the bridge. - */ - - bridge->flags |= IORESOURCE_ASSIGNED; - - printk(BIOS_SPEW, "%s %s: next_base: %llx size: %llx align: %d " - "gran: %d done\n", dev_path(bus->dev), - resource2str(bridge), base, bridge->size, bridge->align, - bridge->gran); - - /* For each child which is a bridge, __allocate_resources. */ - for (dev = bus->children; dev; dev = dev->sibling) { - struct resource *child_bridge; - - if (!dev->link_list) - continue; - - /* Find the resources with matching type flags. */ - for (child_bridge = dev->resource_list; child_bridge; - child_bridge = child_bridge->next) { - struct bus* link; - - if (!(child_bridge->flags & IORESOURCE_BRIDGE) || - (child_bridge->flags & type_mask) != type) - continue; - - /* - * Split prefetchable memory if combined. Many domains - * use the same address space for prefetchable memory - * and non-prefetchable memory. Bridges below them need - * it separated. Add the PREFETCH flag to the type_mask - * and type. - */ - link = dev->link_list; - while (link && link->link_num != - IOINDEX_LINK(child_bridge->index)) - link = link->next; - if (link == NULL) - printk(BIOS_ERR, "link %ld not found on %s\n", - IOINDEX_LINK(child_bridge->index), - dev_path(dev)); - - __allocate_resources(link, child_bridge, - type_mask | IORESOURCE_PREFETCH, - type | (child_bridge->flags & - IORESOURCE_PREFETCH)); - } - } -} - -static int resource_is(struct resource *res, u32 type) -{ - return (res->flags & IORESOURCE_TYPE_MASK) == type; -} - -struct constraints { - struct resource io, mem; -}; - -static struct resource *resource_limit(struct constraints *limits, - struct resource *res) -{ - struct resource *lim = NULL; - - /* MEM, or I/O - skip any others. */ - if (resource_is(res, IORESOURCE_MEM)) - lim = &limits->mem; - else if (resource_is(res, IORESOURCE_IO)) - lim = &limits->io; - - return lim; -} - -static void constrain_resources(const struct device *dev, - struct constraints* limits) -{ - const struct device *child; - struct resource *res; - struct resource *lim; - struct bus *link; - - /* Constrain limits based on the fixed resources of this device. */ - for (res = dev->resource_list; res; res = res->next) { - if (!(res->flags & IORESOURCE_FIXED)) - continue; - if (!res->size) { - /* It makes no sense to have 0-sized, fixed resources.*/ - printk(BIOS_ERR, "skipping %s@%lx fixed resource, " - "size=0!\n", dev_path(dev), res->index); - continue; - } - - lim = resource_limit(limits, res); - if (!lim) - continue; - - /* - * Is it a fixed resource outside the current known region? - * If so, we don't have to consider it - it will be handled - * correctly and doesn't affect current region's limits. - */ - if (((res->base + res->size -1) < lim->base) - || (res->base > lim->limit)) - continue; - - printk(BIOS_SPEW, "%s: %s %02lx base %08llx limit %08llx %s (fixed)\n", - __func__, dev_path(dev), res->index, res->base, - res->base + res->size - 1, resource2str(res)); - - /* - * Choose to be above or below fixed resources. This check is - * signed so that "negative" amounts of space are handled - * correctly. - */ - if ((signed long long)(lim->limit - (res->base + res->size -1)) - > (signed long long)(res->base - lim->base)) - lim->base = res->base + res->size; - else - lim->limit = res->base -1; - } - - /* Descend into every enabled child and look for fixed resources. */ - for (link = dev->link_list; link; link = link->next) { - for (child = link->children; child; child = child->sibling) { - if (child->enabled) - constrain_resources(child, limits); - } - } -} - -static void avoid_fixed_resources(const struct device *dev) -{ - struct constraints limits; - struct resource *res; - struct resource *lim; - - printk(BIOS_SPEW, "%s: %s\n", __func__, dev_path(dev)); - - /* Initialize constraints to maximum size. */ - limits.io.base = 0; - limits.io.limit = 0xffffffffffffffffULL; - limits.mem.base = 0; - limits.mem.limit = 0xffffffffffffffffULL; - - /* Constrain the limits to dev's initial resources. */ - for (res = dev->resource_list; res; res = res->next) { - if ((res->flags & IORESOURCE_FIXED)) - continue; - printk(BIOS_SPEW, "%s:@%s %02lx limit %08llx\n", __func__, - dev_path(dev), res->index, res->limit); - - lim = resource_limit(&limits, res); - if (!lim) - continue; - - if (res->base > lim->base) - lim->base = res->base; - if (res->limit < lim->limit) - lim->limit = res->limit; - } - - /* Look through the tree for fixed resources and update the limits. */ - constrain_resources(dev, &limits); - - /* Update dev's resources with new limits. */ - for (res = dev->resource_list; res; res = res->next) { - if ((res->flags & IORESOURCE_FIXED)) - continue; - - lim = resource_limit(&limits, res); - if (!lim) - continue; - - /* Is the resource outside the limits? */ - if (lim->base > res->base) - res->base = lim->base; - if (res->limit > lim->limit) - res->limit = lim->limit; - - /* MEM resources need to start at the highest address manageable. */ - if (res->flags & IORESOURCE_MEM) - res->base = resource_max(res); - - printk(BIOS_SPEW, "%s:@%s %02lx base %08llx limit %08llx\n", - __func__, dev_path(dev), res->index, res->base, res->limit); - } -} - -void allocate_resources(const struct device *root) -{ - struct resource *res; - const struct device *child; - - /* Compute resources for all domains. */ - for (child = root->link_list->children; child; child = child->sibling) { - if (!(child->path.type == DEVICE_PATH_DOMAIN)) - continue; - post_log_path(child); - for (res = child->resource_list; res; res = res->next) { - if (res->flags & IORESOURCE_FIXED) - continue; - if (res->flags & IORESOURCE_MEM) { - compute_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_MEM); - continue; - } - if (res->flags & IORESOURCE_IO) { - compute_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_IO); - continue; - } - } - } - - /* For all domains. */ - for (child = root->link_list->children; child; child=child->sibling) - if (child->path.type == DEVICE_PATH_DOMAIN) - avoid_fixed_resources(child); - - /* Store the computed resource allocations into device registers ... */ - printk(BIOS_INFO, "Setting resources...\n"); - for (child = root->link_list->children; child; child = child->sibling) { - if (!(child->path.type == DEVICE_PATH_DOMAIN)) - continue; - post_log_path(child); - for (res = child->resource_list; res; res = res->next) { - if (res->flags & IORESOURCE_FIXED) - continue; - if (res->flags & IORESOURCE_MEM) { - __allocate_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_MEM); - continue; - } - if (res->flags & IORESOURCE_IO) { - __allocate_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_IO); - continue; - } - } - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/69140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifccb59ae45daa8fec41a9a2d46c628ff24a0c998 Gerrit-Change-Number: 69140 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: soc/mediatek/mt8188: Disable input-gating for big-core SRAM
by Liju-Clr Chen (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Liju-Clr Chen, Rex-BC Chen, Yu-Ping Wu, Yidi Lin. Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69089 to look at the new patch set (#9). Change subject: soc/mediatek/mt8188: Disable input-gating for big-core SRAM ...................................................................... soc/mediatek/mt8188: Disable input-gating for big-core SRAM The input-gating is an experimental feature (but unfortunately default enabled) and would lead to crash on MT8188, so we have to disable it in the firmware stage. BUG=b:233720142 TEST=CPUfreq in kernel test pass. Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com> --- M src/soc/mediatek/mt8188/Makefile.inc A src/soc/mediatek/mt8188/cpu_inputgating.c A src/soc/mediatek/mt8188/include/soc/cpu_inputgating.h M src/soc/mediatek/mt8188/soc.c 4 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/69089/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/69089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca Gerrit-Change-Number: 69089 Gerrit-PatchSet: 9 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver
by Liju-Clr Chen (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Liju-Clr Chen, Paul Menzel, Rex-BC Chen. Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69088 to look at the new patch set (#9). Change subject: soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver ...................................................................... soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver When enabling cpufreq-hw driver, it is required for MCUPM to access secure register. Therefore, we enable sideband to allow MCUPM to access the secure registers. BUG=b:236331463 TEST=It works well after boot to login shell. Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6 Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com> --- M src/soc/mediatek/mt8188/devapc.c M src/soc/mediatek/mt8188/include/soc/devapc.h 2 files changed, 23 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/69088/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/69088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6 Gerrit-Change-Number: 69088 Gerrit-PatchSet: 9 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: Revert "soc/mediatek/mt8188: Allow CPUfreq hardware to access MCUPM r...
by Liju-Clr Chen (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Hung-Te Lin, Liju-Clr Chen, Rex-BC Chen. Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69139 to look at the new patch set (#4). Change subject: Revert "soc/mediatek/mt8188: Allow CPUfreq hardware to access MCUPM registers" ...................................................................... Revert "soc/mediatek/mt8188: Allow CPUfreq hardware to access MCUPM registers" This reverts commit a8172c329fe309f3b5b409c1a59a227186400dd4. In the patch CB:67724, we allow MCUPM to access secure registers and set the domain to DOMAIN_2. Additional attribute settings are also required when a hardware is set to a specific domain. Otherwise, there would be violation between hardware. Since MT8188 is in bring-up stage, we simply enable access register permission for the DOMAIN_0 by default. So remove the wrong setting for MCUPM, SCP and SSPM. We will complete DEVAPC setting when the settings are confirmed. Change-Id: I5d9809f6e84b8d10bc2e6f2ea5a442e676ad3bf9 Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com> --- M src/soc/mediatek/mt8188/devapc.c M src/soc/mediatek/mt8188/include/soc/devapc.h 2 files changed, 23 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/69139/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/69139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d9809f6e84b8d10bc2e6f2ea5a442e676ad3bf9 Gerrit-Change-Number: 69139 Gerrit-PatchSet: 4 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: Revert "soc/mediatek/mt8188: Allow CPUfreq hardware to access MCUPM r...
by Yu-Ping Wu (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Hung-Te Lin, Liju-Clr Chen, Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69139 ) Change subject: Revert "soc/mediatek/mt8188: Allow CPUfreq hardware to access MCUPM registers" ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69139/comment/dea63649_0d5ab004 PS3, Line 11: In the patch CB:67724, we allow MCUPM to access secure registers and set the Line too long. -- To view, visit https://review.coreboot.org/c/coreboot/+/69139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d9809f6e84b8d10bc2e6f2ea5a442e676ad3bf9 Gerrit-Change-Number: 69139 Gerrit-PatchSet: 3 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Comment-Date: Wed, 02 Nov 2022 09:35:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XL] Change in coreboot[master]: mb/aopen/dxplplusu: Remove board
by Arthur Heymans (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Kyösti Mälkki, Elyes Haouas, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69114 ) Change subject: mb/aopen/dxplplusu: Remove board ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > Should we keep src/cpu/intel/model_f2x ? > it is used only for socket_mPGA604 Done. -- To view, visit https://review.coreboot.org/c/coreboot/+/69114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf37ade31ddb55697df1a65062c092a0a485e175 Gerrit-Change-Number: 69114 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 02 Nov 2022 09:34:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

1 0

[XL] Change in coreboot[master]: mb/aopen/dxplplusu: Remove board
by Arthur Heymans (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Kyösti Mälkki, Elyes Haouas, Felix Held. Hello build bot (Jenkins), Kyösti Mälkki, Elyes Haouas, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69114 to look at the new patch set (#5). Change subject: mb/aopen/dxplplusu: Remove board ...................................................................... mb/aopen/dxplplusu: Remove board This board use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: Idf37ade31ddb55697df1a65062c092a0a485e175 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/smbios.c M src/cpu/intel/Kconfig M src/cpu/intel/Makefile.inc D src/cpu/intel/model_f2x/Kconfig D src/cpu/intel/model_f2x/Makefile.inc D src/cpu/intel/model_f2x/model_f2x_init.c D src/cpu/intel/socket_mPGA604/Kconfig D src/cpu/intel/socket_mPGA604/Makefile.inc M src/cpu/x86/Kconfig M src/cpu/x86/smm/smmrelocate.S D src/mainboard/aopen/Kconfig D src/mainboard/aopen/Kconfig.name D src/mainboard/aopen/dxplplusu/Kconfig D src/mainboard/aopen/dxplplusu/Kconfig.name D src/mainboard/aopen/dxplplusu/Makefile.inc D src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl D src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl D src/mainboard/aopen/dxplplusu/acpi/i82801db.asl D src/mainboard/aopen/dxplplusu/acpi/p64h2.asl D src/mainboard/aopen/dxplplusu/acpi/power.asl D src/mainboard/aopen/dxplplusu/acpi/scsi.asl D src/mainboard/aopen/dxplplusu/acpi/superio.asl D src/mainboard/aopen/dxplplusu/acpi_tables.c D src/mainboard/aopen/dxplplusu/board_info.txt D src/mainboard/aopen/dxplplusu/bootblock.c D src/mainboard/aopen/dxplplusu/devicetree.cb D src/mainboard/aopen/dxplplusu/dsdt.asl D src/northbridge/intel/e7505/Kconfig D src/northbridge/intel/e7505/Makefile.inc D src/northbridge/intel/e7505/e7505.h D src/northbridge/intel/e7505/memmap.c D src/northbridge/intel/e7505/northbridge.c D src/northbridge/intel/e7505/raminit.c D src/northbridge/intel/e7505/raminit.h D src/northbridge/intel/e7505/romstage.c M src/southbridge/intel/common/smbus.c D src/southbridge/intel/i82801dx/Kconfig D src/southbridge/intel/i82801dx/Makefile.inc D src/southbridge/intel/i82801dx/ac97.c D src/southbridge/intel/i82801dx/bootblock.c D src/southbridge/intel/i82801dx/chip.h D src/southbridge/intel/i82801dx/early_smbus.c D src/southbridge/intel/i82801dx/fadt.c D src/southbridge/intel/i82801dx/i82801dx.c D src/southbridge/intel/i82801dx/i82801dx.h D src/southbridge/intel/i82801dx/ide.c D src/southbridge/intel/i82801dx/lpc.c D src/southbridge/intel/i82801dx/pci.c D src/southbridge/intel/i82801dx/smi.c D src/southbridge/intel/i82801dx/smihandler.c D src/southbridge/intel/i82801dx/usb.c D src/southbridge/intel/i82801dx/usb2.c D src/southbridge/intel/i82870/82870.h D src/southbridge/intel/i82870/Kconfig D src/southbridge/intel/i82870/Makefile.inc D src/southbridge/intel/i82870/ioapic.c D src/southbridge/intel/i82870/pcibridge.c M src/superio/smsc/Makefile.inc D src/superio/smsc/lpc47m10x/Kconfig D src/superio/smsc/lpc47m10x/Makefile.inc D src/superio/smsc/lpc47m10x/early_serial.c D src/superio/smsc/lpc47m10x/lpc47m10x.h D src/superio/smsc/lpc47m10x/superio.c 63 files changed, 16 insertions(+), 5,323 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/69114/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/69114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf37ade31ddb55697df1a65062c092a0a485e175 Gerrit-Change-Number: 69114 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2022