Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68854 )
Change subject: mb/google/rex: Disable TBT PCIe rp1 and rp3 root ports
......................................................................
mb/google/rex: Disable TBT PCIe rp1 and rp3 root ports
Rex board only uses TBT PCIe root ports 0 and 2. This change disables
rp1 and rp3 root ports.
BUG=b:254207628
TEST=Booted to OS and verified rp1 and rp3 root ports were disabled.
Change-Id: Ia5c1d657c0ad0482619d739f8949bc9168eac25b
Signed-off-by: zhaojohn <john.zhao(a)intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68854
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli(a)google.com>
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
---
M src/mainboard/google/rex/variants/rex0/overridetree.cb
1 file changed, 22 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
Eric Lai: Looks good to me, approved
Tarun Tuli: Looks good to me, approved
Kapil Porwal: Looks good to me, approved
diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb
index 2e1c159..c14077b 100644
--- a/src/mainboard/google/rex/variants/rex0/overridetree.cb
+++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb
@@ -136,9 +136,7 @@
}"
end #PCIE11 SD card
device ref tbt_pcie_rp0 on end
- device ref tbt_pcie_rp1 on end
device ref tbt_pcie_rp2 on end
- device ref tbt_pcie_rp3 on end
device ref tcss_xhci on
chip drivers/usb/acpi
device ref tcss_root_hub on
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Saurabh Mishra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69107 )
Change subject: vc/intel/fsp: Update JSL FSP headers from v2385.04 to v4155.00
......................................................................
Patch Set 4:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69107/comment/32c2997c_d8e42a88
PS3, Line 7: vc/intel/fsp:Update JSL FSP headers from v2385.04 to v4155.00
> Please add a space after the colon.
Done
https://review.coreboot.org/c/coreboot/+/69107/comment/d73e3caa_5be06d6d
PS3, Line 10: Previous FSP version was v2385.04
> 1. Please add a dot/period at the end of sentences. […]
Done
https://review.coreboot.org/c/coreboot/+/69107/comment/0cae6aef_ac06266a
PS3, Line 11: Include
> include
Done
https://review.coreboot.org/c/coreboot/+/69107/comment/34e7735e_2849555a
PS3, Line 11: Changes Include:
> Please add a blank line above.
Done
https://review.coreboot.org/c/coreboot/+/69107/comment/29ed39c1_8bf0db65
PS3, Line 12: FspsUpd.h: Change in header offset.
: {FspmUpd.h,FspUpd.h}: Copyright year update.
: MemInfoHob.h: Add HOB_GUID_TYPE, HOB_GENERIC_HEADER Struct.
> Plesae format this as a list.
Done
https://review.coreboot.org/c/coreboot/+/69107/comment/3bb544b9_44db402a
PS3, Line 15:
> Please add a note, why the big version jump 2385 to 4155 only has such a few changes.
Hi Paul, FSP Headers changes are pushed for IPU based JSL FSP i.e. FSP v4155.00.
There has been a 8Bytes of addition in FSPS Struct.
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Hello build bot (Jenkins), Saurabh Mishra,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69107
to look at the new patch set (#4).
Change subject: vc/intel/fsp: Update JSL FSP headers from v2385.04 to v4155.00
......................................................................
vc/intel/fsp: Update JSL FSP headers from v2385.04 to v4155.00
The headers added are generated as per FSP v4155.00. Previous headers were
generated from FSP version v2385.04.
Changes include:
1. FspsUpd.h:
- Change in header offset.
2. {FspmUpd.h,FspUpd.h}:
- Copyright year update.
3. MemInfoHob.h:
- Add HOB_GUID_TYPE, HOB_GENERIC_HEADER Struct.
BUG=b:TBD
BRANCH=firmware-dedede-13606.B
TEST=Build and boot JSLRVP
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com>
Change-Id: Ic4fae89d8d7fbbcb0448222d39dd829bc3f99644
---
M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspUpd.h
M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h
M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h
M src/vendorcode/intel/fsp/fsp2_0/jasperlake/MemInfoHob.h
4 files changed, 341 insertions(+), 280 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/69107/4
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Raymond Chung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69137 )
Change subject: mb/google/brya/gaelin: Configure devicetree settings
......................................................................
Patch Set 2: Code-Review+1
This change is ready for review.
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Change subject: mb/google/brya/gaelin: Configure GPIO settings
......................................................................
Patch Set 1: Code-Review+1
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Change subject: soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver
......................................................................
Patch Set 4: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69088/comment/35dc18c3_108526e3
PS4, Line 15: Since MT8188 is in bring-up stage, we simply remove the domain setting
A blank line between paragraphs.
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Change subject: mb/google/brya/variants/crota:: Configure TDC current for VR domains.
......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69135/comment/e2e3a875_7229764e
PS7, Line 7: :
extra : still here
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Change subject: mb/google/brya/variants/crota:: Configure TDC current for VR domains.
......................................................................
Patch Set 7:
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PS6, Line 7: :
> please remove extra :
Done
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