Attention is currently required from: Shelley Chen, Venkat Thogaru.
Sudheer Amrabadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67673 )
Change subject: soc/qualcomm/sc7280: Move AOP load and reset handle to Romstage
......................................................................
Patch Set 18:
(4 comments)
Patchset:
PS3:
> Can you also mention in the commit message how much time is saved and on what devices you took measu […]
Ack
Patchset:
PS18:
Able to apply changes as per the review comments suggested. Can you please review once.
File src/mainboard/google/herobrine/romstage.c:
https://review.coreboot.org/c/coreboot/+/67673/comment/a761291c_2c2bc5c1
PS3, Line 4: #include <console/console.h>
> okay sure will revert these include lines
Ack
https://review.coreboot.org/c/coreboot/+/67673/comment/f25ba104_6919d9f6
PS3, Line 30: printk(BIOS_INFO, "About to call aop_fw_load_reset\n");
> okay sure will revert these printk statements.
Ack
--
To view, visit https://review.coreboot.org/c/coreboot/+/67673
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iabc8ee8f6e7b14d237b0aeaae42da8077f9dafc4
Gerrit-Change-Number: 67673
Gerrit-PatchSet: 18
Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org>
Gerrit-Reviewer: Shelley Chen <shchen(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: T.Michael Turney <tmiketurney(a)gmail.com>
Gerrit-Attention: Shelley Chen <shchen(a)google.com>
Gerrit-Attention: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com>
Gerrit-Comment-Date: Wed, 02 Nov 2022 08:49:12 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Shelley Chen <shchen(a)google.com>
Comment-In-Reply-To: Sudheer Amrabadi <samrabad(a)codeaurora.org>
Gerrit-MessageType: comment
Attention is currently required from: Arthur Heymans.
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69119
to look at the new patch set (#10).
Change subject: nb/amd/agesa: Remove leftover code
......................................................................
nb/amd/agesa: Remove leftover code
This code is now unused by any platform.
Change-Id: I5464daa8cfb8231e2b19447c343fc80ab1d68ce8
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
D src/northbridge/amd/agesa/BiosCallOuts.h
D src/northbridge/amd/agesa/Kconfig
D src/northbridge/amd/agesa/Makefile.inc
D src/northbridge/amd/agesa/dimmSpd.h
D src/northbridge/amd/agesa/state_machine.h
5 files changed, 12 insertions(+), 189 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/69119/10
--
To view, visit https://review.coreboot.org/c/coreboot/+/69119
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5464daa8cfb8231e2b19447c343fc80ab1d68ce8
Gerrit-Change-Number: 69119
Gerrit-PatchSet: 10
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newpatchset
Attention is currently required from: Arthur Heymans.
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69120
to look at the new patch set (#9).
Change subject: sb/amd: Remove dropped platforms
......................................................................
sb/amd: Remove dropped platforms
This code is now unused by any platform.
Change-Id: I60afbde6ead70f0c887866fc351b4a6a15a89287
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/drivers/amd/agesa/state_machine.c
D src/southbridge/amd/agesa/Kconfig
D src/southbridge/amd/agesa/Makefile.inc
D src/southbridge/amd/agesa/hudson/Kconfig
D src/southbridge/amd/agesa/hudson/Makefile.inc
D src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl
D src/southbridge/amd/agesa/hudson/acpi/audio.asl
D src/southbridge/amd/agesa/hudson/acpi/fch.asl
D src/southbridge/amd/agesa/hudson/acpi/lpc.asl
D src/southbridge/amd/agesa/hudson/acpi/pci_int.asl
D src/southbridge/amd/agesa/hudson/acpi/pcie.asl
D src/southbridge/amd/agesa/hudson/acpi/smbus.asl
D src/southbridge/amd/agesa/hudson/acpi/usb.asl
D src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h
D src/southbridge/amd/agesa/hudson/amd_pci_int_types.h
D src/southbridge/amd/agesa/hudson/bootblock.c
D src/southbridge/amd/agesa/hudson/chip.h
D src/southbridge/amd/agesa/hudson/early_setup.c
D src/southbridge/amd/agesa/hudson/enable_usbdebug.c
D src/southbridge/amd/agesa/hudson/fadt.c
D src/southbridge/amd/agesa/hudson/hda.c
D src/southbridge/amd/agesa/hudson/hudson.c
D src/southbridge/amd/agesa/hudson/hudson.h
D src/southbridge/amd/agesa/hudson/ide.c
D src/southbridge/amd/agesa/hudson/imc.c
D src/southbridge/amd/agesa/hudson/imc.h
D src/southbridge/amd/agesa/hudson/lpc.c
D src/southbridge/amd/agesa/hudson/pci.c
D src/southbridge/amd/agesa/hudson/pci_devs.h
D src/southbridge/amd/agesa/hudson/pcie.c
D src/southbridge/amd/agesa/hudson/ramtop.c
D src/southbridge/amd/agesa/hudson/reset.c
D src/southbridge/amd/agesa/hudson/resume.c
D src/southbridge/amd/agesa/hudson/sata.c
D src/southbridge/amd/agesa/hudson/sd.c
D src/southbridge/amd/agesa/hudson/sm.c
D src/southbridge/amd/agesa/hudson/smbus.c
D src/southbridge/amd/agesa/hudson/smbus.h
D src/southbridge/amd/agesa/hudson/smbus_spd.c
D src/southbridge/amd/agesa/hudson/smi.c
D src/southbridge/amd/agesa/hudson/smi.h
D src/southbridge/amd/agesa/hudson/smi_util.c
D src/southbridge/amd/agesa/hudson/smihandler.c
D src/southbridge/amd/agesa/hudson/spi.c
D src/southbridge/amd/agesa/hudson/usb.c
D src/southbridge/amd/cimx/Kconfig
D src/southbridge/amd/cimx/Makefile.inc
D src/southbridge/amd/cimx/sb800/Amd.h
D src/southbridge/amd/cimx/sb800/AmdSbLib.h
D src/southbridge/amd/cimx/sb800/Kconfig
D src/southbridge/amd/cimx/sb800/Makefile.inc
D src/southbridge/amd/cimx/sb800/SBPLATFORM.h
D src/southbridge/amd/cimx/sb800/acpi/audio.asl
D src/southbridge/amd/cimx/sb800/acpi/fch.asl
D src/southbridge/amd/cimx/sb800/acpi/lpc.asl
D src/southbridge/amd/cimx/sb800/acpi/misc_io.asl
D src/southbridge/amd/cimx/sb800/acpi/pcie.asl
D src/southbridge/amd/cimx/sb800/acpi/smbus.asl
D src/southbridge/amd/cimx/sb800/acpi/usb.asl
D src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h
D src/southbridge/amd/cimx/sb800/amd_pci_int_types.h
D src/southbridge/amd/cimx/sb800/bootblock.c
D src/southbridge/amd/cimx/sb800/cfg.c
D src/southbridge/amd/cimx/sb800/cfg.h
D src/southbridge/amd/cimx/sb800/chip.h
D src/southbridge/amd/cimx/sb800/early.c
D src/southbridge/amd/cimx/sb800/fadt.c
D src/southbridge/amd/cimx/sb800/fan.c
D src/southbridge/amd/cimx/sb800/fan.h
D src/southbridge/amd/cimx/sb800/gpio_oem.h
D src/southbridge/amd/cimx/sb800/late.c
D src/southbridge/amd/cimx/sb800/lpc.c
D src/southbridge/amd/cimx/sb800/lpc.h
D src/southbridge/amd/cimx/sb800/pci_devs.h
D src/southbridge/amd/cimx/sb800/ramtop.c
D src/southbridge/amd/cimx/sb800/reset.c
D src/southbridge/amd/cimx/sb800/sb_cimx.h
D src/southbridge/amd/cimx/sb800/smbus.c
D src/southbridge/amd/cimx/sb800/smbus.h
D src/southbridge/amd/cimx/sb800/smbus_spd.c
D src/southbridge/amd/cimx/sb800/smbus_spd.h
D src/southbridge/amd/cimx/sb800/spi.c
M src/southbridge/amd/common/Makefile.inc
M src/southbridge/amd/pi/hudson/acpi/fch.asl
M src/southbridge/amd/pi/hudson/hudson.c
M src/vendorcode/amd/Makefile.inc
D src/vendorcode/amd/cimx/Makefile.inc
D src/vendorcode/amd/cimx/sb800/ACPILIB.c
D src/vendorcode/amd/cimx/sb800/ACPILIB.h
D src/vendorcode/amd/cimx/sb800/AMDLIB.c
D src/vendorcode/amd/cimx/sb800/AMDSBLIB.c
D src/vendorcode/amd/cimx/sb800/AMDSBLIB.h
D src/vendorcode/amd/cimx/sb800/AZALIA.c
D src/vendorcode/amd/cimx/sb800/DISPATCHER.c
D src/vendorcode/amd/cimx/sb800/EC.c
D src/vendorcode/amd/cimx/sb800/ECLIB.c
D src/vendorcode/amd/cimx/sb800/ECfan.h
D src/vendorcode/amd/cimx/sb800/ECfanLIB.c
D src/vendorcode/amd/cimx/sb800/ECfanc.c
D src/vendorcode/amd/cimx/sb800/GEC.c
D src/vendorcode/amd/cimx/sb800/Gpp.c
D src/vendorcode/amd/cimx/sb800/IOLIB.c
D src/vendorcode/amd/cimx/sb800/LEGACY.c
D src/vendorcode/amd/cimx/sb800/MEMLIB.c
D src/vendorcode/amd/cimx/sb800/Makefile.inc
D src/vendorcode/amd/cimx/sb800/OEM.h
D src/vendorcode/amd/cimx/sb800/PCILIB.c
D src/vendorcode/amd/cimx/sb800/PMIO2LIB.c
D src/vendorcode/amd/cimx/sb800/PMIOLIB.c
D src/vendorcode/amd/cimx/sb800/SATA.c
D src/vendorcode/amd/cimx/sb800/SB800.h
D src/vendorcode/amd/cimx/sb800/SBCMN.c
D src/vendorcode/amd/cimx/sb800/SBDEF.h
D src/vendorcode/amd/cimx/sb800/SBMAIN.c
D src/vendorcode/amd/cimx/sb800/SBPELIB.c
D src/vendorcode/amd/cimx/sb800/SBPort.c
D src/vendorcode/amd/cimx/sb800/SBSUBFUN.h
D src/vendorcode/amd/cimx/sb800/SBTYPE.h
D src/vendorcode/amd/cimx/sb800/SMM.c
D src/vendorcode/amd/cimx/sb800/SbModInf.c
D src/vendorcode/amd/cimx/sb800/USB.c
121 files changed, 13 insertions(+), 19,196 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/69120/9
--
To view, visit https://review.coreboot.org/c/coreboot/+/69120
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I60afbde6ead70f0c887866fc351b4a6a15a89287
Gerrit-Change-Number: 69120
Gerrit-PatchSet: 9
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newpatchset
Attention is currently required from: Arthur Heymans.
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69118
to look at the new patch set (#9).
Change subject: cpu/amd/agesa: Remove leftover code
......................................................................
cpu/amd/agesa: Remove leftover code
Now that all agesa CPUs are removed this code is unused.
Change-Id: If0c082bbdb09457e3876962fa75725add11cb67c
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/include/arch/cpu.h
M src/cpu/amd/Kconfig
M src/cpu/amd/Makefile.inc
D src/cpu/amd/agesa/Kconfig
D src/cpu/amd/agesa/Makefile.inc
D src/cpu/amd/smm/Makefile.inc
D src/cpu/amd/smm/smm_init.c
M src/drivers/amd/agesa/Makefile.inc
M src/drivers/amd/agesa/acpi_tables.c
M src/drivers/amd/agesa/state_machine.c
M src/northbridge/amd/agesa/Kconfig
M src/vendorcode/amd/Kconfig
M src/vendorcode/amd/pi/00670F00/Makefile.inc
M src/vendorcode/amd/pi/Makefile.inc
14 files changed, 28 insertions(+), 179 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/69118/9
--
To view, visit https://review.coreboot.org/c/coreboot/+/69118
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If0c082bbdb09457e3876962fa75725add11cb67c
Gerrit-Change-Number: 69118
Gerrit-PatchSet: 9
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newpatchset
Attention is currently required from: Tarun Tuli, Ravishankar Sarawadi.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68305 )
Change subject: src/soc/intel/{common,meteorlake}: Add new Meteor Lake device ID
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68305/comment/497d7067_1d501fbe
PS2, Line 7: src/soc/intel/{common,meteorlake}: Add new Meteor Lake device ID
Maybe:
> soc/intel: Add Meteor Lake IGD device id 0x7d45
https://review.coreboot.org/c/coreboot/+/68305/comment/0b4f670b_97eca10f
PS2, Line 7: src/
Please remove.
https://review.coreboot.org/c/coreboot/+/68305/comment/d10008e3_7cd4bcd1
PS2, Line 10:
Was this id missed in the past? Anyway, just add: Reorder the macros, so the smallest id comes first.
--
To view, visit https://review.coreboot.org/c/coreboot/+/68305
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iad69f547a981390ef3749256e9fd9bcfc106fe3c
Gerrit-Change-Number: 68305
Gerrit-PatchSet: 2
Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>
Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com>
Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com>
Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>
Gerrit-Comment-Date: Wed, 02 Nov 2022 08:02:14 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment
Attention is currently required from: Arthur Heymans, Marc Jones, Wonkyu Kim, Subrata Banik, Jonathan Zhang, Johnny Lin, Daocheng Bu, Rizwan Qureshi, Jingle Hsu, Shuming Chu (Shuming), Shelly Chang.
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66579 )
Change subject: soc/intel/cmn: Clear interrupt status after HECI-1 has been received
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/66579/comment/131f084a_f32c8918
PS4, Line 15: get_me_fw_version
> For our case we call get_me_fw_version after EOP and can see this issue. […]
Thanks Johnny for clarification.
The clearing interrupt request has to be done during Host CPU RX cycle. But, coreboot reads the messages in the poll mode. So, I guess your platform might be clearing interrupt status (code @ line# 542 in this file) before the CSE has sends the message. This can happen if CSE is busy when it receives the command from Host, so it may send after few milli seconds.
To confirm this, can you please do additional test : before clearing the interrupt status @line#542, just log the intr status).BTW, remove the fix in the patch in your test. From this test, we will understand if we are clearing the interrupt status before CSE generates.
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/66579/comment/1d6af63e_630a7ab6
PS4, Line 542: clear_int();
Is this too early in your platform? Can you check interrupt status before this code clears?
--
To view, visit https://review.coreboot.org/c/coreboot/+/66579
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1cf21112870e53a11134d43e461b735ead239717
Gerrit-Change-Number: 66579
Gerrit-PatchSet: 4
Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com>
Gerrit-Reviewer: Daocheng Bu <daocheng.bu(a)intel.com>
Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com>
Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com>
Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com>
Gerrit-Reviewer: Shuming Chu (Shuming) <s1218944(a)gmail.com>
Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com>
Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com>
Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com>
Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com>
Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Gerrit-Attention: Daocheng Bu <daocheng.bu(a)intel.com>
Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Gerrit-Attention: Jingle Hsu <jingle_hsu(a)wiwynn.com>
Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com>
Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com>
Gerrit-Comment-Date: Wed, 02 Nov 2022 07:56:12 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-MessageType: comment
Attention is currently required from: Liju-Clr Chen, Paul Menzel, Rex-BC Chen.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69088 )
Change subject: soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69088/comment/6984393a_cf7db035
PS4, Line 9: previous patch
use the link to that patch, for example CB:XXXXX, or a complete review.coreboot.org URL
File src/soc/mediatek/mt8188/devapc.c:
https://review.coreboot.org/c/coreboot/+/69088/comment/1af1bbb4_c5887652
PS4, Line 1556: /* Default APC setting */
should we add a TODO before this?
/* TODO: Setup SCP, SSPM and MCUPM permissions in APC . */
--
To view, visit https://review.coreboot.org/c/coreboot/+/69088
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6
Gerrit-Change-Number: 69088
Gerrit-PatchSet: 4
Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com>
Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com>
Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Gerrit-Comment-Date: Wed, 02 Nov 2022 07:45:18 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment
Attention is currently required from: Martin L Roth, Angel Pons, Julius Werner, Martin Roth.
Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67918 )
Change subject: tests: Add option for debug symbols & no optimization
......................................................................
Patch Set 4: Code-Review+2
--
To view, visit https://review.coreboot.org/c/coreboot/+/67918
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3a644dcccb7e15473413b775da8f70617afaefce
Gerrit-Change-Number: 67918
Gerrit-PatchSet: 4
Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Julius Werner <jwerner(a)chromium.org>
Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com>
Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Attention: Julius Werner <jwerner(a)chromium.org>
Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Gerrit-Comment-Date: Wed, 02 Nov 2022 07:32:14 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment