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Change subject: soc/intel/alderlake: Hook up GMA ACPI brightness controls
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> I thought the backlight control has moved into Intel GFX driver since few generations now and we don […]
Backlight control on Windows doesn't seem to work without ACPI. Also, see https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/3PJ3…
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Change subject: mb/prodrive/atlas: Add IBECC Kconfig option
......................................................................
Patch Set 3:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68783/comment/982a85d5_3996c61e
PS2, Line 10: indurance
> *e*ndurance
Done
https://review.coreboot.org/c/coreboot/+/68783/comment/cde6d67f_adaa7784
PS2, Line 12: Test: start atlas mainboard with Linux. See in dmesg that IBECC (EDAC igen6) driver is loaded. Inject a fake error via debugfs and see in dmesg that Linux handles it.
> Please wrap at 72 characters
Done
File src/mainboard/prodrive/atlas/Kconfig:
https://review.coreboot.org/c/coreboot/+/68783/comment/b8f34591_9146724b
PS2, Line 26: indurance
> *e*ndurance
Done
https://review.coreboot.org/c/coreboot/+/68783/comment/ea001a6f_155acb9a
PS2, Line 27: not always required
> Why is it default enabled then?
My bad
File src/mainboard/prodrive/atlas/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/68783/comment/acd7d368_80d1df78
PS2, Line 50: ? true : false
> This is redundant
Done
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Hello build bot (Jenkins), Christian Walter, Angel Pons, Lean Sheng Tan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/68783
to look at the new patch set (#3).
Change subject: mb/prodrive/atlas: Add IBECC Kconfig option
......................................................................
mb/prodrive/atlas: Add IBECC Kconfig option
Add an option on Atlas to enable IBECC (In Band Error Correction Code),
which is currently needed for endurance testing.
Test: start atlas mainboard with Linux. See in dmesg that
IBECC (EDAC igen6) driver is loaded. Inject a fake error via debugfs
and see in dmesg that Linux handles it.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I71ee2401136e2dc70b3164db6c99af03a3e1f346
---
M src/mainboard/prodrive/atlas/Kconfig
M src/mainboard/prodrive/atlas/devicetree.cb
2 files changed, 27 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/68783/3
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Change subject: cbfstool/lz4: Fix compilation issue
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> > Have you tried cherry-picking CB:63936 to see if it works?
>
> yeah it works
Nice, then we can probably drop this change
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Change subject: soc/intel/alderlake: Add IBECC
......................................................................
Patch Set 7: Code-Review+1
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Change subject: soc/intel/alderlake: Add IBECC
......................................................................
Patch Set 7:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68756/comment/97eda0ba_1d710775
PS5, Line 7: src/
> Drop `src/`
Done
https://review.coreboot.org/c/coreboot/+/68756/comment/eb7c76a3_7fd14bcd
PS5, Line 7: Alderlake
> Alder Lake, but it’s redundant as it’s in the prefix.
Done
https://review.coreboot.org/c/coreboot/+/68756/comment/899e33fa_423ea5f8
PS5, Line 10: Board
> Without capitalizing `b`? +1
Done
https://review.coreboot.org/c/coreboot/+/68756/comment/1abc0aca_557fd1a9
PS5, Line 11:
> > Please elaborate. Is the FSP doing that? […]
Done
Patchset:
PS5:
> Should something be logged, when this is enabled?
Done
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/68756/comment/c00d04ae_a7535356
PS5, Line 372: !!config->ibecc.enable
> It's a `bool` already
Done
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Change subject: cbfstool/lz4: Fix compilation issue
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Have you tried cherry-picking CB:63936 to see if it works?
yeah it works
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Change subject: cpu/x86: Set up a separate stack for APs
......................................................................
Patch Set 16:
(1 comment)
File src/cpu/x86/Kconfig:
https://review.coreboot.org/c/coreboot/+/69123/comment/f89d8a8b_97098c89
PS16, Line 214: default 0x200
> Could this cause regressions? It feels quite small.
I made it comparable to the stack size for the smihandler. That should be fine.
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Change subject: nb/intel/gm45: Make polling loops more explicit
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Another commonly used way to write it is to put the ';' on the next line.
One concern with this approach is that the semicolon seems to be spurious if one doesn't take the context into account. If memory serves right, Jenkins also warns about it.
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Change subject: soc/intel/alderlake: Add IBECC
......................................................................
soc/intel/alderlake: Add IBECC
Add In Band Error Correction Code to Alderlake SOC's.
It's currently needed and tested for the Prodrive Atlas mainboard.
After enabling it in the UPD, FSP-M takes care of enabling IBECC.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I9cc2ed6defa1223aa422b9b0d8145f8f8b3dd12e
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 51 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/68756/7
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