coreboot-gerrit November 2022

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[S] Change in coreboot[master]: soc/xeon_sp: Add weak mainboard_ewl_check for EWL check after FSP-M
by Johnny Lin (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Jonathan Zhang, Christian Walter, Arthur Heymans, Tim Chu. Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69143 ) Change subject: soc/xeon_sp: Add weak mainboard_ewl_check for EWL check after FSP-M ...................................................................... soc/xeon_sp: Add weak mainboard_ewl_check for EWL check after FSP-M EWL (Enhanced Warning Log) is a FSP HOB generated by FSP-M that may contain several warnings/errors related to core, uncore and memory, etc. mainboard can override it in its romstage.c for its own Enhanced Warning Log check. Change-Id: I6f542e71d20307397c398fd757d9408438f681ed Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/soc/intel/xeon_sp/include/soc/romstage.h M src/soc/intel/xeon_sp/romstage.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/69143/1 diff --git a/src/soc/intel/xeon_sp/include/soc/romstage.h b/src/soc/intel/xeon_sp/include/soc/romstage.h index 90689af..a2adfed 100644 --- a/src/soc/intel/xeon_sp/include/soc/romstage.h +++ b/src/soc/intel/xeon_sp/include/soc/romstage.h @@ -9,4 +9,6 @@ void mainboard_memory_init_params(FSPM_UPD * mupd); void mainboard_rtc_failed(void); void save_dimm_info(void); +void mainboard_ewl_check(void); + #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index b1c7b3b..d001d61 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -15,6 +15,7 @@ fsp_memory_init(false); printk(BIOS_DEBUG, "coreboot fsp_memory_init finished...\n"); + mainboard_ewl_check(); unlock_pam_regions(); @@ -31,3 +32,4 @@ } __weak void save_dimm_info(void) { } +__weak void mainboard_ewl_check(void) { } -- To view, visit https://review.coreboot.org/c/coreboot/+/69143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f542e71d20307397c398fd757d9408438f681ed Gerrit-Change-Number: 69143 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: vc/intel/fsp/fsp2_0/cpx: Add Enhanced Warning Log hob header
by Johnny Lin (Code Review) 02 Nov '22

02 Nov '22

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69142 ) Change subject: vc/intel/fsp/fsp2_0/cpx: Add Enhanced Warning Log hob header ...................................................................... vc/intel/fsp/fsp2_0/cpx: Add Enhanced Warning Log hob header The files were created by reference to the specification document -- BIOS Data ACPI Table (BDAT) Interface Specification v4.0 Draft 5: https://uefi.org/sites/default/files/resources/BDAT%20Specification%20v4.0%… Can get EWL_PRIVATE_DATA struct by FSP_HOB_EWLID_GUID. This change only uses type 3. Change-Id: I95fbc6c2f5e2debff9eadc3c6ec3a413398d7606 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- A src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/EnhancedWarningLogLib.h A src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_enhancedwarningloglib.h 2 files changed, 224 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/69142/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/EnhancedWarningLogLib.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/EnhancedWarningLogLib.h new file mode 100644 index 0000000..0bbed0b --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/EnhancedWarningLogLib.h @@ -0,0 +1,167 @@ +/** @file + Interface header file for the Enhanced warning log library class. + + @copyright + INTEL CONFIDENTIAL + Copyright 2018 - 2021 Intel Corporation. <BR> + + The source code contained or described herein and all documents related to the + source code ("Material") are owned by Intel Corporation or its suppliers or + licensors. Title to the Material remains with Intel Corporation or its suppliers + and licensors. The Material may contain trade secrets and proprietary and + confidential information of Intel Corporation and its suppliers and licensors, + and is protected by worldwide copyright and trade secret laws and treaty + provisions. No part of the Material may be used, copied, reproduced, modified, + published, uploaded, posted, transmitted, distributed, or disclosed in any way + without Intel's prior express written permission. + + No license under any patent, copyright, trade secret or other intellectual + property right is granted to or conferred upon you by disclosure or delivery + of the Materials, either expressly, by implication, inducement, estoppel or + otherwise. Any license under such intellectual property rights must be + express and approved by Intel in writing. + + Unless otherwise agreed by Intel in writing, you may not remove or alter + this notice or any other notice embedded in Materials by Intel or + Intel's suppliers or licensors in any way. +**/ + +#ifndef _ENHANCED_WARNING_LOG_LIB_ +#define _ENHANCED_WARNING_LOG_LIB_ + +#define FSP_RESERVED_LEN 12 + +#pragma pack(1) + +/// +/// Enhanced Warning Log Header +/// +typedef struct { + EFI_GUID EwlGuid; /// GUID that uniquely identifies the EWL revision + UINT32 Size; /// Total size in bytes including the header and buffer + UINT32 FreeOffset; /// Offset of the beginning of the free space from byte 0 + /// of the buffer immediately following this structure + /// Can be used to determine if buffer has sufficient space for next entry + UINT32 Crc; /// 32-bit CRC generated over the whole size minus this crc field + /// Note: UEFI 32-bit CRC implementation (CalculateCrc32) (References [7]) + /// Consumers can ignore CRC check if not needed. + UINT32 Reserved; /// Reserved for future use, must be initialized to 0 +} EWL_HEADER; + +/// +/// List of all entry types supported by this revision of EWL +/// +typedef enum { + EwlType0 = 0, + EwlType1 = 1, + EwlType2 = 2, + EwlType3 = 3, + EwlType4 = 4, + EwlType5 = 5, + EwlType6 = 6, + EwlType7 = 7, + EwlType8 = 8, + EwlType9 = 9, + EwlType10 = 10, + EwlType11 = 11, + EwlType12 = 12, + EwlType13 = 13, + EwlType14 = 14, + EwlType15 = 15, + EwlType16 = 16, + EwlType17 = 17, + EwlType18 = 18, + EwlType19 = 19, + EwlType20 = 20, + EwlType21 = 21, + EwlType22 = 22, + EwlType23 = 23, + EwlType24 = 24, + EwlType25 = 25, + EwlType26 = 26, + EwlType27 = 27, + EwlType28 = 28, + EwlType29 = 29, + EwlType30 = 30, + EwlType31 = 31, + EwlType32 = 32, + EwlTypeMax, + EwlTypeOem = 0x8000, + EwlTypeDelim = MAX_INT32 +} EWL_TYPE; + +/// +/// EWL severities +/// +typedef enum { + EwlSeverityInfo, + EwlSeverityWarning, + EwlSeverityFatal, + EwlSeverityMax, + EwlSeverityDelim = MAX_INT32 +} EWL_SEVERITY; + + +/// +/// Generic entry header for parsing the log +/// +typedef struct { + EWL_TYPE Type; + UINT16 Size; /// Entries will be packed by byte in contiguous space + EWL_SEVERITY Severity; /// Warning, error, informational, this may be extended in the future +} EWL_ENTRY_HEADER; + +/// +/// Legacy content provides context of the warning +/// +typedef struct { + UINT8 MajorCheckpoint; // EWL Spec - Appendix B + UINT8 MinorCheckpoint; + UINT8 MajorWarningCode; // EWL Spec - Appendix A + UINT8 MinorWarningCode; +} EWL_ENTRY_CONTEXT; + +/// +/// Legacy content to specify memory location +/// +typedef struct { + UINT8 Socket; /// 0xFF = n/a + UINT8 Channel; /// 0xFF = n/a + UINT8 PseudoChannel; /// 0xFF = n/a + UINT8 Dimm; /// 0xFF = n/a + UINT8 Rank; /// 0xFF = n/a +} EWL_ENTRY_MEMORY_LOCATION; + +/// +/// Type 3 = Enhanced type for command, control IO errors +/// +typedef struct { + EWL_ENTRY_HEADER Header; + EWL_ENTRY_CONTEXT Context; + EWL_ENTRY_MEMORY_LOCATION MemoryLocation; + UINT8 reserved1[FSP_RESERVED_LEN]; // MRC_LT Level; MRC_GT Group; GSM_CSN Signal; + UINT8 EyeSize; // 0xFF = n/a +} EWL_ENTRY_TYPE3; + +#pragma pack() + +/// +/// Enhanced Warning Log Spec defined data log structure +/// +typedef struct { + EWL_HEADER Header; /// The size will vary by implementation and should not be assumed + UINT8 Buffer[4 * 1024]; /// The spec requirement is that the buffer follow the header +} EWL_PUBLIC_DATA; + +/// +/// EWL private data structure. This is going to be implementation dependent +/// When we separate OEM hooks via a PPI, we can remove this +/// +typedef struct { + UINT32 bufSizeOverflow; // Number of bytes that could not be added to buffer + UINT32 numEntries; // Number of entries currently logged + EWL_PUBLIC_DATA status; // Spec defined EWL +} EWL_PRIVATE_DATA; + + +#endif // #ifndef _ENHANCED_WARNING_LOG_LIB_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_enhancedwarningloglib.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_enhancedwarningloglib.h new file mode 100644 index 0000000..1a86caa --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_enhancedwarningloglib.h @@ -0,0 +1,40 @@ +/** @file + Interface header file for the Enhanced warning log library class. + + @copyright + INTEL CONFIDENTIAL + Copyright 2018 - 2021 Intel Corporation. <BR> + + The source code contained or described herein and all documents related to the + source code ("Material") are owned by Intel Corporation or its suppliers or + licensors. Title to the Material remains with Intel Corporation or its suppliers + and licensors. The Material may contain trade secrets and proprietary and + confidential information of Intel Corporation and its suppliers and licensors, + and is protected by worldwide copyright and trade secret laws and treaty + provisions. No part of the Material may be used, copied, reproduced, modified, + published, uploaded, posted, transmitted, distributed, or disclosed in any way + without Intel's prior express written permission. + + No license under any patent, copyright, trade secret or other intellectual + property right is granted to or conferred upon you by disclosure or delivery + of the Materials, either expressly, by implication, inducement, estoppel or + otherwise. Any license under such intellectual property rights must be + express and approved by Intel in writing. + + Unless otherwise agreed by Intel in writing, you may not remove or alter + this notice or any other notice embedded in Materials by Intel or + Intel's suppliers or licensors in any way. +**/ + +#ifndef _HOB_ENHANCEDWARNINGLOG_H_ +#define _HOB_ENHANCEDWARNINGLOG_H_ + +#include <fsp/util.h> +#include "EnhancedWarningLogLib.h" + +#define FSP_HOB_EWLID_GUID { \ + 0x00, 0x58, 0xe0, 0xd8, 0x5e, 0x00, 0x62, 0x44,\ + 0xaa, 0x3d, 0x9c, 0x6b, 0x47, 0x4, 0x92, 0x0b \ +} + +#endif //_HOB_ENHANCEDWARNINGLOG_H_ -- To view, visit https://review.coreboot.org/c/coreboot/+/69142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95fbc6c2f5e2debff9eadc3c6ec3a413398d7606 Gerrit-Change-Number: 69142 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: cbfstool/lz4: Fix compilation issue
by Subrata Banik (Code Review) 02 Nov '22

02 Nov '22

Subrata Banik has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/69091 ) Change subject: cbfstool/lz4: Fix compilation issue ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/69091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82110085c39d001afbdf777481fd7fb1553d731d Gerrit-Change-Number: 69091 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: soc/intel/alderlake: Hook up GMA ACPI brightness controls
by Angel Pons (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Tim Crawford, Tarun Tuli, Subrata Banik. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69076 ) Change subject: soc/intel/alderlake: Hook up GMA ACPI brightness controls ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > I thought the backlight control has moved into Intel GFX driver since few generations now and we don […] Backlight control on Windows doesn't seem to work without ACPI. Also, see https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/3PJ3… -- To view, visit https://review.coreboot.org/c/coreboot/+/69076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cc33bf0121ff44aea68a7e3615c5e58e2ab6ce2 Gerrit-Change-Number: 69076 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Wed, 02 Nov 2022 11:00:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/prodrive/atlas: Add IBECC Kconfig option
by Maximilian Brune (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Paul Menzel, Christian Walter, Angel Pons, Lean Sheng Tan. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68783 ) Change subject: mb/prodrive/atlas: Add IBECC Kconfig option ...................................................................... Patch Set 3: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68783/comment/982a85d5_3996c61e PS2, Line 10: indurance > *e*ndurance Done https://review.coreboot.org/c/coreboot/+/68783/comment/cde6d67f_adaa7784 PS2, Line 12: Test: start atlas mainboard with Linux. See in dmesg that IBECC (EDAC igen6) driver is loaded. Inject a fake error via debugfs and see in dmesg that Linux handles it. > Please wrap at 72 characters Done File src/mainboard/prodrive/atlas/Kconfig: https://review.coreboot.org/c/coreboot/+/68783/comment/b8f34591_9146724b PS2, Line 26: indurance > *e*ndurance Done https://review.coreboot.org/c/coreboot/+/68783/comment/ea001a6f_155acb9a PS2, Line 27: not always required > Why is it default enabled then? My bad File src/mainboard/prodrive/atlas/devicetree.cb: https://review.coreboot.org/c/coreboot/+/68783/comment/acd7d368_80d1df78 PS2, Line 50: ? true : false > This is redundant Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71ee2401136e2dc70b3164db6c99af03a3e1f346 Gerrit-Change-Number: 68783 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 02 Nov 2022 10:59:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/prodrive/atlas: Add IBECC Kconfig option
by Maximilian Brune (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Paul Menzel, Christian Walter, Maximilian Brune, Lean Sheng Tan. Hello build bot (Jenkins), Christian Walter, Angel Pons, Lean Sheng Tan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68783 to look at the new patch set (#3). Change subject: mb/prodrive/atlas: Add IBECC Kconfig option ...................................................................... mb/prodrive/atlas: Add IBECC Kconfig option Add an option on Atlas to enable IBECC (In Band Error Correction Code), which is currently needed for endurance testing. Test: start atlas mainboard with Linux. See in dmesg that IBECC (EDAC igen6) driver is loaded. Inject a fake error via debugfs and see in dmesg that Linux handles it. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I71ee2401136e2dc70b3164db6c99af03a3e1f346 --- M src/mainboard/prodrive/atlas/Kconfig M src/mainboard/prodrive/atlas/devicetree.cb 2 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/68783/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71ee2401136e2dc70b3164db6c99af03a3e1f346 Gerrit-Change-Number: 68783 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: cbfstool/lz4: Fix compilation issue
by Angel Pons (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Paul Menzel, Kapil Porwal, Julius Werner, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69091 ) Change subject: cbfstool/lz4: Fix compilation issue ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > > Have you tried cherry-picking CB:63936 to see if it works? > > yeah it works Nice, then we can probably drop this change -- To view, visit https://review.coreboot.org/c/coreboot/+/69091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82110085c39d001afbdf777481fd7fb1553d731d Gerrit-Change-Number: 69091 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 02 Nov 2022 10:58:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/alderlake: Add IBECC
by Angel Pons (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Paul Menzel, Christian Walter, Tim Wawrzynczak, Maximilian Brune, Lean Sheng Tan, David Milosevic. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68756 ) Change subject: soc/intel/alderlake: Add IBECC ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cc2ed6defa1223aa422b9b0d8145f8f8b3dd12e Gerrit-Change-Number: 68756 Gerrit-PatchSet: 7 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Wed, 02 Nov 2022 10:58:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/alderlake: Add IBECC
by Maximilian Brune (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Paul Menzel, Christian Walter, Tim Wawrzynczak, Angel Pons, Lean Sheng Tan, David Milosevic. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68756 ) Change subject: soc/intel/alderlake: Add IBECC ...................................................................... Patch Set 7: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68756/comment/97eda0ba_1d710775 PS5, Line 7: src/ > Drop `src/` Done https://review.coreboot.org/c/coreboot/+/68756/comment/eb7c76a3_7fd14bcd PS5, Line 7: Alderlake > Alder Lake, but it’s redundant as it’s in the prefix. Done https://review.coreboot.org/c/coreboot/+/68756/comment/899e33fa_423ea5f8 PS5, Line 10: Board > Without capitalizing `b`? +1 Done https://review.coreboot.org/c/coreboot/+/68756/comment/1abc0aca_557fd1a9 PS5, Line 11: > > Please elaborate. Is the FSP doing that? […] Done Patchset: PS5: > Should something be logged, when this is enabled? Done File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/68756/comment/c00d04ae_a7535356 PS5, Line 372: !!config->ibecc.enable > It's a `bool` already Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cc2ed6defa1223aa422b9b0d8145f8f8b3dd12e Gerrit-Change-Number: 68756 Gerrit-PatchSet: 7 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Wed, 02 Nov 2022 10:54:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cbfstool/lz4: Fix compilation issue
by Subrata Banik (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Tarun Tuli, Paul Menzel, Kapil Porwal, Angel Pons, Julius Werner, Arthur Heymans. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69091 ) Change subject: cbfstool/lz4: Fix compilation issue ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > Have you tried cherry-picking CB:63936 to see if it works? yeah it works -- To view, visit https://review.coreboot.org/c/coreboot/+/69091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82110085c39d001afbdf777481fd7fb1553d731d Gerrit-Change-Number: 69091 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 02 Nov 2022 10:54:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit November 2022