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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69146 )
Change subject: mb/ocp/deltalake: Add EWL Hob processing for MRC error
......................................................................
Patch Set 1:
(1 comment)
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Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162117):
https://review.coreboot.org/c/coreboot/+/69146/comment/384a6663_a8195481
PS1, Line 9: Override the weak function mainboard_ewl_check() and
'disble' may be misspelled - perhaps 'disable'?
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Change subject: vc/intel/fsp/fsp2_0/cpx: Add Enhanced Warning Log hob header
......................................................................
Patch Set 1:
(1 comment)
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Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162113):
https://review.coreboot.org/c/coreboot/+/69142/comment/bead7e40_0da84cd5
PS1, Line 10: -- BIOS Data ACPI Table (BDAT) Interface Specification v4.0 Draft 5:
Possible unwrapped commit description (prefer a maximum 72 chars per line)
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Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69148 )
Change subject: drivers/ocp/ewl: Set CMOS flag to enforce MRC when there's EWL type3 error
......................................................................
drivers/ocp/ewl: Set CMOS flag to enforce MRC when there's EWL type3 error
If Fastboot is enabled, the next boot will skip MRC and won't be able
to detect MRC error via EWL and still continues booting. Set a CMOS flag
to enforce FSP MRC training in the next boot.
Reference CPX change https://review.coreboot.org/c/coreboot/+/51230
Change-Id: I9dee0472f8e2602cecf88c6d00dec0bf02b9f7bd
Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com>
---
M src/drivers/ocp/ewl/ewl.c
1 file changed, 36 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/69148/1
diff --git a/src/drivers/ocp/ewl/ewl.c b/src/drivers/ocp/ewl/ewl.c
index 5448c30..8e4648e 100644
--- a/src/drivers/ocp/ewl/ewl.c
+++ b/src/drivers/ocp/ewl/ewl.c
@@ -1,10 +1,25 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <pc80/mc146818rtc.h>
#include <soc/soc_util.h>
+#include <stdbool.h>
#include <lib.h>
#include <drivers/ipmi/ocp/ipmi_ocp.h>
#include "ocp_ewl.h"
+#define CMOS_OFFSET_MRC_STATUS 0x47
+
+static void set_cmos_mrc_cold_boot_flag(bool cold_boot_required)
+{
+ uint8_t mrc_status = cmos_read(CMOS_OFFSET_MRC_STATUS);
+ uint8_t new_mrc_status = (mrc_status & 0xfe) | cold_boot_required;
+ printk(BIOS_SPEW, "MRC status: 0x%02x want 0x%02x\n", mrc_status, new_mrc_status);
+ if (new_mrc_status != mrc_status) {
+ printk(BIOS_DEBUG, "Set CMOS MRC cold boot flag.\n");
+ cmos_write(new_mrc_status, CMOS_OFFSET_MRC_STATUS);
+ }
+}
+
static void ipmi_send_sel_ewl_type3_err(EWL_ENTRY_HEADER *header,
EWL_ENTRY_MEMORY_LOCATION memory_location)
{
@@ -81,6 +96,11 @@
}
offset += warning_header->Size;
}
- if (type3_flag)
+ if (type3_flag) {
+ /* If Fastboot is enabled, the next boot will skip MRC and won't detect
+ MRC error via EWL and still can boot up, so set cmos flag to enforce
+ MRC as a workaround. */
+ set_cmos_mrc_cold_boot_flag(true);
die("Memory Training Error!\n");
+ }
}
--
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Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69143 )
Change subject: soc/xeon_sp: Add weak mainboard_ewl_check for EWL check after FSP-M
......................................................................
soc/xeon_sp: Add weak mainboard_ewl_check for EWL check after FSP-M
EWL (Enhanced Warning Log) is a FSP HOB generated by FSP-M that may
contain several warnings/errors related to core, uncore and memory, etc.
mainboard can override it in its romstage.c for its own
Enhanced Warning Log check.
Change-Id: I6f542e71d20307397c398fd757d9408438f681ed
Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com>
---
M src/soc/intel/xeon_sp/include/soc/romstage.h
M src/soc/intel/xeon_sp/romstage.c
2 files changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/69143/1
diff --git a/src/soc/intel/xeon_sp/include/soc/romstage.h b/src/soc/intel/xeon_sp/include/soc/romstage.h
index 90689af..a2adfed 100644
--- a/src/soc/intel/xeon_sp/include/soc/romstage.h
+++ b/src/soc/intel/xeon_sp/include/soc/romstage.h
@@ -9,4 +9,6 @@
void mainboard_memory_init_params(FSPM_UPD * mupd);
void mainboard_rtc_failed(void);
void save_dimm_info(void);
+void mainboard_ewl_check(void);
+
#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c
index b1c7b3b..d001d61 100644
--- a/src/soc/intel/xeon_sp/romstage.c
+++ b/src/soc/intel/xeon_sp/romstage.c
@@ -15,6 +15,7 @@
fsp_memory_init(false);
printk(BIOS_DEBUG, "coreboot fsp_memory_init finished...\n");
+ mainboard_ewl_check();
unlock_pam_regions();
@@ -31,3 +32,4 @@
}
__weak void save_dimm_info(void) { }
+__weak void mainboard_ewl_check(void) { }
--
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Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69142 )
Change subject: vc/intel/fsp/fsp2_0/cpx: Add Enhanced Warning Log hob header
......................................................................
vc/intel/fsp/fsp2_0/cpx: Add Enhanced Warning Log hob header
The files were created by reference to the specification document
-- BIOS Data ACPI Table (BDAT) Interface Specification v4.0 Draft 5:
https://uefi.org/sites/default/files/resources/BDAT%20Specification%20v4.0%…
Can get EWL_PRIVATE_DATA struct by FSP_HOB_EWLID_GUID. This change only
uses type 3.
Change-Id: I95fbc6c2f5e2debff9eadc3c6ec3a413398d7606
Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com>
---
A src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/EnhancedWarningLogLib.h
A src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_enhancedwarningloglib.h
2 files changed, 224 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/69142/1
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/EnhancedWarningLogLib.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/EnhancedWarningLogLib.h
new file mode 100644
index 0000000..0bbed0b
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/EnhancedWarningLogLib.h
@@ -0,0 +1,167 @@
+/** @file
+ Interface header file for the Enhanced warning log library class.
+
+ @copyright
+ INTEL CONFIDENTIAL
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+
+ The source code contained or described herein and all documents related to the
+ source code ("Material") are owned by Intel Corporation or its suppliers or
+ licensors. Title to the Material remains with Intel Corporation or its suppliers
+ and licensors. The Material may contain trade secrets and proprietary and
+ confidential information of Intel Corporation and its suppliers and licensors,
+ and is protected by worldwide copyright and trade secret laws and treaty
+ provisions. No part of the Material may be used, copied, reproduced, modified,
+ published, uploaded, posted, transmitted, distributed, or disclosed in any way
+ without Intel's prior express written permission.
+
+ No license under any patent, copyright, trade secret or other intellectual
+ property right is granted to or conferred upon you by disclosure or delivery
+ of the Materials, either expressly, by implication, inducement, estoppel or
+ otherwise. Any license under such intellectual property rights must be
+ express and approved by Intel in writing.
+
+ Unless otherwise agreed by Intel in writing, you may not remove or alter
+ this notice or any other notice embedded in Materials by Intel or
+ Intel's suppliers or licensors in any way.
+**/
+
+#ifndef _ENHANCED_WARNING_LOG_LIB_
+#define _ENHANCED_WARNING_LOG_LIB_
+
+#define FSP_RESERVED_LEN 12
+
+#pragma pack(1)
+
+///
+/// Enhanced Warning Log Header
+///
+typedef struct {
+ EFI_GUID EwlGuid; /// GUID that uniquely identifies the EWL revision
+ UINT32 Size; /// Total size in bytes including the header and buffer
+ UINT32 FreeOffset; /// Offset of the beginning of the free space from byte 0
+ /// of the buffer immediately following this structure
+ /// Can be used to determine if buffer has sufficient space for next entry
+ UINT32 Crc; /// 32-bit CRC generated over the whole size minus this crc field
+ /// Note: UEFI 32-bit CRC implementation (CalculateCrc32) (References [7])
+ /// Consumers can ignore CRC check if not needed.
+ UINT32 Reserved; /// Reserved for future use, must be initialized to 0
+} EWL_HEADER;
+
+///
+/// List of all entry types supported by this revision of EWL
+///
+typedef enum {
+ EwlType0 = 0,
+ EwlType1 = 1,
+ EwlType2 = 2,
+ EwlType3 = 3,
+ EwlType4 = 4,
+ EwlType5 = 5,
+ EwlType6 = 6,
+ EwlType7 = 7,
+ EwlType8 = 8,
+ EwlType9 = 9,
+ EwlType10 = 10,
+ EwlType11 = 11,
+ EwlType12 = 12,
+ EwlType13 = 13,
+ EwlType14 = 14,
+ EwlType15 = 15,
+ EwlType16 = 16,
+ EwlType17 = 17,
+ EwlType18 = 18,
+ EwlType19 = 19,
+ EwlType20 = 20,
+ EwlType21 = 21,
+ EwlType22 = 22,
+ EwlType23 = 23,
+ EwlType24 = 24,
+ EwlType25 = 25,
+ EwlType26 = 26,
+ EwlType27 = 27,
+ EwlType28 = 28,
+ EwlType29 = 29,
+ EwlType30 = 30,
+ EwlType31 = 31,
+ EwlType32 = 32,
+ EwlTypeMax,
+ EwlTypeOem = 0x8000,
+ EwlTypeDelim = MAX_INT32
+} EWL_TYPE;
+
+///
+/// EWL severities
+///
+typedef enum {
+ EwlSeverityInfo,
+ EwlSeverityWarning,
+ EwlSeverityFatal,
+ EwlSeverityMax,
+ EwlSeverityDelim = MAX_INT32
+} EWL_SEVERITY;
+
+
+///
+/// Generic entry header for parsing the log
+///
+typedef struct {
+ EWL_TYPE Type;
+ UINT16 Size; /// Entries will be packed by byte in contiguous space
+ EWL_SEVERITY Severity; /// Warning, error, informational, this may be extended in the future
+} EWL_ENTRY_HEADER;
+
+///
+/// Legacy content provides context of the warning
+///
+typedef struct {
+ UINT8 MajorCheckpoint; // EWL Spec - Appendix B
+ UINT8 MinorCheckpoint;
+ UINT8 MajorWarningCode; // EWL Spec - Appendix A
+ UINT8 MinorWarningCode;
+} EWL_ENTRY_CONTEXT;
+
+///
+/// Legacy content to specify memory location
+///
+typedef struct {
+ UINT8 Socket; /// 0xFF = n/a
+ UINT8 Channel; /// 0xFF = n/a
+ UINT8 PseudoChannel; /// 0xFF = n/a
+ UINT8 Dimm; /// 0xFF = n/a
+ UINT8 Rank; /// 0xFF = n/a
+} EWL_ENTRY_MEMORY_LOCATION;
+
+///
+/// Type 3 = Enhanced type for command, control IO errors
+///
+typedef struct {
+ EWL_ENTRY_HEADER Header;
+ EWL_ENTRY_CONTEXT Context;
+ EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
+ UINT8 reserved1[FSP_RESERVED_LEN]; // MRC_LT Level; MRC_GT Group; GSM_CSN Signal;
+ UINT8 EyeSize; // 0xFF = n/a
+} EWL_ENTRY_TYPE3;
+
+#pragma pack()
+
+///
+/// Enhanced Warning Log Spec defined data log structure
+///
+typedef struct {
+ EWL_HEADER Header; /// The size will vary by implementation and should not be assumed
+ UINT8 Buffer[4 * 1024]; /// The spec requirement is that the buffer follow the header
+} EWL_PUBLIC_DATA;
+
+///
+/// EWL private data structure. This is going to be implementation dependent
+/// When we separate OEM hooks via a PPI, we can remove this
+///
+typedef struct {
+ UINT32 bufSizeOverflow; // Number of bytes that could not be added to buffer
+ UINT32 numEntries; // Number of entries currently logged
+ EWL_PUBLIC_DATA status; // Spec defined EWL
+} EWL_PRIVATE_DATA;
+
+
+#endif // #ifndef _ENHANCED_WARNING_LOG_LIB_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_enhancedwarningloglib.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_enhancedwarningloglib.h
new file mode 100644
index 0000000..1a86caa
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_enhancedwarningloglib.h
@@ -0,0 +1,40 @@
+/** @file
+ Interface header file for the Enhanced warning log library class.
+
+ @copyright
+ INTEL CONFIDENTIAL
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+
+ The source code contained or described herein and all documents related to the
+ source code ("Material") are owned by Intel Corporation or its suppliers or
+ licensors. Title to the Material remains with Intel Corporation or its suppliers
+ and licensors. The Material may contain trade secrets and proprietary and
+ confidential information of Intel Corporation and its suppliers and licensors,
+ and is protected by worldwide copyright and trade secret laws and treaty
+ provisions. No part of the Material may be used, copied, reproduced, modified,
+ published, uploaded, posted, transmitted, distributed, or disclosed in any way
+ without Intel's prior express written permission.
+
+ No license under any patent, copyright, trade secret or other intellectual
+ property right is granted to or conferred upon you by disclosure or delivery
+ of the Materials, either expressly, by implication, inducement, estoppel or
+ otherwise. Any license under such intellectual property rights must be
+ express and approved by Intel in writing.
+
+ Unless otherwise agreed by Intel in writing, you may not remove or alter
+ this notice or any other notice embedded in Materials by Intel or
+ Intel's suppliers or licensors in any way.
+**/
+
+#ifndef _HOB_ENHANCEDWARNINGLOG_H_
+#define _HOB_ENHANCEDWARNINGLOG_H_
+
+#include <fsp/util.h>
+#include "EnhancedWarningLogLib.h"
+
+#define FSP_HOB_EWLID_GUID { \
+ 0x00, 0x58, 0xe0, 0xd8, 0x5e, 0x00, 0x62, 0x44,\
+ 0xaa, 0x3d, 0x9c, 0x6b, 0x47, 0x4, 0x92, 0x0b \
+}
+
+#endif //_HOB_ENHANCEDWARNINGLOG_H_
--
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