Hello Shelly Chang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69147
to look at the new patch set (#2).
Change subject: drivers/ocp/ewl: Add sending Meta's BMC SEL for memory training error
......................................................................
drivers/ocp/ewl: Add sending Meta's BMC SEL for memory training error
Add sending Meta's BMC SEL for memory training error occurred in EWL
type 3 error.
Change-Id: I664e9d3da7910b47260881c0df64159c8dbe2dca
Signed-off-by: Shelly Chang <Shelly_Chang(a)wiwynn.com>
Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com>
---
M src/drivers/ipmi/ocp/Makefile.inc
M src/drivers/ipmi/ocp/ipmi_ocp.h
M src/drivers/ocp/ewl/ewl.c
3 files changed, 73 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/69147/2
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Gerrit-Change-Number: 69147
Gerrit-PatchSet: 2
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62830 )
Change subject: Makefile.inc: Decrease minimal pagesize from 4 kB to 1 kB
......................................................................
Patch Set 3:
(4 comments)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162120):
https://review.coreboot.org/c/coreboot/+/62830/comment/fb34933c_14520096
PS3, Line 17: In function 'write_ble8',
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162120):
https://review.coreboot.org/c/coreboot/+/62830/comment/62f6acce_b6e2951d
PS3, Line 20: inlined from 'setup_ebda' at src/arch/x86/ebda.c:35:2,
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Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162120):
https://review.coreboot.org/c/coreboot/+/62830/comment/0e6af3ca_1f5406ea
PS3, Line 21: inlined from 'setup_default_ebda' at src/arch/x86/ebda.c:48:2:
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Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162120):
https://review.coreboot.org/c/coreboot/+/62830/comment/f60ac703_6d7098a2
PS3, Line 30: pointer arithmetics from NULL while addresses equal or larger than that
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Attention is currently required from: Jonathan Zhang, Christian Walter, Arthur Heymans, Tim Chu, Shelly Chang.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69146 )
Change subject: mb/ocp/deltalake: Add EWL Hob processing for MRC error
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162117):
https://review.coreboot.org/c/coreboot/+/69146/comment/384a6663_a8195481
PS1, Line 9: Override the weak function mainboard_ewl_check() and
'disble' may be misspelled - perhaps 'disable'?
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69142 )
Change subject: vc/intel/fsp/fsp2_0/cpx: Add Enhanced Warning Log hob header
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162113):
https://review.coreboot.org/c/coreboot/+/69142/comment/bead7e40_0da84cd5
PS1, Line 10: -- BIOS Data ACPI Table (BDAT) Interface Specification v4.0 Draft 5:
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Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69148 )
Change subject: drivers/ocp/ewl: Set CMOS flag to enforce MRC when there's EWL type3 error
......................................................................
drivers/ocp/ewl: Set CMOS flag to enforce MRC when there's EWL type3 error
If Fastboot is enabled, the next boot will skip MRC and won't be able
to detect MRC error via EWL and still continues booting. Set a CMOS flag
to enforce FSP MRC training in the next boot.
Reference CPX change https://review.coreboot.org/c/coreboot/+/51230
Change-Id: I9dee0472f8e2602cecf88c6d00dec0bf02b9f7bd
Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com>
---
M src/drivers/ocp/ewl/ewl.c
1 file changed, 36 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/69148/1
diff --git a/src/drivers/ocp/ewl/ewl.c b/src/drivers/ocp/ewl/ewl.c
index 5448c30..8e4648e 100644
--- a/src/drivers/ocp/ewl/ewl.c
+++ b/src/drivers/ocp/ewl/ewl.c
@@ -1,10 +1,25 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <pc80/mc146818rtc.h>
#include <soc/soc_util.h>
+#include <stdbool.h>
#include <lib.h>
#include <drivers/ipmi/ocp/ipmi_ocp.h>
#include "ocp_ewl.h"
+#define CMOS_OFFSET_MRC_STATUS 0x47
+
+static void set_cmos_mrc_cold_boot_flag(bool cold_boot_required)
+{
+ uint8_t mrc_status = cmos_read(CMOS_OFFSET_MRC_STATUS);
+ uint8_t new_mrc_status = (mrc_status & 0xfe) | cold_boot_required;
+ printk(BIOS_SPEW, "MRC status: 0x%02x want 0x%02x\n", mrc_status, new_mrc_status);
+ if (new_mrc_status != mrc_status) {
+ printk(BIOS_DEBUG, "Set CMOS MRC cold boot flag.\n");
+ cmos_write(new_mrc_status, CMOS_OFFSET_MRC_STATUS);
+ }
+}
+
static void ipmi_send_sel_ewl_type3_err(EWL_ENTRY_HEADER *header,
EWL_ENTRY_MEMORY_LOCATION memory_location)
{
@@ -81,6 +96,11 @@
}
offset += warning_header->Size;
}
- if (type3_flag)
+ if (type3_flag) {
+ /* If Fastboot is enabled, the next boot will skip MRC and won't detect
+ MRC error via EWL and still can boot up, so set cmos flag to enforce
+ MRC as a workaround. */
+ set_cmos_mrc_cold_boot_flag(true);
die("Memory Training Error!\n");
+ }
}
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