coreboot-gerrit November 2022

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[M] Change in coreboot[master]: cbmem_top_chipset: Change the return value to uintptr_t
by Elyes Haouas (Code Review) 02 Nov '22

02 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69078 ) Change subject: cbmem_top_chipset: Change the return value to uintptr_t ...................................................................... cbmem_top_chipset: Change the return value to uintptr_t Get rid of a lot of casts. Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/drivers/amd/agesa/romstage.c M src/drivers/intel/fsp2_0/cbmem.c M src/include/cbmem.h M src/mainboard/emulation/qemu-aarch64/cbmem.c M src/mainboard/emulation/qemu-armv7/cbmem.c M src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-power8/cbmem.c M src/mainboard/emulation/qemu-power9/cbmem.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/ironlake/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/soc/amd/stoneyridge/memmap.c M src/soc/cavium/cn81xx/cbmem.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/braswell/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/mediatek/common/cbmem.c M src/soc/nvidia/tegra124/cbmem.c M src/soc/nvidia/tegra210/cbmem.c M src/soc/qualcomm/ipq40xx/cbmem.c M src/soc/qualcomm/ipq806x/cbmem.c M src/soc/qualcomm/qcs405/cbmem.c M src/soc/qualcomm/sc7180/cbmem.c M src/soc/qualcomm/sc7280/cbmem.c M src/soc/rockchip/common/cbmem.c M src/soc/samsung/exynos5250/cbmem.c M src/soc/samsung/exynos5420/cbmem.c M src/soc/sifive/fu540/cbmem.c M src/soc/ti/am335x/cbmem.c M src/soc/ucb/riscv/cbmem.c M tests/lib/coreboot_table-test.c M tests/lib/imd_cbmem-test.c 37 files changed, 86 insertions(+), 74 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/69078/1 diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index f60239a..c8bcfec 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -93,8 +93,8 @@ halt(); } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ - return (void *)restore_top_of_low_cacheable(); + return restore_top_of_low_cacheable(); } diff --git a/src/drivers/intel/fsp2_0/cbmem.c b/src/drivers/intel/fsp2_0/cbmem.c index 0efb462..b725aad 100644 --- a/src/drivers/intel/fsp2_0/cbmem.c +++ b/src/drivers/intel/fsp2_0/cbmem.c @@ -3,10 +3,10 @@ #include <cbmem.h> #include <fsp/util.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { struct range_entry tolum; fsp_find_bootloader_tolum(&tolum); - return (void *)(uintptr_t)range_entry_end(&tolum); + return (uintptr_t)range_entry_end(&tolum); } diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 5b5191a..911291a 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -65,7 +65,7 @@ * in the _cbmem_top_ptr symbol. Without CONFIG_RAMSTAGE_CBMEM_TOP_ARG the same * implementation as used in romstage will be used. */ -void *cbmem_top_chipset(void); +uintptr_t cbmem_top_chipset(void); /* Add a cbmem entry of a given size and id. These return NULL on failure. The * add function performs a find first and do not check against the original diff --git a/src/mainboard/emulation/qemu-aarch64/cbmem.c b/src/mainboard/emulation/qemu-aarch64/cbmem.c index 6b6ac72..389ff4e 100644 --- a/src/mainboard/emulation/qemu-aarch64/cbmem.c +++ b/src/mainboard/emulation/qemu-aarch64/cbmem.c @@ -4,7 +4,7 @@ #include <ramdetect.h> #include <symbols.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/src/mainboard/emulation/qemu-armv7/cbmem.c b/src/mainboard/emulation/qemu-armv7/cbmem.c index 157e443..5c423a0 100644 --- a/src/mainboard/emulation/qemu-armv7/cbmem.c +++ b/src/mainboard/emulation/qemu-armv7/cbmem.c @@ -4,7 +4,7 @@ #include <symbols.h> #include <ramdetect.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/src/mainboard/emulation/qemu-i440fx/memmap.c b/src/mainboard/emulation/qemu-i440fx/memmap.c index 75ab352..efe83c3 100644 --- a/src/mainboard/emulation/qemu-i440fx/memmap.c +++ b/src/mainboard/emulation/qemu-i440fx/memmap.c @@ -41,7 +41,7 @@ return tomk; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t top = 0; @@ -56,7 +56,7 @@ smm_region(&top, &smm_size); } - return (void *)top; + return top; } /* Nothing to do, MTRRs are no-op on QEMU. */ diff --git a/src/mainboard/emulation/qemu-power8/cbmem.c b/src/mainboard/emulation/qemu-power8/cbmem.c index 15c20f8..f14a5e2 100644 --- a/src/mainboard/emulation/qemu-power8/cbmem.c +++ b/src/mainboard/emulation/qemu-power8/cbmem.c @@ -2,10 +2,10 @@ #include <cbmem.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ /* For now, last 1M of 4G */ - void *ptr = (void *) ((1ULL << 32) - 1048576); + uintptr_t ptr = (uintptr_t)((1ULL << 32) - 1048576); return ptr; } diff --git a/src/mainboard/emulation/qemu-power9/cbmem.c b/src/mainboard/emulation/qemu-power9/cbmem.c index 1b7b690..11e48bd 100644 --- a/src/mainboard/emulation/qemu-power9/cbmem.c +++ b/src/mainboard/emulation/qemu-power9/cbmem.c @@ -3,7 +3,7 @@ #include <cbmem.h> #include <ramdetect.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)(probe_ramsize(0, CONFIG_DRAM_SIZE_MB) * MiB); + return (probe_ramsize(0, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 28edb38..2ba7c80 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -104,10 +104,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return top_of_ram; } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index c19cfec..6b75caa 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -54,9 +54,9 @@ return tolum; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)top_of_low_usable_memory(); + return top_of_low_usable_memory(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c index b6d9526..5cee1b4 100644 --- a/src/northbridge/intel/i440bx/memmap.c +++ b/src/northbridge/intel/i440bx/memmap.c @@ -8,7 +8,7 @@ #include <program_loading.h> #include "i440bx.h" -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Base of TSEG is top of usable DRAM */ /* @@ -39,7 +39,7 @@ * * Source: 440BX datasheet, pages 3-28 thru 3-29. */ - unsigned long tom = pci_read_config8(NB, DRB7) * 8 * MiB; + uintptr_t tom = pci_read_config8(NB, DRB7) * 8 * MiB; int gsmrame = pci_read_config8(NB, SMRAM) & 0x8; /* T_SZ and TSEG_EN */ @@ -48,7 +48,7 @@ int tseg_size = 128 * KiB * (1 << (tseg >> 1)); tom -= tseg_size; } - return (void *)tom; + return tom; } void fill_postcar_frame(struct postcar_frame *pcf) diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 1fa0358..96dee76 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -57,10 +57,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return top_of_ram; } /* Decodes used Graphics Mode Select (GMS) to kilobytes. */ diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c index 78fbae8..bdb76c1 100644 --- a/src/northbridge/intel/ironlake/memmap.c +++ b/src/northbridge/intel/ironlake/memmap.c @@ -22,9 +22,9 @@ return CONFIG_SMM_TSEG_SIZE; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)northbridge_get_tseg_base(); + return northbridge_get_tseg_base(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index c02cf35..55d7046 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -73,9 +73,9 @@ * Depending of UMA and TSEG configuration, TSEG might start at any 1 MiB alignment. * As this may cause very greedy MTRR setup, push CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *) ALIGN_DOWN(northbridge_get_tseg_base(), 4 * MiB); + return ALIGN_DOWN(northbridge_get_tseg_base(), 4 * MiB); } diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index f667544..ac95ab5 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -54,9 +54,9 @@ return tolum; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)top_of_low_usable_memory(); + return top_of_low_usable_memory(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index dced902..5079756 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -71,10 +71,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return top_of_ram; } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index f015740..8de3515 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -12,7 +12,7 @@ #include <soc/iomap.h> #include <amdblocks/biosram.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { msr_t tom = rdmsr(TOP_MEM); @@ -20,7 +20,7 @@ return 0; /* 8MB alignment to keep MTRR usage low */ - return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() + return ALIGN_DOWN(restore_top_of_low_cacheable() - CONFIG_SMM_TSEG_SIZE, 8 * MiB); } diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c index d50fe16..0b0c717 100644 --- a/src/soc/cavium/cn81xx/cbmem.c +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -5,8 +5,8 @@ #include <soc/sdram.h> #include <symbols.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Make sure not to overlap with reserved ATF scratchpad */ - return (void *)((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB); + return (uintptr_t)_dram + (sdram_size_mb() - 1) * MiB; } diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index aa8e890..43b96c1 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -16,9 +16,9 @@ return CONFIG_SMM_TSEG_SIZE; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *) smm_region_start(); + return smm_region_start(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index 4a791ef..3c3ad74 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -19,7 +19,7 @@ *size = smm_region_size(); } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t smm_base; size_t smm_size; @@ -53,5 +53,5 @@ */ smm_region(&smm_base, &smm_size); - return (void *)smm_base; + return smm_base; } diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index b467dc0..98c8016 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -29,9 +29,9 @@ return tom; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *) dpr_region_start(); + return dpr_region_start(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/soc/mediatek/common/cbmem.c b/src/soc/mediatek/common/cbmem.c index f9d11e9..0ca9e6b 100644 --- a/src/soc/mediatek/common/cbmem.c +++ b/src/soc/mediatek/common/cbmem.c @@ -7,7 +7,7 @@ #define MAX_DRAM_ADDRESS ((uintptr_t)4 * GiB) -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)MIN((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); + return MIN((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); } diff --git a/src/soc/nvidia/tegra124/cbmem.c b/src/soc/nvidia/tegra124/cbmem.c index 3f59f06..b38a763 100644 --- a/src/soc/nvidia/tegra124/cbmem.c +++ b/src/soc/nvidia/tegra124/cbmem.c @@ -4,7 +4,7 @@ #include <soc/display.h> #include <soc/sdram.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL); + return ((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL); } diff --git a/src/soc/nvidia/tegra210/cbmem.c b/src/soc/nvidia/tegra210/cbmem.c index d9b2226..a56f150 100644 --- a/src/soc/nvidia/tegra210/cbmem.c +++ b/src/soc/nvidia/tegra210/cbmem.c @@ -3,7 +3,7 @@ #include <cbmem.h> #include <soc/addressmap.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { static uintptr_t addr; @@ -19,5 +19,5 @@ addr = end_mib << 20; } - return (void *)addr; + return addr; } diff --git a/src/soc/qualcomm/ipq40xx/cbmem.c b/src/soc/qualcomm/ipq40xx/cbmem.c index 0ee9f9a..e3f4a3e 100644 --- a/src/soc/qualcomm/ipq40xx/cbmem.c +++ b/src/soc/qualcomm/ipq40xx/cbmem.c @@ -10,7 +10,7 @@ cbmem_backing_store_ready = 1; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* * In romstage, make sure that cbmem backing store is ready before @@ -21,5 +21,5 @@ if (cbmem_backing_store_ready == 0) return NULL; - return _memlayout_cbmem_top; + return (uintptr_t)_memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index a695cf8..97f5acd 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -10,7 +10,7 @@ cbmem_backing_store_ready = 1; } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* * In romstage, make sure that cbmem backing store is ready before @@ -22,5 +22,5 @@ if (cbmem_backing_store_ready == 0) return NULL; - return _memlayout_cbmem_top; + return (uintptr_t)_memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/qcs405/cbmem.c b/src/soc/qualcomm/qcs405/cbmem.c index 97ba38b..c5ddb17 100644 --- a/src/soc/qualcomm/qcs405/cbmem.c +++ b/src/soc/qualcomm/qcs405/cbmem.c @@ -2,7 +2,7 @@ #include <cbmem.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((uintptr_t)3 * GiB); + return (uintptr_t)(3 * GiB); } diff --git a/src/soc/qualcomm/sc7180/cbmem.c b/src/soc/qualcomm/sc7180/cbmem.c index 4b9eb37..47cd198 100644 --- a/src/soc/qualcomm/sc7180/cbmem.c +++ b/src/soc/qualcomm/sc7180/cbmem.c @@ -2,7 +2,7 @@ #include <cbmem.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((uintptr_t)4 * GiB); + return (uintptr_t)(4 * GiB); } diff --git a/src/soc/qualcomm/sc7280/cbmem.c b/src/soc/qualcomm/sc7280/cbmem.c index 4b9eb37..47cd198 100644 --- a/src/soc/qualcomm/sc7280/cbmem.c +++ b/src/soc/qualcomm/sc7280/cbmem.c @@ -2,7 +2,7 @@ #include <cbmem.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((uintptr_t)4 * GiB); + return (uintptr_t)(4 * GiB); } diff --git a/src/soc/rockchip/common/cbmem.c b/src/soc/rockchip/common/cbmem.c index 5650114..3019486e 100644 --- a/src/soc/rockchip/common/cbmem.c +++ b/src/soc/rockchip/common/cbmem.c @@ -6,8 +6,8 @@ #include <soc/sdram.h> #include <symbols.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)MIN((uintptr_t)_dram + sdram_size_mb() * MiB, + return MIN((uintptr_t)_dram + sdram_size_mb() * MiB, MAX_DRAM_ADDRESS); } diff --git a/src/soc/samsung/exynos5250/cbmem.c b/src/soc/samsung/exynos5250/cbmem.c index 167bd80..e2b58ab 100644 --- a/src/soc/samsung/exynos5250/cbmem.c +++ b/src/soc/samsung/exynos5250/cbmem.c @@ -3,7 +3,7 @@ #include <cbmem.h> #include <soc/cpu.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)(get_fb_base_kb() * KiB); + return (uintptr_t)(get_fb_base_kb() * KiB); } diff --git a/src/soc/samsung/exynos5420/cbmem.c b/src/soc/samsung/exynos5420/cbmem.c index 167bd80..e2b58ab 100644 --- a/src/soc/samsung/exynos5420/cbmem.c +++ b/src/soc/samsung/exynos5420/cbmem.c @@ -3,7 +3,7 @@ #include <cbmem.h> #include <soc/cpu.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)(get_fb_base_kb() * KiB); + return (uintptr_t)(get_fb_base_kb() * KiB); } diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c index af04130..81db74c 100644 --- a/src/soc/sifive/fu540/cbmem.c +++ b/src/soc/sifive/fu540/cbmem.c @@ -6,8 +6,8 @@ #include <soc/sdram.h> #include <symbols.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)MIN((uintptr_t)_dram + sdram_size_mb() * MiB, + return MIN((uintptr_t)_dram + sdram_size_mb() * MiB, FU540_MAXDRAM); } diff --git a/src/soc/ti/am335x/cbmem.c b/src/soc/ti/am335x/cbmem.c index 3765874..215d48b 100644 --- a/src/soc/ti/am335x/cbmem.c +++ b/src/soc/ti/am335x/cbmem.c @@ -3,7 +3,7 @@ #include <cbmem.h> #include <symbols.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return _dram + (CONFIG_DRAM_SIZE_MB << 20); + return (uintptr_t)_dram + (CONFIG_DRAM_SIZE_MB << 20); } diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c index 157e443..5c423a0 100644 --- a/src/soc/ucb/riscv/cbmem.c +++ b/src/soc/ucb/riscv/cbmem.c @@ -4,7 +4,7 @@ #include <symbols.h> #include <ramdetect.h> -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/tests/lib/coreboot_table-test.c b/tests/lib/coreboot_table-test.c index 5257552..b774c97 100644 --- a/tests/lib/coreboot_table-test.c +++ b/tests/lib/coreboot_table-test.c @@ -264,9 +264,9 @@ } extern uintptr_t _cbmem_top_ptr; -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)_cbmem_top_ptr; + return _cbmem_top_ptr; } #define CBMEM_SIZE (64 * KiB) diff --git a/tests/lib/imd_cbmem-test.c b/tests/lib/imd_cbmem-test.c index fe25285..e345c84 100644 --- a/tests/lib/imd_cbmem-test.c +++ b/tests/lib/imd_cbmem-test.c @@ -36,9 +36,9 @@ function_called(); } -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)_cbmem_top_ptr; + return _cbmem_top_ptr; } static void *get_cbmem_ptr(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/69078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Gerrit-Change-Number: 69078 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: drivers/ocp/ewl: Add sending Meta's BMC SEL for memory training error
by Johnny Lin (Code Review) 02 Nov '22

02 Nov '22

Hello Shelly Chang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69147 to look at the new patch set (#2). Change subject: drivers/ocp/ewl: Add sending Meta's BMC SEL for memory training error ...................................................................... drivers/ocp/ewl: Add sending Meta's BMC SEL for memory training error Add sending Meta's BMC SEL for memory training error occurred in EWL type 3 error. Change-Id: I664e9d3da7910b47260881c0df64159c8dbe2dca Signed-off-by: Shelly Chang <Shelly_Chang(a)wiwynn.com> Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/drivers/ipmi/ocp/Makefile.inc M src/drivers/ipmi/ocp/ipmi_ocp.h M src/drivers/ocp/ewl/ewl.c 3 files changed, 73 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/69147/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I664e9d3da7910b47260881c0df64159c8dbe2dca Gerrit-Change-Number: 69147 Gerrit-PatchSet: 2 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-CC: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: Makefile.inc: Decrease minimal pagesize from 4 kB to 1 kB
by build bot (Jenkins) (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Nico Huber, Martin L Roth, Paul Menzel, Angel Pons. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62830 ) Change subject: Makefile.inc: Decrease minimal pagesize from 4 kB to 1 kB ...................................................................... Patch Set 3: (4 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162120): https://review.coreboot.org/c/coreboot/+/62830/comment/fb34933c_14520096 PS3, Line 17: In function 'write_ble8', Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162120): https://review.coreboot.org/c/coreboot/+/62830/comment/62f6acce_b6e2951d PS3, Line 20: inlined from 'setup_ebda' at src/arch/x86/ebda.c:35:2, Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162120): https://review.coreboot.org/c/coreboot/+/62830/comment/0e6af3ca_1f5406ea PS3, Line 21: inlined from 'setup_default_ebda' at src/arch/x86/ebda.c:48:2: Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162120): https://review.coreboot.org/c/coreboot/+/62830/comment/f60ac703_6d7098a2 PS3, Line 30: pointer arithmetics from NULL while addresses equal or larger than that Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/62830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e36633f42cb4dc5af53212c10c919a86e451ee0 Gerrit-Change-Number: 62830 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 02 Nov 2022 11:18:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/ocp/deltalake: Add EWL Hob processing for MRC error
by build bot (Jenkins) (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Jonathan Zhang, Christian Walter, Arthur Heymans, Tim Chu, Shelly Chang. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69146 ) Change subject: mb/ocp/deltalake: Add EWL Hob processing for MRC error ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162117): https://review.coreboot.org/c/coreboot/+/69146/comment/384a6663_a8195481 PS1, Line 9: Override the weak function mainboard_ewl_check() and 'disble' may be misspelled - perhaps 'disable'? -- To view, visit https://review.coreboot.org/c/coreboot/+/69146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4419ef43815f8181af89c49514a69bdb29858c13 Gerrit-Change-Number: 69146 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Comment-Date: Wed, 02 Nov 2022 11:16:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: vc/intel/fsp/fsp2_0/cpx: Add Enhanced Warning Log hob header
by build bot (Jenkins) (Code Review) 02 Nov '22

02 Nov '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69142 ) Change subject: vc/intel/fsp/fsp2_0/cpx: Add Enhanced Warning Log hob header ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162113): https://review.coreboot.org/c/coreboot/+/69142/comment/bead7e40_0da84cd5 PS1, Line 10: -- BIOS Data ACPI Table (BDAT) Interface Specification v4.0 Draft 5: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/69142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95fbc6c2f5e2debff9eadc3c6ec3a413398d7606 Gerrit-Change-Number: 69142 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 02 Nov 2022 11:14:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: drivers/ocp/ewl: Set CMOS flag to enforce MRC when there's EWL type3 ...
by Johnny Lin (Code Review) 02 Nov '22

02 Nov '22

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69148 ) Change subject: drivers/ocp/ewl: Set CMOS flag to enforce MRC when there's EWL type3 error ...................................................................... drivers/ocp/ewl: Set CMOS flag to enforce MRC when there's EWL type3 error If Fastboot is enabled, the next boot will skip MRC and won't be able to detect MRC error via EWL and still continues booting. Set a CMOS flag to enforce FSP MRC training in the next boot. Reference CPX change https://review.coreboot.org/c/coreboot/+/51230 Change-Id: I9dee0472f8e2602cecf88c6d00dec0bf02b9f7bd Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/drivers/ocp/ewl/ewl.c 1 file changed, 36 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/69148/1 diff --git a/src/drivers/ocp/ewl/ewl.c b/src/drivers/ocp/ewl/ewl.c index 5448c30..8e4648e 100644 --- a/src/drivers/ocp/ewl/ewl.c +++ b/src/drivers/ocp/ewl/ewl.c @@ -1,10 +1,25 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <pc80/mc146818rtc.h> #include <soc/soc_util.h> +#include <stdbool.h> #include <lib.h> #include <drivers/ipmi/ocp/ipmi_ocp.h> #include "ocp_ewl.h" +#define CMOS_OFFSET_MRC_STATUS 0x47 + +static void set_cmos_mrc_cold_boot_flag(bool cold_boot_required) +{ + uint8_t mrc_status = cmos_read(CMOS_OFFSET_MRC_STATUS); + uint8_t new_mrc_status = (mrc_status & 0xfe) | cold_boot_required; + printk(BIOS_SPEW, "MRC status: 0x%02x want 0x%02x\n", mrc_status, new_mrc_status); + if (new_mrc_status != mrc_status) { + printk(BIOS_DEBUG, "Set CMOS MRC cold boot flag.\n"); + cmos_write(new_mrc_status, CMOS_OFFSET_MRC_STATUS); + } +} + static void ipmi_send_sel_ewl_type3_err(EWL_ENTRY_HEADER *header, EWL_ENTRY_MEMORY_LOCATION memory_location) { @@ -81,6 +96,11 @@ } offset += warning_header->Size; } - if (type3_flag) + if (type3_flag) { + /* If Fastboot is enabled, the next boot will skip MRC and won't detect + MRC error via EWL and still can boot up, so set cmos flag to enforce + MRC as a workaround. */ + set_cmos_mrc_cold_boot_flag(true); die("Memory Training Error!\n"); + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/69148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dee0472f8e2602cecf88c6d00dec0bf02b9f7bd Gerrit-Change-Number: 69148 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: drivers/ocp/ewl: Add sending Meta's BMC SEL for memory training error
by Johnny Lin (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Shelly Chang. Hello Shelly Chang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/69147 to review the following change. Change subject: drivers/ocp/ewl: Add sending Meta's BMC SEL for memory training error ...................................................................... drivers/ocp/ewl: Add sending Meta's BMC SEL for memory training error Add sending Meta's BMC SEL for memory training error occurred in EWL type 3 error. Change-Id: I664e9d3da7910b47260881c0df64159c8dbe2dca Signed-off-by: Shelly Chang <Shelly_Chang(a)wiwynn.com> Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/drivers/ipmi/ocp/Makefile.inc M src/drivers/ipmi/ocp/ipmi_ocp.h M src/drivers/ocp/ewl/ewl.c 3 files changed, 70 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/69147/1 diff --git a/src/drivers/ipmi/ocp/Makefile.inc b/src/drivers/ipmi/ocp/Makefile.inc index 2b492e1..3d5e69e 100644 --- a/src/drivers/ipmi/ocp/Makefile.inc +++ b/src/drivers/ipmi/ocp/Makefile.inc @@ -1,5 +1,5 @@ ramstage-$(CONFIG_IPMI_OCP) += ipmi_ocp.c ipmi_sel.c ifeq ($(CONFIG_IPMI_OCP),y) -romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_ocp_romstage.c +romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_ocp_romstage.c ipmi_sel.c smm-$(CONFIG_IPMI_BMC_SEL) += ipmi_sel.c endif diff --git a/src/drivers/ipmi/ocp/ipmi_ocp.h b/src/drivers/ipmi/ocp/ipmi_ocp.h index 571eafc..4bd2492 100644 --- a/src/drivers/ipmi/ocp/ipmi_ocp.h +++ b/src/drivers/ipmi/ocp/ipmi_ocp.h @@ -89,6 +89,16 @@ PCIE_ECRC_EVNT = 5, }; +enum sel_err_type { + MEM_TRAINING_ERR = 0, + MEM_CORR_ERR = 1, + MEM_UNCORR_ERR = 2, + MEM_CORR_ERR_PATROL = 3, + MEM_UNCORR_ERR_PATROL = 4, + MEM_PARITY_ERR = 5, + MEM_UNDEFINED = 0xF, +}; + struct ipmi_sel_pcie_dev_fail { uint16_t record_id; uint8_t record_type; @@ -102,6 +112,21 @@ uint8_t rsvd2; } __packed; +struct ipmi_sel_mem_err { + uint16_t record_id; + uint8_t record_type; + uint8_t general_info; + uint32_t timestamp; + uint8_t socket; + uint8_t channel; + uint8_t dimm_slot; + uint8_t rsvd1; + uint8_t dimm_failure_type; + uint8_t major_code; + uint8_t minor_code; + uint8_t rsvd2; +} __packed; + struct ipmi_config_rsp { uint8_t board_sku_id; uint8_t board_rev_id; @@ -167,6 +192,8 @@ #define PERR_NON_AER 0xA0 #define SERR_NON_AER 0xA1 +#define INTEL_MEMORY_ERROR 0x21 + enum cb_err ipmi_set_post_start(const int port); enum cb_err ipmi_set_cmos_clear(void); diff --git a/src/drivers/ocp/ewl/ewl.c b/src/drivers/ocp/ewl/ewl.c index d70a23f..5448c30 100644 --- a/src/drivers/ocp/ewl/ewl.c +++ b/src/drivers/ocp/ewl/ewl.c @@ -2,8 +2,35 @@ #include <soc/soc_util.h> #include <lib.h> +#include <drivers/ipmi/ocp/ipmi_ocp.h> #include "ocp_ewl.h" +static void ipmi_send_sel_ewl_type3_err(EWL_ENTRY_HEADER *header, + EWL_ENTRY_MEMORY_LOCATION memory_location) +{ + struct ipmi_sel_mem_err sel; + uint8_t socketid = 0xff; + EWL_ENTRY_TYPE3 *basic_warning; + basic_warning = (EWL_ENTRY_TYPE3 *)header; + + memset(&sel, 0, sizeof(struct ipmi_sel_mem_err)); + sel.record_id = 0x0000; + sel.record_type = 0xfb; + sel.general_info = INTEL_MEMORY_ERROR; + sel.timestamp = 0; + socketid = get_blade_id() - 1; + sel.socket = socketid <<= 4; + sel.channel = memory_location.Channel; + sel.dimm_slot = memory_location.Dimm; + sel.rsvd1 = 0xff; + sel.dimm_failure_type = MEM_TRAINING_ERR; + sel.major_code = basic_warning->Context.MajorWarningCode; + sel.minor_code = basic_warning->Context.MinorWarningCode; + sel.rsvd2 = 0xff; + ipmi_send_to_bmc((unsigned char *)&sel, sizeof(sel)); + printk(BIOS_DEBUG, "ipmi send memory training error\n"); +} + static void process_ewl_type3(EWL_ENTRY_HEADER *header, EWL_ENTRY_MEMORY_LOCATION memory_location) { /* Treat warning as type 3, collect basic information and print to serial log */ @@ -44,6 +71,7 @@ type3 = (EWL_ENTRY_TYPE3 *)warning_header; process_ewl_type3(warning_header, type3->MemoryLocation); type3_flag = 1; + ipmi_send_sel_ewl_type3_err(warning_header, type3->MemoryLocation); } else { printk(BIOS_DEBUG, "EWL type: %d size:%d severity level:%d\n", warning_header->Type, -- To view, visit https://review.coreboot.org/c/coreboot/+/69147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I664e9d3da7910b47260881c0df64159c8dbe2dca Gerrit-Change-Number: 69147 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/ocp/deltalake: Add EWL Hob processing for MRC error
by Johnny Lin (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Jonathan Zhang, Christian Walter, Arthur Heymans, Tim Chu, Shelly Chang. Hello Shelly Chang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/69146 to review the following change. Change subject: mb/ocp/deltalake: Add EWL Hob processing for MRC error ...................................................................... mb/ocp/deltalake: Add EWL Hob processing for MRC error Override the weak function mainboard_ewl_check() and select OCP_EWL. The Intel FSP needs to disble promote MRC Warnings otherwise FSP won't return after MRC error. Change-Id: I4419ef43815f8181af89c49514a69bdb29858c13 Signed-off-by: Shelly Chang <Shelly_Chang(a)wiwynn.com> Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/ocp/deltalake/romstage.c 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/69146/1 diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index dbf4a2e..654a816 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -11,6 +11,7 @@ select IPMI_KCS select IPMI_KCS_ROMSTAGE select OCP_DMI + select OCP_EWL select VPD select VPD_SMBIOS_VERSION select IPMI_OCP diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index 2efed1c..4b967bf 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -4,6 +4,7 @@ #include <console/uart.h> #include <drivers/ipmi/ipmi_if.h> #include <drivers/ipmi/ocp/ipmi_ocp.h> +#include <drivers/ocp/ewl/ocp_ewl.h> #include <drivers/vpd/vpd.h> #include <fsp/api.h> #include <FspmUpd.h> @@ -14,6 +15,11 @@ #include "ipmi.h" #include "vpd.h" +void mainboard_ewl_check(void) +{ + get_ewl(); +} + /* Convert the vpd integer to the DDR frenquency limit enum */ static enum ddr_freq_limit ddr_freq_limit(int num) { -- To view, visit https://review.coreboot.org/c/coreboot/+/69146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4419ef43815f8181af89c49514a69bdb29858c13 Gerrit-Change-Number: 69146 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: drivers/ocp/ewl: Add EWL driver for EWL type 3 error handling
by Johnny Lin (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Shelly Chang. Hello Shelly Chang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/69145 to review the following change. Change subject: drivers/ocp/ewl: Add EWL driver for EWL type 3 error handling ...................................................................... drivers/ocp/ewl: Add EWL driver for EWL type 3 error handling Add EWL (Enhanced Warning Log) driver which handles Intel EWL HOB and prints EWL type 3 primarily associated with MRC training failures. Change-Id: Ibd5b521bafd457505db4147c5d3fe41364a09045 Signed-off-by: Shelly Chang <Shelly_Chang(a)wiwynn.com> Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- A src/drivers/ocp/ewl/Kconfig A src/drivers/ocp/ewl/Makefile.inc A src/drivers/ocp/ewl/ewl.c A src/drivers/ocp/ewl/ocp_ewl.h 4 files changed, 88 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/69145/1 diff --git a/src/drivers/ocp/ewl/Kconfig b/src/drivers/ocp/ewl/Kconfig new file mode 100644 index 0000000..3c3b82d --- /dev/null +++ b/src/drivers/ocp/ewl/Kconfig @@ -0,0 +1,5 @@ +config OCP_EWL + bool + default n + help + It implements checking FSP Enhanced Warning Log Hob. diff --git a/src/drivers/ocp/ewl/Makefile.inc b/src/drivers/ocp/ewl/Makefile.inc new file mode 100644 index 0000000..43112e9 --- /dev/null +++ b/src/drivers/ocp/ewl/Makefile.inc @@ -0,0 +1 @@ +romstage-$(CONFIG_OCP_EWL) += ewl.c diff --git a/src/drivers/ocp/ewl/ewl.c b/src/drivers/ocp/ewl/ewl.c new file mode 100644 index 0000000..d70a23f --- /dev/null +++ b/src/drivers/ocp/ewl/ewl.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/soc_util.h> +#include <lib.h> +#include "ocp_ewl.h" + +static void process_ewl_type3(EWL_ENTRY_HEADER *header, EWL_ENTRY_MEMORY_LOCATION memory_location) +{ + /* Treat warning as type 3, collect basic information and print to serial log */ + EWL_ENTRY_TYPE3 *basic_warning; + basic_warning = (EWL_ENTRY_TYPE3 *)header; + printk(BIOS_ERR, "Major Warning Code = 0x%02x, Minor Warning Code = 0x%02x,\n", + basic_warning->Context.MajorWarningCode, + basic_warning->Context.MinorWarningCode); + printk(BIOS_ERR, "Major Checkpoint: 0x%02x\n", basic_warning->Context.MajorCheckpoint); + printk(BIOS_ERR, "Minor Checkpoint: 0x%02x\n", basic_warning->Context.MinorCheckpoint); + + if (memory_location.Socket != 0xff) + printk(BIOS_ERR, "Socket %d\n", memory_location.Socket); + if (memory_location.Channel != 0xff) + printk(BIOS_ERR, "Channel %d\n", memory_location.Channel); + if (memory_location.Dimm != 0xff) + printk(BIOS_ERR, "Dimm %d\n", memory_location.Dimm); + if (memory_location.Rank != 0xff) + printk(BIOS_ERR, "Rank %d\n", memory_location.Rank); +} + +void get_ewl(void) +{ + const EWL_PRIVATE_DATA *hob = get_ewl_hob(); + int offset = 0; + bool type3_flag = 0; + EWL_ENTRY_HEADER *warning_header; + printk(BIOS_DEBUG, "Number of EWL entries %d\n", hob->numEntries); + while (offset < hob->status.Header.FreeOffset) { + warning_header = (EWL_ENTRY_HEADER *) &(hob->status.Buffer[offset]); + if (warning_header->Type == EwlType3) { + printk(BIOS_ERR, "EWL type: %d\n", warning_header->Type); + if (warning_header->Size != sizeof(EWL_ENTRY_TYPE3)) { + printk(BIOS_ERR, "EWL type3 size mismatch!\n"); + return; + } + EWL_ENTRY_TYPE3 *type3; + type3 = (EWL_ENTRY_TYPE3 *)warning_header; + process_ewl_type3(warning_header, type3->MemoryLocation); + type3_flag = 1; + } else { + printk(BIOS_DEBUG, "EWL type: %d size:%d severity level:%d\n", + warning_header->Type, + warning_header->Size, + warning_header->Severity); + hexdump(&(hob->status.Buffer[offset]), warning_header->Size); + } + offset += warning_header->Size; + } + if (type3_flag) + die("Memory Training Error!\n"); +} diff --git a/src/drivers/ocp/ewl/ocp_ewl.h b/src/drivers/ocp/ewl/ocp_ewl.h new file mode 100644 index 0000000..38d5286d --- /dev/null +++ b/src/drivers/ocp/ewl/ocp_ewl.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __OCP_EWL_H +#define __OCP_EWL_H + +#include <soc/soc_util.h> + +void get_ewl(void); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/69145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd5b521bafd457505db4147c5d3fe41364a09045 Gerrit-Change-Number: 69145 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add get_ewl_hob() utility function
by Johnny Lin (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Jonathan Zhang, Christian Walter, Arthur Heymans, Tim Chu. Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69144 ) Change subject: soc/intel/xeon_sp/cpx: Add get_ewl_hob() utility function ...................................................................... soc/intel/xeon_sp/cpx: Add get_ewl_hob() utility function Change-Id: I8f949e9c881099c3723fca056e2c4732ca8b64cf Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h M src/soc/intel/xeon_sp/cpx/soc_util.c 3 files changed, 27 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/69144/1 diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index 0cd267b..7e18b92 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -5,7 +5,7 @@ subdirs-y += ../../../../cpu/intel/turbo subdirs-y += ../../../../cpu/intel/microcode -romstage-y += romstage.c ddr.c +romstage-y += romstage.c ddr.c soc_util.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index 5ce3928..c4e2a7d 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -5,11 +5,13 @@ #include <hob_iiouds.h> #include <hob_memmap.h> +#include <hob_enhancedwarningloglib.h> const struct SystemMemoryMapHob *get_system_memory_map(void); uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); int soc_get_stack_for_port(int port); +const EWL_PRIVATE_DATA *get_ewl_hob(void); #endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index cd1e06d..2a8b6c9 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -9,6 +9,20 @@ #include <soc/soc_util.h> #include <soc/util.h> +const EWL_PRIVATE_DATA *get_ewl_hob(void) +{ + size_t hob_size; + static const EWL_PRIVATE_DATA *hob; + const uint8_t ewl_id_hob_guid[16] = FSP_HOB_EWLID_GUID; + + if (hob != NULL) + return hob; + + hob = fsp_find_extension_hob_by_guid(ewl_id_hob_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + return hob; +} + const struct SystemMemoryMapHob *get_system_memory_map(void) { size_t hob_size; -- To view, visit https://review.coreboot.org/c/coreboot/+/69144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f949e9c881099c3723fca056e2c4732ca8b64cf Gerrit-Change-Number: 69144 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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