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Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66909 )
Change subject: vboot: Add VBOOT_CBFS_INTEGRATION support
......................................................................
Patch Set 20:
(4 comments)
File src/security/vboot/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/66909/comment/1f7ae90a_ef5c01bc
PS15, Line 104: bootblock-y += secdata_mock.c
> The parentheses aren't right, that's why you get that error. […]
Oh..... My confusion was caused by incorrect parentheses placement. Now it makes sense. Sorry for that and thank you for help :)
File src/soc/amd/stoneyridge/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/66909/comment/fb5e7000_6d52f6af
PS18, Line 40: postcar-y += i2c.c
> I think you should no longer need this
Done
File src/soc/qualcomm/ipq40xx/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/66909/comment/9b2adb84_ef26b52f
PS18, Line 7: bootblock-y += i2c.c
> and this
Done
File src/soc/qualcomm/ipq806x/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/66909/comment/1cd79ba6_1bb46066
PS18, Line 7: bootblock-y += i2c.c
> and this
Done
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Hello Hung-Te Lin, build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Julius Werner, Fred Reitberger, Yu-Ping Wu, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/66909
to look at the new patch set (#20).
Change subject: vboot: Add VBOOT_CBFS_INTEGRATION support
......................................................................
vboot: Add VBOOT_CBFS_INTEGRATION support
This patch introduces support signing and verification of firmware
slots using CBFS metadata hash verification method for faster initial
verification. To have complete verification, CBFS_VERIFICATION should
also be enabled, as metadata hash covers only files metadata, not their
contents.
This patch also adapts mainboards and SoCs to new vboot reset
requirements.
TEST=Volteer/Voxel boots with CL:3811754
Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com>
Change-Id: I40ae01c477c4e4f7a1c90e4026a8a868ae64b5ca
---
M src/include/cbfs_glue.h
M src/lib/cbfs.c
M src/mainboard/google/asurada/Makefile.inc
M src/mainboard/google/cherry/Makefile.inc
M src/mainboard/google/corsola/Makefile.inc
M src/mainboard/google/geralt/Makefile.inc
M src/security/vboot/Kconfig
M src/security/vboot/Makefile.inc
M src/security/vboot/common.c
M src/security/vboot/vboot_common.c
M src/security/vboot/vboot_common.h
M src/security/vboot/vboot_loader.c
M src/security/vboot/vboot_logic.c
M src/soc/amd/common/psp_verstage/psp_verstage.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/mediatek/mt8173/Makefile.inc
16 files changed, 173 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/66909/20
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Change subject: mb/google/brya/var/lisbon: turn off thunderbolt
......................................................................
Patch Set 1: Code-Review+1
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Change subject: mb/google/brya: Create marasov variant
......................................................................
Patch Set 3: Code-Review+2
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Change subject: cpu/x86: Drop LEGACY_SMP_INIT
......................................................................
Patch Set 15: Code-Review+2
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Change subject: device/resource_allocator_v3: Drop code
......................................................................
Patch Set 2: Code-Review+1
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Change subject: cpu/x86: Set up a separate stack for APs
......................................................................
Patch Set 16:
(1 comment)
File src/cpu/x86/Kconfig:
https://review.coreboot.org/c/coreboot/+/69123/comment/ad90c2c2_217db00b
PS16, Line 214: default 0x200
Could this cause regressions? It feels quite small.
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Change subject: cpu/x86: Drop !CPU_INFO_V2 code
......................................................................
Patch Set 16: Code-Review+2
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