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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68992 )
Change subject: device/dram: Add kconfig options for memory types
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
> Hmmm, another thought: Chipsets can support multiple memory types, but individual boards typically o […]
Update to self: And how do you deal with the build problems? Don't bother for now.
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Change subject: device/dram: Add kconfig options for memory types
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Hmmm, another thought: Chipsets can support multiple memory types, but individual boards typically only support one or two types. Would it be possible for mainboards to unselect support for chipset-supported memory types?
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Hello Hung-Te Lin, Philipp Hug, Jakub Czapiga, Matt DeVillier, Angel Pons, Julius Werner, Andrey Petrov, ron minnich, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69078
to look at the new patch set (#3).
Change subject: cbmem_top_chipset: Change the return value to uintptr_t
......................................................................
cbmem_top_chipset: Change the return value to uintptr_t
Get rid of a lot of casts.
Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/drivers/amd/agesa/romstage.c
M src/drivers/intel/fsp2_0/cbmem.c
M src/include/cbmem.h
M src/lib/imd_cbmem.c
M src/mainboard/emulation/qemu-aarch64/cbmem.c
M src/mainboard/emulation/qemu-armv7/cbmem.c
M src/mainboard/emulation/qemu-i440fx/memmap.c
M src/mainboard/emulation/qemu-power8/cbmem.c
M src/mainboard/emulation/qemu-power9/cbmem.c
M src/northbridge/intel/gm45/memmap.c
M src/northbridge/intel/haswell/memmap.c
M src/northbridge/intel/i440bx/memmap.c
M src/northbridge/intel/i945/memmap.c
M src/northbridge/intel/ironlake/memmap.c
M src/northbridge/intel/pineview/memmap.c
M src/northbridge/intel/sandybridge/memmap.c
M src/northbridge/intel/x4x/memmap.c
M src/soc/amd/stoneyridge/memmap.c
M src/soc/cavium/cn81xx/cbmem.c
M src/soc/intel/baytrail/memmap.c
M src/soc/intel/braswell/memmap.c
M src/soc/intel/broadwell/memmap.c
M src/soc/mediatek/common/cbmem.c
M src/soc/nvidia/tegra124/cbmem.c
M src/soc/nvidia/tegra210/cbmem.c
M src/soc/qualcomm/ipq40xx/cbmem.c
M src/soc/qualcomm/ipq806x/cbmem.c
M src/soc/qualcomm/qcs405/cbmem.c
M src/soc/qualcomm/sc7180/cbmem.c
M src/soc/qualcomm/sc7280/cbmem.c
M src/soc/rockchip/common/cbmem.c
M src/soc/samsung/exynos5250/cbmem.c
M src/soc/samsung/exynos5420/cbmem.c
M src/soc/sifive/fu540/cbmem.c
M src/soc/ti/am335x/cbmem.c
M src/soc/ucb/riscv/cbmem.c
M tests/lib/coreboot_table-test.c
M tests/lib/imd_cbmem-test.c
38 files changed, 89 insertions(+), 79 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/69078/3
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Change subject: soc/amd: Specify memory types supported by each chip
......................................................................
Patch Set 1: Code-Review+1
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Change subject: soc/amd/common: Only call into enabled memory types
......................................................................
Patch Set 1: Code-Review+1
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Change subject: device/dram: Add kconfig options for memory types
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
File src/device/dram/Kconfig:
https://review.coreboot.org/c/coreboot/+/68992/comment/48a8daec_f9943c16
PS1, Line 3: # Short-term plan: Start adding 'USE_' and "NO_" options to each chip.
: #
: # Long-term plan: Every SoC or chipset should select the memory types they
: # use. When they all select their memory, the 'no_' options can be removed
: # and the defaults for all memory types can be set to n.
:
: config NO_DDR5
: bool
:
: config NO_LPDDR4
: bool
:
: config NO_DDR4
: bool
:
: config NO_DDR3
: bool
:
: config NO_DDR2
: bool
OK, so the negative options are temporary. Got it.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68709 )
Change subject: MAINTAINERS: Make Misc Fixes
......................................................................
Patch Set 5:
(1 comment)
File MAINTAINERS:
https://review.coreboot.org/c/coreboot/+/68709/comment/219b55e5_712b9f4f
PS2, Line 697: MAINTAINED
> Yeah - it's hard. I'm not adding anyone's name who isn't volunteering for it. […]
Makes sense, thanks for the explanation.
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Hello Hung-Te Lin, Philipp Hug, Jakub Czapiga, Matt DeVillier, Angel Pons, Julius Werner, Andrey Petrov, ron minnich, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69078
to look at the new patch set (#2).
Change subject: cbmem_top_chipset: Change the return value to uintptr_t
......................................................................
cbmem_top_chipset: Change the return value to uintptr_t
Get rid of a lot of casts.
Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/drivers/amd/agesa/romstage.c
M src/drivers/intel/fsp2_0/cbmem.c
M src/include/cbmem.h
M src/lib/imd_cbmem.c
M src/mainboard/emulation/qemu-aarch64/cbmem.c
M src/mainboard/emulation/qemu-armv7/cbmem.c
M src/mainboard/emulation/qemu-i440fx/memmap.c
M src/mainboard/emulation/qemu-power8/cbmem.c
M src/mainboard/emulation/qemu-power9/cbmem.c
M src/northbridge/intel/gm45/memmap.c
M src/northbridge/intel/haswell/memmap.c
M src/northbridge/intel/i440bx/memmap.c
M src/northbridge/intel/i945/memmap.c
M src/northbridge/intel/ironlake/memmap.c
M src/northbridge/intel/pineview/memmap.c
M src/northbridge/intel/sandybridge/memmap.c
M src/northbridge/intel/x4x/memmap.c
M src/soc/amd/stoneyridge/memmap.c
M src/soc/cavium/cn81xx/cbmem.c
M src/soc/intel/baytrail/memmap.c
M src/soc/intel/braswell/memmap.c
M src/soc/intel/broadwell/memmap.c
M src/soc/mediatek/common/cbmem.c
M src/soc/nvidia/tegra124/cbmem.c
M src/soc/nvidia/tegra210/cbmem.c
M src/soc/qualcomm/ipq40xx/cbmem.c
M src/soc/qualcomm/ipq806x/cbmem.c
M src/soc/qualcomm/qcs405/cbmem.c
M src/soc/qualcomm/sc7180/cbmem.c
M src/soc/qualcomm/sc7280/cbmem.c
M src/soc/rockchip/common/cbmem.c
M src/soc/samsung/exynos5250/cbmem.c
M src/soc/samsung/exynos5420/cbmem.c
M src/soc/sifive/fu540/cbmem.c
M src/soc/ti/am335x/cbmem.c
M src/soc/ucb/riscv/cbmem.c
M tests/lib/coreboot_table-test.c
M tests/lib/imd_cbmem-test.c
38 files changed, 89 insertions(+), 79 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/69078/2
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69162 )
Change subject: security/tpm: support compiling in multiple TPM drivers
......................................................................
Patch Set 1:
(2 comments)
File src/security/tpm/tis.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162139):
https://review.coreboot.org/c/coreboot/+/69162/comment/7a4e6fa4_303a91dd
PS1, Line 101: #define __tis_driver __attribute__((used, __section__(".rodata.tis_driver")))
Prefer __used over __attribute__((used))
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162139):
https://review.coreboot.org/c/coreboot/+/69162/comment/7a619fca_b1bd57a0
PS1, Line 101: #define __tis_driver __attribute__((used, __section__(".rodata.tis_driver")))
Prefer __section(".rodata.tis_driver") over __attribute__((__section__(".rodata.tis_driver")))
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