coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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7286 discussions

[M] Change in coreboot[master]: cbmem_top_chipset: Change the return value to uintptr_t
by Jakub Czapiga (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Hung-Te Lin, Philipp Hug, Matt DeVillier, Angel Pons, Julius Werner, Andrey Petrov, ron minnich, Elyes Haouas, Felix Held. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69078 ) Change subject: cbmem_top_chipset: Change the return value to uintptr_t ...................................................................... Patch Set 4: (2 comments) File src/lib/imd_cbmem.c: https://review.coreboot.org/c/coreboot/+/69078/comment/6d9411c0_6168ae4b PS4, Line 21: uintptr_t top; It should be static File src/northbridge/intel/i440bx/memmap.c: https://review.coreboot.org/c/coreboot/+/69078/comment/05a1a3fe_da22ef3d PS1, Line 48: int tseg_size = 128 * KiB * (1 << (tseg >> 1)); : tom -= tseg_size; > If anything, this belongs to a follow-up. I assume it works with ints here, so there should be no problems. I agree a potential fix should be in follow-up patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/69078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Gerrit-Change-Number: 69078 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 02 Nov 2022 13:42:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/sandybridge: Specify supported memory types
by Angel Pons (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Elyes Haouas. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69019 ) Change subject: nb/intel/sandybridge: Specify supported memory types ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/northbridge/intel/sandybridge/Kconfig: https://review.coreboot.org/c/coreboot/+/69019/comment/ada0ba60_cc61e289 PS1, Line 18: select USE_DDR3 Why not select these from `config NORTHBRIDGE_INTEL_SANDYBRIDGE` instead? -- To view, visit https://review.coreboot.org/c/coreboot/+/69019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie43e818d03f411733e1bba5b7a4721c9a54ff4a4 Gerrit-Change-Number: 69019 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 02 Nov 2022 13:41:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/gm45: Specify supported memory types
by Angel Pons (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Elyes Haouas. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68997 ) Change subject: nb/intel/gm45: Specify supported memory types ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/northbridge/intel/gm45/Kconfig: https://review.coreboot.org/c/coreboot/+/68997/comment/ed01bb95_2231b0fc PS1, Line 20: select USE_DDR2 Not yet supported, but there are WIP patches: https://review.coreboot.org/q/hashtag:gm45_ddr2 This is fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/68997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a3a45a1a36ea6ad0b8fb2d3ee78add0b38460ac Gerrit-Change-Number: 68997 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 02 Nov 2022 13:41:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cbmem_top_chipset: Change the return value to uintptr_t
by Elyes Haouas (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Hung-Te Lin, Philipp Hug, Jakub Czapiga, Matt DeVillier, Julius Werner, Andrey Petrov, ron minnich, Elyes Haouas, Felix Held. Hello Hung-Te Lin, Philipp Hug, Jakub Czapiga, Matt DeVillier, Angel Pons, Julius Werner, Andrey Petrov, ron minnich, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69078 to look at the new patch set (#4). Change subject: cbmem_top_chipset: Change the return value to uintptr_t ...................................................................... cbmem_top_chipset: Change the return value to uintptr_t Get rid of a lot of casts. Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/drivers/amd/agesa/romstage.c M src/drivers/intel/fsp2_0/cbmem.c M src/include/cbmem.h M src/lib/imd_cbmem.c M src/mainboard/emulation/qemu-aarch64/cbmem.c M src/mainboard/emulation/qemu-armv7/cbmem.c M src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-power8/cbmem.c M src/mainboard/emulation/qemu-power9/cbmem.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/ironlake/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/soc/amd/stoneyridge/memmap.c M src/soc/cavium/cn81xx/cbmem.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/braswell/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/mediatek/common/cbmem.c M src/soc/nvidia/tegra124/cbmem.c M src/soc/nvidia/tegra210/cbmem.c M src/soc/nvidia/tegra210/ramstage.c M src/soc/qualcomm/ipq40xx/cbmem.c M src/soc/qualcomm/ipq806x/cbmem.c M src/soc/qualcomm/qcs405/cbmem.c M src/soc/qualcomm/sc7180/cbmem.c M src/soc/qualcomm/sc7280/cbmem.c M src/soc/rockchip/common/cbmem.c M src/soc/samsung/exynos5250/cbmem.c M src/soc/samsung/exynos5420/cbmem.c M src/soc/sifive/fu540/cbmem.c M src/soc/ti/am335x/cbmem.c M src/soc/ucb/riscv/cbmem.c M tests/lib/coreboot_table-test.c M tests/lib/imd_cbmem-test.c 39 files changed, 90 insertions(+), 80 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/69078/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/69078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Gerrit-Change-Number: 69078 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: nb/intel/i945: Specify supported memory type
by Angel Pons (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Elyes Haouas. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68996 ) Change subject: nb/intel/i945: Specify supported memory type ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cc2a9786dfb1f8fb1ec8e78bde7c46c07f8da48 Gerrit-Change-Number: 68996 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 02 Nov 2022 13:39:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: device/dram: Add kconfig options for memory types
by Angel Pons (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Martin L Roth. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68992 ) Change subject: device/dram: Add kconfig options for memory types ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: > Hmmm, another thought: Chipsets can support multiple memory types, but individual boards typically o […] Update to self: And how do you deal with the build problems? Don't bother for now. -- To view, visit https://review.coreboot.org/c/coreboot/+/68992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c98a702e0d67c5ad7bd9b8a4ff24c9288ab569 Gerrit-Change-Number: 68992 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Wed, 02 Nov 2022 13:39:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: device/dram: Add kconfig options for memory types
by Angel Pons (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Martin L Roth. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68992 ) Change subject: device/dram: Add kconfig options for memory types ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Hmmm, another thought: Chipsets can support multiple memory types, but individual boards typically only support one or two types. Would it be possible for mainboards to unselect support for chipset-supported memory types? -- To view, visit https://review.coreboot.org/c/coreboot/+/68992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c98a702e0d67c5ad7bd9b8a4ff24c9288ab569 Gerrit-Change-Number: 68992 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Wed, 02 Nov 2022 13:38:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cbmem_top_chipset: Change the return value to uintptr_t
by Elyes Haouas (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Hung-Te Lin, Philipp Hug, Jakub Czapiga, Matt DeVillier, Julius Werner, Andrey Petrov, ron minnich, Elyes Haouas, Felix Held. Hello Hung-Te Lin, Philipp Hug, Jakub Czapiga, Matt DeVillier, Angel Pons, Julius Werner, Andrey Petrov, ron minnich, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69078 to look at the new patch set (#3). Change subject: cbmem_top_chipset: Change the return value to uintptr_t ...................................................................... cbmem_top_chipset: Change the return value to uintptr_t Get rid of a lot of casts. Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/drivers/amd/agesa/romstage.c M src/drivers/intel/fsp2_0/cbmem.c M src/include/cbmem.h M src/lib/imd_cbmem.c M src/mainboard/emulation/qemu-aarch64/cbmem.c M src/mainboard/emulation/qemu-armv7/cbmem.c M src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-power8/cbmem.c M src/mainboard/emulation/qemu-power9/cbmem.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/ironlake/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/soc/amd/stoneyridge/memmap.c M src/soc/cavium/cn81xx/cbmem.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/braswell/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/mediatek/common/cbmem.c M src/soc/nvidia/tegra124/cbmem.c M src/soc/nvidia/tegra210/cbmem.c M src/soc/qualcomm/ipq40xx/cbmem.c M src/soc/qualcomm/ipq806x/cbmem.c M src/soc/qualcomm/qcs405/cbmem.c M src/soc/qualcomm/sc7180/cbmem.c M src/soc/qualcomm/sc7280/cbmem.c M src/soc/rockchip/common/cbmem.c M src/soc/samsung/exynos5250/cbmem.c M src/soc/samsung/exynos5420/cbmem.c M src/soc/sifive/fu540/cbmem.c M src/soc/ti/am335x/cbmem.c M src/soc/ucb/riscv/cbmem.c M tests/lib/coreboot_table-test.c M tests/lib/imd_cbmem-test.c 38 files changed, 89 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/69078/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Gerrit-Change-Number: 69078 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd: Specify memory types supported by each chip
by Angel Pons (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Fred Reitberger, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68994 ) Change subject: soc/amd: Specify memory types supported by each chip ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c7f47b43d8d4a89630fbd645a725e61d74bc2a5 Gerrit-Change-Number: 68994 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 02 Nov 2022 13:37:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/common: Only call into enabled memory types
by Angel Pons (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Fred Reitberger, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68993 ) Change subject: soc/amd/common: Only call into enabled memory types ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie239039b3dd2b5d0a6f8e9230fd3466bb8309761 Gerrit-Change-Number: 68993 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 02 Nov 2022 13:37:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2022