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Change subject: mb/ocp/deltalake: Add EWL Hob processing for MRC error
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69146/comment/ad50a223_474e6916
PS1, Line 9: Override the weak function mainboard_ewl_check() and
> 'disble' may be misspelled - perhaps 'disable'?
Please fix.
https://review.coreboot.org/c/coreboot/+/69146/comment/ecd7ea01_72970474
PS1, Line 10: The Intel FSP needs to disble promote
: MRC Warnings
Is this an UPD? Where is it set?
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Change subject: drivers/ocp/ewl: Add EWL driver for EWL type 3 error handling
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Patch Set 1: Code-Review+1
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Change subject: soc/intel/xeon_sp/cpx: Add get_ewl_hob() utility function
......................................................................
Patch Set 1: Code-Review+1
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Change subject: soc/xeon_sp: Add weak mainboard_ewl_check for EWL check after FSP-M
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Change subject: vc/intel/fsp/fsp2_0/cpx: Add Enhanced Warning Log hob header
......................................................................
Patch Set 1:
(2 comments)
File src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/EnhancedWarningLogLib.h:
https://review.coreboot.org/c/coreboot/+/69142/comment/83ebe5f2_771f180e
PS1, Line 5: INTEL CONFIDENTIAL
Hmmmmm, is this license header correct?
File src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_enhancedwarningloglib.h:
https://review.coreboot.org/c/coreboot/+/69142/comment/68c26007_b55dce2a
PS1, Line 5: INTEL CONFIDENTIAL
Hmmmmm, is this license header correct?
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Change subject: soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill
......................................................................
Patch Set 5:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68525/comment/5648dc52_b513571a
PS3, Line 14: Furthermore, function dimm_info_fill()
: was adjusted.
> How about: […]
Done
https://review.coreboot.org/c/coreboot/+/68525/comment/bd5881bb_727949fb
PS3, Line 17: ATLAS
> nit: Mainboard Kconfig capitalizes only the first letter of `Atlas`
Done
https://review.coreboot.org/c/coreboot/+/68525/comment/86e304c8_8d82800d
PS3, Line 25: RVP board.
> Maybe elaborate a bit more? […]
Done
File src/include/memory_info.h:
https://review.coreboot.org/c/coreboot/+/68525/comment/2df7926f_e38e2965
PS4, Line 96: * Node-ID / Memory-Controller-ID
> Yes, similar like on the server side, the hierarchy is socket/controller/channel/DIMM.
Done
File src/include/memory_info.h:
https://review.coreboot.org/c/coreboot/+/68525/comment/5aa2c90f_32846c58
PS3, Line 98: uint8_t node_num;
> It's just a data struct, so there's no problem if the offsets change. […]
Done
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Hello build bot (Jenkins), Jonathan Zhang, weidong.wd(a)bytedance.com, Angel Pons, Arthur Heymans, TangYiwei, Andrey Petrov, Tarun Tuli, Anjaneya "Reddy" Chagam, Subrata Banik, Johnny Lin, Kapil Porwal, Christian Walter, Tim Wawrzynczak, Lean Sheng Tan, Werner Zeh, Tim Chu,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill
......................................................................
soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill
The dimm_info structure (defined in src/include/memory_info.h)
currently does not hold information about the DIMM's
node/controller ID.
This patch extends the dimm_info structure by adding a new field for
the node ID, called node_num. Also, adapt the dimm_info_fill()
function accordingly to populate the newly-added field.
Background: These changes are necessary for the Atlas mainboard, where
we are currently experiencing issues with the DIMMs device/bank
locator. Our 2 DIMMs share the same CHANNEL and DIMM ID but have a
distinct NODE ID. By looking at the smbios table we see
Channel-0-DIMM-0 for both DIMMs. Thus, we need their NODE IDs in order
to distinguish them.
This patch was tested by building and booting for the Alderlake-P
RVP board, which has the same DIMM slot configuration as the
Prodrive Atlas mainboard.
Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com>
Change-Id: I6ffa5bdff0ba0e3c4a4a51f2419291fd1278cd68
---
M src/include/memory_info.h
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/apollolake/meminit_util_apl.c
M src/soc/intel/apollolake/meminit_util_glk.c
M src/soc/intel/cannonlake/romstage/romstage.c
M src/soc/intel/common/smbios.c
M src/soc/intel/common/smbios.h
M src/soc/intel/elkhartlake/romstage/romstage.c
M src/soc/intel/icelake/romstage/romstage.c
M src/soc/intel/jasperlake/romstage/romstage.c
M src/soc/intel/meteorlake/romstage/romstage.c
M src/soc/intel/skylake/romstage/romstage.c
M src/soc/intel/tigerlake/romstage/romstage.c
M src/soc/intel/xeon_sp/cpx/romstage.c
14 files changed, 65 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/68525/5
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Change subject: cbmem_top_chipset: Change the return value to uintptr_t
......................................................................
Patch Set 4:
(4 comments)
Patchset:
PS4:
Thank you.
File src/northbridge/intel/x4x/memmap.c:
https://review.coreboot.org/c/coreboot/+/69078/comment/091e3b03_e97ca0a1
PS1, Line 76: uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
: return top_of_ram;
> +1, there are other occurrences in other Intel platforms. Could be done in a follow-up.
Done
File src/soc/nvidia/tegra124/cbmem.c:
https://review.coreboot.org/c/coreboot/+/69078/comment/082426b9_d91d2a13
PS1, Line 9: return ((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL);
> nit: Outer set of parentheses is now unnecessary
Done
File src/soc/sifive/fu540/cbmem.c:
https://review.coreboot.org/c/coreboot/+/69078/comment/d9a9261f_5e5eea76
PS1, Line 11: return MIN((uintptr_t)_dram + sdram_size_mb() * MiB,
: FU540_MAXDRAM);
> nit: Can it fit in one line?
Done
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