coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: Makefile.inc: Decrease minimal pagesize from 4 kB to 1 kB
by Angel Pons (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Nico Huber, Martin L Roth, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62830 ) Change subject: Makefile.inc: Decrease minimal pagesize from 4 kB to 1 kB ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS2: > It’d be great if somebody submitted this. Needs to pass Jenkins, apparently the builders don't know about the option. We might need to guard it for older GCC versions. -- To view, visit https://review.coreboot.org/c/coreboot/+/62830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e36633f42cb4dc5af53212c10c919a86e451ee0 Gerrit-Change-Number: 62830 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 02 Nov 2022 14:22:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: drivers/ocp/ewl: Set CMOS flag to enforce MRC when there's EWL type3 ...
by Angel Pons (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Johnny Lin. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69148 ) Change subject: drivers/ocp/ewl: Set CMOS flag to enforce MRC when there's EWL type3 error ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69148/comment/c273e4e8_686ead94 PS2, Line 12: Reference CPX change https://review.coreboot.org/c/coreboot/+/51230 How about: See commit 95059b705500f4a7061bb3e8ea1e2fd01a3abde1 for the reference CPX change. -- To view, visit https://review.coreboot.org/c/coreboot/+/69148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dee0472f8e2602cecf88c6d00dec0bf02b9f7bd Gerrit-Change-Number: 69148 Gerrit-PatchSet: 2 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Comment-Date: Wed, 02 Nov 2022 14:20:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/ocp/ewl: Add sending Meta's BMC SEL for memory training error
by Angel Pons (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Johnny Lin. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69147 ) Change subject: drivers/ocp/ewl: Add sending Meta's BMC SEL for memory training error ...................................................................... Patch Set 2: Code-Review+1 (2 comments) File src/drivers/ipmi/ocp/ipmi_ocp.h: https://review.coreboot.org/c/coreboot/+/69147/comment/3cfbb223_9118db79 PS2, Line 195: #define INTEL_MEMORY_ERROR 0x21 nit: place this so that the macro numbers are in ascending order? File src/drivers/ocp/ewl/ewl.c: https://review.coreboot.org/c/coreboot/+/69147/comment/8278f2bd_4ffac686 PS2, Line 12: = 0xff Unused assignment -- To view, visit https://review.coreboot.org/c/coreboot/+/69147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I664e9d3da7910b47260881c0df64159c8dbe2dca Gerrit-Change-Number: 69147 Gerrit-PatchSet: 2 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Comment-Date: Wed, 02 Nov 2022 14:19:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: payloads/cbui: Add new payload CBUI
by Iman Bingi (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Iman Bingi, Martin L Roth, Julius Werner, Patrick Rudolph. Iman Bingi has uploaded a new patch set (#199) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/23586 ) Change subject: payloads/cbui: Add new payload CBUI ...................................................................... payloads/cbui: Add new payload CBUI Depends on libpayload and nuklear. Features: * Graphical menus with scrolling. * Text rendering engine (atm only bitmap font) * Support for keyboard and mouse * Support for USB and PS/2 devices * Ported coreinfo and nvramcui * Allows to modify NVRAM and RTC * Works as ELF payload * Works as Seabios secondary payload * Basic support for multiple languages * Hacky support for BIOS calls (depends on NASM) * Runs in qemu and on real hardware * Use linker script to allocate low memory Shortcomings: * Doesn't work in VGA text mode * Untested on UEFI * int32 relocates itself to low memory Licenses: * GPLv2 (CBUI + libpayload) * BSD (libpayload) * MIT (nuklear) TODO: * Test on as much platforms as possible * Link int32 into low memory This is Patrick Rudolph's original patch, updated by Ben Adu-Boahen to: * Add Read/Write module * This module allows read/write to any hardware component that is readable/writeable Note: This is work in progress Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Signed-off-by: Ben Adu-Boahen <imanbingy(a)gmail.com> --- M payloads/Kconfig M payloads/Makefile.inc A payloads/cbui/.gitignore A payloads/cbui/Kconfig A payloads/cbui/Makefile A payloads/cbui/NuklearUI/NuklearCheckbox.c A payloads/cbui/NuklearUI/NuklearCheckbox.h A payloads/cbui/NuklearUI/NuklearCombo.c A payloads/cbui/NuklearUI/NuklearCombo.h A payloads/cbui/NuklearUI/NuklearCommon.h A payloads/cbui/NuklearUI/NuklearDataGrid.c A payloads/cbui/NuklearUI/NuklearDataGrid.h A payloads/cbui/NuklearUI/NuklearDatePicker.c A payloads/cbui/NuklearUI/NuklearDatePicker.h A payloads/cbui/NuklearUI/NuklearFieldFile.c A payloads/cbui/NuklearUI/NuklearFieldFile.h A payloads/cbui/NuklearUI/NuklearFieldHex.c A payloads/cbui/NuklearUI/NuklearFieldHex.h A payloads/cbui/NuklearUI/NuklearFileChooser.c A payloads/cbui/NuklearUI/NuklearFileChooser.h A payloads/cbui/NuklearUI/NuklearGroup.c A payloads/cbui/NuklearUI/NuklearGroup.h A payloads/cbui/NuklearUI/NuklearHex.c A payloads/cbui/NuklearUI/NuklearHex.h A payloads/cbui/NuklearUI/NuklearIntegerRange.c A payloads/cbui/NuklearUI/NuklearIntegerRange.h A payloads/cbui/NuklearUI/NuklearLabel.c A payloads/cbui/NuklearUI/NuklearLabel.h A payloads/cbui/NuklearUI/NuklearObject.c A payloads/cbui/NuklearUI/NuklearObject.h A payloads/cbui/NuklearUI/NuklearRW.c A payloads/cbui/NuklearUI/NuklearRW.h A payloads/cbui/NuklearUI/NuklearRoot.c A payloads/cbui/NuklearUI/NuklearRwAcpi.c A payloads/cbui/NuklearUI/NuklearRwAcpi.h A payloads/cbui/NuklearUI/NuklearRwAtaAtapi.c A payloads/cbui/NuklearUI/NuklearRwAtaAtapi.h A payloads/cbui/NuklearUI/NuklearRwDimmSpd.c A payloads/cbui/NuklearUI/NuklearRwDimmSpd.h A payloads/cbui/NuklearUI/NuklearRwEc.c A payloads/cbui/NuklearUI/NuklearRwEc.h A payloads/cbui/NuklearUI/NuklearRwIo.c A payloads/cbui/NuklearUI/NuklearRwIo.h A payloads/cbui/NuklearUI/NuklearRwIoIndexData.c A payloads/cbui/NuklearUI/NuklearRwIoIndexData.h A payloads/cbui/NuklearUI/NuklearRwMemory.c A payloads/cbui/NuklearUI/NuklearRwMemory.h A payloads/cbui/NuklearUI/NuklearRwMemoryIndexData.c A payloads/cbui/NuklearUI/NuklearRwMemoryIndexData.h A payloads/cbui/NuklearUI/NuklearRwNvram.c A payloads/cbui/NuklearUI/NuklearRwNvram.h A payloads/cbui/NuklearUI/NuklearRwPci.c A payloads/cbui/NuklearUI/NuklearRwPci.h A payloads/cbui/NuklearUI/NuklearRwPciIndexData.c A payloads/cbui/NuklearUI/NuklearRwPciIndexData.h A payloads/cbui/NuklearUI/NuklearRwSmbios.c A payloads/cbui/NuklearUI/NuklearRwSmbios.h A payloads/cbui/NuklearUI/NuklearRwSuperIo.c A payloads/cbui/NuklearUI/NuklearRwSuperIo.h A payloads/cbui/NuklearUI/NuklearStyle.c A payloads/cbui/NuklearUI/NuklearStyle.h A payloads/cbui/NuklearUI/NuklearTabView.c A payloads/cbui/NuklearUI/NuklearTextView.c A payloads/cbui/NuklearUI/NuklearTextView.h A payloads/cbui/NuklearUI/NuklearTextfield.c A payloads/cbui/NuklearUI/NuklearTextfield.h A payloads/cbui/NuklearUI/NuklearTimePicker.c A payloads/cbui/NuklearUI/NuklearTimePicker.h A payloads/cbui/NuklearUI/NuklearUI.h A payloads/cbui/NuklearUI/NuklearVector.c A payloads/cbui/NuklearUI/NuklearVector.h A payloads/cbui/arch/x86/cpuid.c A payloads/cbui/arch/x86/cpuid.h A payloads/cbui/arch/x86/int32.h A payloads/cbui/arch/x86/int32.ld A payloads/cbui/arch/x86/int32.nasm A payloads/cbui/arch/x86/memcpy.c A payloads/cbui/arch/x86/memcpy.h A payloads/cbui/arch/x86/vga.c A payloads/cbui/arch/x86/vga.h A payloads/cbui/cbui.c A payloads/cbui/cbui.h A payloads/cbui/fsys/usbstorage.c A payloads/cbui/fsys/usbstorage.h A payloads/cbui/gfx/coreboot.c A payloads/cbui/gfx/coreboot.h A payloads/cbui/gfx/gfx.c A payloads/cbui/gfx/gfx.h A payloads/cbui/gfx/splash.c A payloads/cbui/gfx/splash.h A payloads/cbui/gfx/vbe.c A payloads/cbui/gfx/vbe.h A payloads/cbui/lang/de.c A payloads/cbui/lang/en.c A payloads/cbui/lang/lang.c A payloads/cbui/lang/lang.h A payloads/cbui/logo/cbui.png A payloads/cbui/lp.config A payloads/cbui/modules/bootlog_module.c A payloads/cbui/modules/cbfs_module.c A payloads/cbui/modules/cmos_module.c A payloads/cbui/modules/coreboot_module.c A payloads/cbui/modules/cpuinfo_module.c A payloads/cbui/modules/license_module.c A payloads/cbui/modules/modules.c A payloads/cbui/modules/modules.h A payloads/cbui/modules/nvram_module.c A payloads/cbui/modules/pci_module.c A payloads/cbui/modules/reboot_module.c A payloads/cbui/modules/rtc_module.c A payloads/cbui/modules/rw_module.c A payloads/cbui/modules/timestamps_module.c A payloads/cbui/modules/usb_module.c A payloads/cbui/smbios/smbios.c A payloads/cbui/smbios/smbios.h A payloads/cbui/smbios/smbios_oem.c A payloads/cbui/smbios/smbios_oem.h A payloads/cbui/smbios/smbios_output.c A payloads/cbui/smbios/smbios_output.h A payloads/cbui/util/stringbuffer.c A payloads/cbui/util/stringbuffer.h A payloads/libpayload/configs/defconfig-cbui 122 files changed, 25,179 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/23586/199 -- To view, visit https://review.coreboot.org/c/coreboot/+/23586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1 Gerrit-Change-Number: 23586 Gerrit-PatchSet: 199 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/ocp/deltalake: Add EWL Hob processing for MRC error
by Angel Pons (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Tim Chu, Shelly Chang. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69146 ) Change subject: mb/ocp/deltalake: Add EWL Hob processing for MRC error ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4419ef43815f8181af89c49514a69bdb29858c13 Gerrit-Change-Number: 69146 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Comment-Date: Wed, 02 Nov 2022 14:17:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/ocp/deltalake: Add EWL Hob processing for MRC error
by Angel Pons (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Tim Chu, Shelly Chang. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69146 ) Change subject: mb/ocp/deltalake: Add EWL Hob processing for MRC error ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69146/comment/ad50a223_474e6916 PS1, Line 9: Override the weak function mainboard_ewl_check() and > 'disble' may be misspelled - perhaps 'disable'? Please fix. https://review.coreboot.org/c/coreboot/+/69146/comment/ecd7ea01_72970474 PS1, Line 10: The Intel FSP needs to disble promote : MRC Warnings Is this an UPD? Where is it set? -- To view, visit https://review.coreboot.org/c/coreboot/+/69146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4419ef43815f8181af89c49514a69bdb29858c13 Gerrit-Change-Number: 69146 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Comment-Date: Wed, 02 Nov 2022 14:17:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/ocp/ewl: Add EWL driver for EWL type 3 error handling
by Angel Pons (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Johnny Lin, Shelly Chang. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69145 ) Change subject: drivers/ocp/ewl: Add EWL driver for EWL type 3 error handling ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd5b521bafd457505db4147c5d3fe41364a09045 Gerrit-Change-Number: 69145 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Comment-Date: Wed, 02 Nov 2022 14:15:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cbmem_top: Change the return value to uintptr_t
by Elyes Haouas (Code Review) 02 Nov '22

02 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69163 ) Change subject: cbmem_top: Change the return value to uintptr_t ...................................................................... cbmem_top: Change the return value to uintptr_t Get rid of a lot of casts. Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/drivers/amd/agesa/mtrr_fixme.c M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp2_0/hob_verify.c M src/include/cbmem.h M src/lib/imd_cbmem.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/ironlake/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/northbridge/intel/x4x/northbridge.c M src/soc/amd/cezanne/root_complex.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/morgana/root_complex.c M src/soc/amd/picasso/root_complex.c M src/soc/amd/stoneyridge/memmap.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/common/block/systemagent/memmap.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/quark/northcluster.c M src/soc/intel/xeon_sp/memmap.c M src/soc/intel/xeon_sp/uncore.c 34 files changed, 53 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/69163/1 diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index 3aef898..bc72458 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -45,7 +45,7 @@ * writeback possible. */ - uintptr_t top_of_ram = (uintptr_t)cbmem_top(); + uintptr_t top_of_ram = cbmem_top(); top_of_ram = ALIGN_UP(top_of_ram, 4 * MiB); set_range_uc(top_of_ram - 4 * MiB, 4 * MiB); @@ -79,7 +79,7 @@ * speed make them WB after CAR teardown. */ if (s3resume) { - uintptr_t top_of_ram = (uintptr_t)cbmem_top(); + uintptr_t top_of_ram = cbmem_top(); top_of_ram = ALIGN_DOWN(top_of_ram, 4 * MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 4 * MiB, 4 * MiB, diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index fc05b91..e9bfafa 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -17,7 +17,7 @@ /* Cache at least 8 MiB below the top of ram, and at most 8 MiB * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); } diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c index ec526e8..c0ee2b8 100644 --- a/src/drivers/intel/fsp2_0/hob_verify.c +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -43,7 +43,7 @@ die("Space between FSP reserved region and BIOS TOLUM!\n"); } - if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) { + if (range_entry_end(&tolum) != cbmem_top()) { printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %p: cbmem_top\n", range_entry_end(&tolum), cbmem_top()); die("Space between cbmem_top and BIOS TOLUM!\n"); diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 911291a..6e8f33a 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -57,7 +57,7 @@ /* The assumption is made that the result of cbmem_top_romstage fits in the size of uintptr_t in the ramstage. */ extern uintptr_t _cbmem_top_ptr; -void *cbmem_top(void); +uintptr_t cbmem_top(void); /* With CONFIG_RAMSTAGE_CBMEM_TOP_ARG set, the result of cbmem_top is passed via * calling arguments to the next stage and saved in the global _cbmem_top_ptr * global variable. Only a romstage callback needs to be implemented by the diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 91c8621..9c01f12 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -15,17 +15,17 @@ static struct imd imd; -void *cbmem_top(void) +uintptr_t cbmem_top(void) { if (ENV_CREATES_CBMEM) { static uintptr_t top; if (top) - return (void *)top; + return top; top = cbmem_top_chipset(); - return (void *)top; + return top; } if (ENV_POSTCAR || ENV_RAMSTAGE) - return (void *)_cbmem_top_ptr; + return _cbmem_top_ptr; dead_code(); } @@ -55,7 +55,7 @@ /* The test is only effective on X86 and when address hits UC memory. */ if (ENV_X86) - quick_ram_check_or_die((uintptr_t)cbmem_top() - sizeof(u32)); + quick_ram_check_or_die(cbmem_top() - sizeof(u32)); } void cbmem_initialize_empty_id_size(u32 id, u64 size) diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 2ba7c80..74bda32 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -123,7 +123,7 @@ /* Cache 8 MiB region below the top of RAM and 2 MiB above top of * RAM to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index df5526c..cf289b9 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -93,7 +93,7 @@ /* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tomk as unusable */ - delta_cbmem = tomk - ((uintptr_t)cbmem_top() >> 10); + delta_cbmem = tomk - (cbmem_top() >> 10); tomk -= delta_cbmem; uma_sizek += delta_cbmem; diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 6b75caa..c786dc9 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -75,6 +75,6 @@ * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8 * MiB); + top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c index 5cee1b4..fb79868 100644 --- a/src/northbridge/intel/i440bx/memmap.c +++ b/src/northbridge/intel/i440bx/memmap.c @@ -56,7 +56,7 @@ uintptr_t top_of_ram; /* Cache CBMEM region as WB. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 96dee76..af23c5f 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -87,7 +87,7 @@ /* Cache 8 MiB region below the top of RAM and 2 MiB above top of * RAM to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 3c5603c..41accab 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -62,7 +62,7 @@ /* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tomk as unusable */ - cbmem_topk = ((uintptr_t)cbmem_top() / KiB); + cbmem_topk = (cbmem_top() / KiB); delta_cbmem = tomk_stolen - cbmem_topk; tomk_stolen -= delta_cbmem; diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c index bdb76c1..e089144 100644 --- a/src/northbridge/intel/ironlake/memmap.c +++ b/src/northbridge/intel/ironlake/memmap.c @@ -41,7 +41,7 @@ * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index 55d7046..f43120c 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -93,7 +93,7 @@ * Cache 8 MiB region below the top of RAM and 2 MiB above top of RAM to cover both * CBMEM and the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index ac95ab5..e99f2ee 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -67,7 +67,7 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram = (uintptr_t)cbmem_top(); + uintptr_t top_of_ram = cbmem_top(); /* * Cache 8MiB below the top of ram. On sandybridge systems the top of diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index 0b085cf..4aa2a33 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -89,7 +89,7 @@ /* Cache 8 MiB region below the top of RAM and 2 MiB above top of * RAM to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index ac276b6..74226bc 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -70,7 +70,7 @@ /* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tomk as unusable */ - delta_cbmem = tomk - ((uintptr_t)cbmem_top() >> 10); + delta_cbmem = tomk - (cbmem_top() >> 10); tomk -= delta_cbmem; uma_sizek += delta_cbmem; diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index ed919b1..cec0626 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -101,7 +101,7 @@ */ static void read_resources(struct device *dev) { - uint32_t mem_usable = (uintptr_t)cbmem_top(); + uintptr_t mem_usable = cbmem_top(); unsigned int idx = 0; const struct hob_header *hob = fsp_get_hob_list(); const struct hob_resource *res; diff --git a/src/soc/amd/glinda/root_complex.c b/src/soc/amd/glinda/root_complex.c index ef6c630..d088022 100644 --- a/src/soc/amd/glinda/root_complex.c +++ b/src/soc/amd/glinda/root_complex.c @@ -116,7 +116,7 @@ */ static void read_resources(struct device *dev) { - uint32_t mem_usable = (uintptr_t)cbmem_top(); + uintptr_t mem_usable = cbmem_top(); unsigned int idx = 0; const struct hob_header *hob = fsp_get_hob_list(); const struct hob_resource *res; diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 6768613..24edd0f7 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -116,7 +116,7 @@ */ static void read_resources(struct device *dev) { - uint32_t mem_usable = (uintptr_t)cbmem_top(); + uintptr_t mem_usable = cbmem_top(); unsigned int idx = 0; const struct hob_header *hob = fsp_get_hob_list(); const struct hob_resource *res; diff --git a/src/soc/amd/morgana/root_complex.c b/src/soc/amd/morgana/root_complex.c index 88bcca7..b0fdced 100644 --- a/src/soc/amd/morgana/root_complex.c +++ b/src/soc/amd/morgana/root_complex.c @@ -116,7 +116,7 @@ */ static void read_resources(struct device *dev) { - uint32_t mem_usable = (uintptr_t)cbmem_top(); + uintptr_t mem_usable = cbmem_top(); unsigned int idx = 0; const struct hob_header *hob = fsp_get_hob_list(); const struct hob_resource *res; diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index d53643e..247ca1f 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -101,7 +101,7 @@ */ static void read_resources(struct device *dev) { - uint32_t mem_usable = (uintptr_t)cbmem_top(); + uintptr_t mem_usable = cbmem_top(); unsigned int idx = 0; const struct hob_header *hob = fsp_get_hob_list(); const struct hob_resource *res; diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 8de3515..176b7e9 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -26,7 +26,7 @@ static uintptr_t smm_region_start(void) { - return (uintptr_t)cbmem_top(); + return cbmem_top(); } static size_t smm_region_size(void) diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 7e93896..c1adf33 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -376,7 +376,7 @@ { uint64_t uma_base = get_uma_base(); uint32_t uma_size = get_uma_size(); - uint32_t mem_useable = (uintptr_t)cbmem_top(); + uintptr_t mem_useable = cbmem_top(); msr_t tom = rdmsr(TOP_MEM); msr_t high_tom = rdmsr(TOP_MEM2); uint64_t high_mem_useable; diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 7d1124a..ceeaeb6 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -123,7 +123,7 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram = (uintptr_t)cbmem_top(); + uintptr_t top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); /* Cache the TSEG region */ diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index 43b96c1..8e3b767 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -35,7 +35,7 @@ * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); } diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 98c8016..f94c54b 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -53,7 +53,7 @@ * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); } diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c index 97344cd..ee3b51a 100644 --- a/src/soc/intel/common/block/systemagent/memmap.c +++ b/src/soc/intel/common/block/systemagent/memmap.c @@ -59,7 +59,7 @@ void fill_postcar_frame(struct postcar_frame *pcf) { /* FSP does not seem to bother w.r.t. alignment when asked to place cbmem_top() */ - uintptr_t top_of_ram = ALIGN_UP((uintptr_t)cbmem_top(), 8 * MiB); + uintptr_t top_of_ram = ALIGN_UP(cbmem_top(), 8 * MiB); /* * We need to make sure ramstage will be run cached. At this diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index e74c118..d5465c8 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -191,7 +191,7 @@ uintptr_t top_of_ram; int index = *resource_count; - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); /* 0 - > 0xa0000 */ ram_from_to(dev, index++, 0, 0xa0000); diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 399bb64..d37834c 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -55,7 +55,7 @@ void soc_fill_gnvs(struct global_nvs *gnvs) { /* Top of Low Memory (start of resource allocation) */ - gnvs->tolm = (uintptr_t)cbmem_top(); + gnvs->tolm = cbmem_top(); /* MMIO Low/High & TSEG base and length */ gnvs->mmiob = (u32)get_top_of_low_memory(); diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index f607d0f..0ad4c5b 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -48,7 +48,7 @@ * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/denverton_ns/systemagent.c b/src/soc/intel/denverton_ns/systemagent.c index 29953a6..a28343f 100644 --- a/src/soc/intel/denverton_ns/systemagent.c +++ b/src/soc/intel/denverton_ns/systemagent.c @@ -232,7 +232,7 @@ * PCI_BASE_ADDRESS_0. */ index = 0; - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); /* 0 - > 0xa0000 */ base_k = 0; diff --git a/src/soc/intel/quark/northcluster.c b/src/soc/intel/quark/northcluster.c index f1e5c63..7c83771 100644 --- a/src/soc/intel/quark/northcluster.c +++ b/src/soc/intel/quark/northcluster.c @@ -28,10 +28,10 @@ reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB); /* 0x100000 -> cbmem_top - cacheable and usable */ - ram_from_to(dev, index++, 1 * MiB, (uintptr_t)cbmem_top()); + ram_from_to(dev, index++, 1 * MiB, cbmem_top()); /* cbmem_top -> 0xc0000000 - reserved */ - reserved_ram_from_to(dev, index++, (uintptr_t)cbmem_top(), 0xc0000000); + reserved_ram_from_to(dev, index++, cbmem_top(), 0xc0000000); /* 0xc0000000 -> 4GiB is mmio. */ mmio_from_to(dev, index++, 0xc0000000, 4ull * GiB); diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c index c256484..54e8c10 100644 --- a/src/soc/intel/xeon_sp/memmap.c +++ b/src/soc/intel/xeon_sp/memmap.c @@ -29,7 +29,7 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - const uintptr_t top_of_ram = (uintptr_t)cbmem_top(); + const uintptr_t top_of_ram = cbmem_top(); uintptr_t cbmem_base; size_t cbmem_size; diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 1a60b60..62e7ae2 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -93,7 +93,7 @@ static void configure_dpr(struct device *dev) { - const uintptr_t cbmem_top_mb = ALIGN_UP((uintptr_t)cbmem_top(), MiB) / MiB; + const uintptr_t cbmem_top_mb = ALIGN_UP(cbmem_top(), MiB) / MiB; union dpr_register dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) }; /* The DPR lock bit has to be set sufficiently early. It looks like @@ -183,7 +183,7 @@ LOG_RESOURCE("legacy_ram", dev, res); /* 1MB -> top_of_ram i.e., cbmem_top */ - res = ram_from_to(dev, index++, 1 * MiB, (uintptr_t)cbmem_top()); + res = ram_from_to(dev, index++, 1 * MiB, cbmem_top()); LOG_RESOURCE("low_ram", dev, res); /* Mark TSEG/SMM region as reserved */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd Gerrit-Change-Number: 69163 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add get_ewl_hob() utility function
by Angel Pons (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69144 ) Change subject: soc/intel/xeon_sp/cpx: Add get_ewl_hob() utility function ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f949e9c881099c3723fca056e2c4732ca8b64cf Gerrit-Change-Number: 69144 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 02 Nov 2022 14:13:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/xeon_sp: Add weak mainboard_ewl_check for EWL check after FSP-M
by Angel Pons (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69143 ) Change subject: soc/xeon_sp: Add weak mainboard_ewl_check for EWL check after FSP-M ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f542e71d20307397c398fd757d9408438f681ed Gerrit-Change-Number: 69143 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 02 Nov 2022 14:13:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2022