coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[master]: drivers/ipmi/ocp: add PCIe SEL support
by Angel Pons (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Arthur Heymans, Jonathan Zhang, Johnny Lin, Rocky Phagura, Paul Menzel, Shuming Chu (Shuming), Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68758 ) Change subject: drivers/ipmi/ocp: add PCIe SEL support ...................................................................... Patch Set 7: Code-Review+1 (1 comment) File src/drivers/ipmi/ocp/ipmi_ocp.h: https://review.coreboot.org/c/coreboot/+/68758/comment/ae6ee476_155d2b7e PS3, Line 111: /* PCIE CE */ : #define RECEIVER_ERROR 0x00 : #define BAD_TLP 0x01 : #define BAD_DLLP 0x02 : #define REPLAY_TIME_OUT 0x03 : #define REPLAY_NUMBER_ROLLOVER 0x04 : #define ADVISORY_NONFATAL_ERROR_STATUS 0x05 : #define CORRECTED_INTERNAL_ERROR_STATUS 0x06 : #define HEADER_LOG_OVERFLOW_STATUS 0x07 : : /* PCIE UCE */ : #define PCI_EXPRESS_DATA_LINK_PROTOCOL_ERROR 0x20 : #define SURPRISE_DOWN_ERROR 0x21 : #define RECEIVED_PCI_EXPRESS_POISONED_TLP 0x22 : #define PCI_EXPRESS_FLOW_CONTROL_PROTOCOL_ERROR 0x23 : #define COMPLETION_TIMEOUT_ON_NP_TRANSACTIONS_OUTSTANDING_ON_PCI_EXPRESS_DMI 0x24 : #define RECEIVED_A_REQUEST_FROM_A_DOWNSTREAM_COMPONENT_THAT_IS_TO_BE_COMPLETER_ABORTED 0x25 : #define RECEIVED_PCI_EXPRESS_UNEXPECTED_COMPLETION 0x26 : #define PCI_EXPRESS_RECEIVER_OVERFLOW 0x27 : #define PCI_EXPRESS_MALFORMED_TLP 0x28 : #define ECRC_ERROR_STATUS 0x29 : #define RECEIVED_A_REQUEST_FROM_A_DOWNSTREAM_COMPONENT_THAT_IS_UNSUPPORTED 0x2A : #define ACS_VIOLATION 0x2B : #define UNCORRECTABLE_INTERNAL_ERROR_STATUS 0x2C : #define MC_BLOCKED_TLP 0x2D : #define ATOMICOP_EGRESS_BLOCKED_STATUS 0x2E : #define TLP_PREFIX_BLOCKED_ERROR_STATUS 0x2F : #define POISONED_TLP_EGRESS_BLOCKED 0x30 > As Jonathan mentioned, these macros are used for SEL (in Error ID field). […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/68758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ee46c8da7dbccbe1e2cc00bfe62e5df2f072d65 Gerrit-Change-Number: 68758 Gerrit-PatchSet: 7 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 02 Nov 2022 14:11:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill
by David Milosevic (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Jonathan Zhang, weidong.wd(a)bytedance.com, Angel Pons, Arthur Heymans, TangYiwei, Andrey Petrov, Sean Rhodes, Tarun Tuli, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Tim Wawrzynczak, Lean Sheng Tan, Werner Zeh, Tim Chu. David Milosevic has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68525 ) Change subject: soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill ...................................................................... Patch Set 5: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68525/comment/5648dc52_b513571a PS3, Line 14: Furthermore, function dimm_info_fill() : was adjusted. > How about: […] Done https://review.coreboot.org/c/coreboot/+/68525/comment/bd5881bb_727949fb PS3, Line 17: ATLAS > nit: Mainboard Kconfig capitalizes only the first letter of `Atlas` Done https://review.coreboot.org/c/coreboot/+/68525/comment/86e304c8_8d82800d PS3, Line 25: RVP board. > Maybe elaborate a bit more? […] Done File src/include/memory_info.h: https://review.coreboot.org/c/coreboot/+/68525/comment/2df7926f_e38e2965 PS4, Line 96: * Node-ID / Memory-Controller-ID > Yes, similar like on the server side, the hierarchy is socket/controller/channel/DIMM. Done File src/include/memory_info.h: https://review.coreboot.org/c/coreboot/+/68525/comment/5aa2c90f_32846c58 PS3, Line 98: uint8_t node_num; > It's just a data struct, so there's no problem if the offsets change. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ffa5bdff0ba0e3c4a4a51f2419291fd1278cd68 Gerrit-Change-Number: 68525 Gerrit-PatchSet: 5 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: weidong.wd(a)bytedance.com Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: weidong.wd(a)bytedance.com Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 02 Nov 2022 14:08:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill
by David Milosevic (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: weidong.wd(a)bytedance.com, Angel Pons, Arthur Heymans, TangYiwei, Andrey Petrov, Tarun Tuli, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Tim Wawrzynczak, Lean Sheng Tan, Werner Zeh, David Milosevic, Tim Chu. Hello build bot (Jenkins), Jonathan Zhang, weidong.wd(a)bytedance.com, Angel Pons, Arthur Heymans, TangYiwei, Andrey Petrov, Tarun Tuli, Anjaneya "Reddy" Chagam, Subrata Banik, Johnny Lin, Kapil Porwal, Christian Walter, Tim Wawrzynczak, Lean Sheng Tan, Werner Zeh, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68525 to look at the new patch set (#5). Change subject: soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill ...................................................................... soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill The dimm_info structure (defined in src/include/memory_info.h) currently does not hold information about the DIMM's node/controller ID. This patch extends the dimm_info structure by adding a new field for the node ID, called node_num. Also, adapt the dimm_info_fill() function accordingly to populate the newly-added field. Background: These changes are necessary for the Atlas mainboard, where we are currently experiencing issues with the DIMMs device/bank locator. Our 2 DIMMs share the same CHANNEL and DIMM ID but have a distinct NODE ID. By looking at the smbios table we see Channel-0-DIMM-0 for both DIMMs. Thus, we need their NODE IDs in order to distinguish them. This patch was tested by building and booting for the Alderlake-P RVP board, which has the same DIMM slot configuration as the Prodrive Atlas mainboard. Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> Change-Id: I6ffa5bdff0ba0e3c4a4a51f2419291fd1278cd68 --- M src/include/memory_info.h M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/apollolake/meminit_util_apl.c M src/soc/intel/apollolake/meminit_util_glk.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/common/smbios.c M src/soc/intel/common/smbios.h M src/soc/intel/elkhartlake/romstage/romstage.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/jasperlake/romstage/romstage.c M src/soc/intel/meteorlake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/tigerlake/romstage/romstage.c M src/soc/intel/xeon_sp/cpx/romstage.c 14 files changed, 65 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/68525/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/68525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ffa5bdff0ba0e3c4a4a51f2419291fd1278cd68 Gerrit-Change-Number: 68525 Gerrit-PatchSet: 5 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: weidong.wd(a)bytedance.com Gerrit-Attention: weidong.wd(a)bytedance.com Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: cbmem_top_chipset: Change the return value to uintptr_t
by Elyes Haouas (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Hung-Te Lin, Philipp Hug, Jakub Czapiga, Matt DeVillier, Angel Pons, Julius Werner, Andrey Petrov, ron minnich, Felix Held. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69078 ) Change subject: cbmem_top_chipset: Change the return value to uintptr_t ...................................................................... Patch Set 4: (4 comments) Patchset: PS4: Thank you. File src/northbridge/intel/x4x/memmap.c: https://review.coreboot.org/c/coreboot/+/69078/comment/091e3b03_e97ca0a1 PS1, Line 76: uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); : return top_of_ram; > +1, there are other occurrences in other Intel platforms. Could be done in a follow-up. Done File src/soc/nvidia/tegra124/cbmem.c: https://review.coreboot.org/c/coreboot/+/69078/comment/082426b9_d91d2a13 PS1, Line 9: return ((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL); > nit: Outer set of parentheses is now unnecessary Done File src/soc/sifive/fu540/cbmem.c: https://review.coreboot.org/c/coreboot/+/69078/comment/d9a9261f_5e5eea76 PS1, Line 11: return MIN((uintptr_t)_dram + sdram_size_mb() * MiB, : FU540_MAXDRAM); > nit: Can it fit in one line? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Gerrit-Change-Number: 69078 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 02 Nov 2022 13:55:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cbmem_top_chipset: Change the return value to uintptr_t
by Elyes Haouas (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Hung-Te Lin, Philipp Hug, Jakub Czapiga, Matt DeVillier, Angel Pons, Julius Werner, Andrey Petrov, ron minnich, Felix Held. Hello Hung-Te Lin, Philipp Hug, Jakub Czapiga, Matt DeVillier, Angel Pons, Julius Werner, Andrey Petrov, ron minnich, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69078 to look at the new patch set (#5). Change subject: cbmem_top_chipset: Change the return value to uintptr_t ...................................................................... cbmem_top_chipset: Change the return value to uintptr_t Get rid of a lot of casts. Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/drivers/amd/agesa/romstage.c M src/drivers/intel/fsp2_0/cbmem.c M src/include/cbmem.h M src/lib/imd_cbmem.c M src/mainboard/emulation/qemu-aarch64/cbmem.c M src/mainboard/emulation/qemu-armv7/cbmem.c M src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-power8/cbmem.c M src/mainboard/emulation/qemu-power9/cbmem.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/ironlake/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/soc/amd/stoneyridge/memmap.c M src/soc/cavium/cn81xx/cbmem.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/braswell/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/mediatek/common/cbmem.c M src/soc/nvidia/tegra124/cbmem.c M src/soc/nvidia/tegra210/cbmem.c M src/soc/nvidia/tegra210/ramstage.c M src/soc/qualcomm/ipq40xx/cbmem.c M src/soc/qualcomm/ipq806x/cbmem.c M src/soc/qualcomm/qcs405/cbmem.c M src/soc/qualcomm/sc7180/cbmem.c M src/soc/qualcomm/sc7280/cbmem.c M src/soc/rockchip/common/cbmem.c M src/soc/samsung/exynos5250/cbmem.c M src/soc/samsung/exynos5420/cbmem.c M src/soc/sifive/fu540/cbmem.c M src/soc/ti/am335x/cbmem.c M src/soc/ucb/riscv/cbmem.c M tests/lib/coreboot_table-test.c M tests/lib/imd_cbmem-test.c 39 files changed, 90 insertions(+), 80 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/69078/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/69078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Gerrit-Change-Number: 69078 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: cbmem_top_chipset: Change the return value to uintptr_t
by Elyes Haouas (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Hung-Te Lin, Philipp Hug, Jakub Czapiga, Matt DeVillier, Angel Pons, Julius Werner, Andrey Petrov, ron minnich, Felix Held. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69078 ) Change subject: cbmem_top_chipset: Change the return value to uintptr_t ...................................................................... Patch Set 4: (1 comment) File src/lib/imd_cbmem.c: https://review.coreboot.org/c/coreboot/+/69078/comment/aa7b4f4d_6a63715e PS4, Line 21: uintptr_t top; > It should be static indeed ! Thank you -- To view, visit https://review.coreboot.org/c/coreboot/+/69078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Gerrit-Change-Number: 69078 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 02 Nov 2022 13:53:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: mb/*/*: Remove AMD FAMILY15TN boards
by Paul Menzel (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Arthur Heymans, Alexander Couzens. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69111 ) Change subject: mb/*/*: Remove AMD FAMILY15TN boards ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > > Aren’t there change-sets up for review [1]? […] For Family 14h they were also change-sets [1]? https://review.coreboot.org/c/coreboot/+/52780/ -- To view, visit https://review.coreboot.org/c/coreboot/+/69111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9efb5cb1149cc4cf6337c47af8a2f4c4b55f4368 Gerrit-Change-Number: 69111 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Wed, 02 Nov 2022 13:53:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/sandybridge: Specify supported memory types
by Elyes Haouas (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Angel Pons. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69019 ) Change subject: nb/intel/sandybridge: Specify supported memory types ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: Thank you. File src/northbridge/intel/sandybridge/Kconfig: https://review.coreboot.org/c/coreboot/+/69019/comment/460d1e39_1533e907 PS1, Line 18: select USE_DDR3 > Why not select these from `config NORTHBRIDGE_INTEL_SANDYBRIDGE` instead? If I'm not wrong, all other nb/Kconfig are using "NORTHBRIDGE_SPECIFIC_OPTIONS" I don't know why current northbridge is different :p (I'm also ok to move DDR selection to config NORTHBRIDGE_INTEL_SANDYBRIDGE if you want) -- To view, visit https://review.coreboot.org/c/coreboot/+/69019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie43e818d03f411733e1bba5b7a4721c9a54ff4a4 Gerrit-Change-Number: 69019 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 02 Nov 2022 13:47:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/pineview: Specify supported memory types
by Angel Pons (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Elyes Haouas. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69020 ) Change subject: nb/intel/pineview: Specify supported memory types ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/northbridge/intel/pineview/Kconfig: https://review.coreboot.org/c/coreboot/+/69020/comment/4888d3fd_f9e32665 PS1, Line 19: select USE_DDR3 Not yet supported, but hopefully it will eventually be. Not a problem. -- To view, visit https://review.coreboot.org/c/coreboot/+/69020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If40010abdf180e40c2aab7a991c7382dc5b2d7d5 Gerrit-Change-Number: 69020 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 02 Nov 2022 13:43:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/x4x: Specify supported memory types
by Angel Pons (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Elyes Haouas. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68998 ) Change subject: nb/intel/x4x: Specify supported memory types ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c24ece29616fa008da0935c3fe71e35f16ed2d Gerrit-Change-Number: 68998 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 02 Nov 2022 13:43:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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