Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69077 )
Change subject: nb/intel/gm45: Make polling loops more explicit
......................................................................
nb/intel/gm45: Make polling loops more explicit
Replace `while (...);` with `do {} while (...);` so that it's easier to
distinguish polling loops from something else, like function calls. The
`{}` can be understood as "nothing", so that the construct is naturally
read as "do nothing while (...)".
Another reason to prefer this method is that Jenkins does not complain.
Change-Id: Ifbf3cf072f8b817b2fdeece4ef89bae0822bb6e6
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69077
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/northbridge/intel/gm45/pcie.c
1 file changed, 24 insertions(+), 3 deletions(-)
Approvals:
build bot (Jenkins): Verified
Felix Held: Looks good to me, approved
Arthur Heymans: Looks good to me, but someone else must approve
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c
index 295bf5b..59a4992 100644
--- a/src/northbridge/intel/gm45/pcie.c
+++ b/src/northbridge/intel/gm45/pcie.c
@@ -33,12 +33,12 @@
epbar_write32(EP_PORTARB(7), 0x00005555);
epbar_setbits32(EPVC1RCTL, 1 << 16);
- while ((epbar_read8(EPVC1RSTS) & 1) != 0);
+ do {} while ((epbar_read8(EPVC1RSTS) & 1) != 0);
/* VC1: enable */
epbar_setbits32(EPVC1RCTL, 1 << 31);
- while ((epbar_read8(EPVC1RSTS) & 2) != 0);
+ do {} while ((epbar_read8(EPVC1RSTS) & 2) != 0);
}
/* MCH side */
@@ -56,7 +56,7 @@
/* VC1: enable */
dmibar_setbits32(DMIVC1RCTL, 1 << 31);
- while ((dmibar_read8(DMIVC1RSTS) & VC1NP) != 0);
+ do {} while ((dmibar_read8(DMIVC1RSTS) & VC1NP) != 0);
/* additional configuration. */
dmibar_setbits32(0x200, 3 << 13);
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69052 )
Change subject: mb/google/brya: Create marasov variant
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162238):
https://review.coreboot.org/c/coreboot/+/69052/comment/d17b3395_7ce90d9a
PS5, Line 9: # See util/spd_tools/README.md for more details and instructions.
'README' may be misspelled - perhaps 'README'?
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Change subject: mb/google/nissa/var/craask: Modify PL2 setting to 25w
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
Hi Vidya,
Could you allow let's only update the PL2 value on the CL?
And let's have another issue and CL for PL4 setting if it's necessary.
Thanks ~
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Change subject: mb/google/nissa/var/craask: Modify PL2 setting to 25w
......................................................................
Patch Set 4: Code-Review+1
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Change subject: soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver
......................................................................
Patch Set 11:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69088/comment/67ed8cb6_eeb5352d
PS10, Line 10: secure register
> either "the secure register" or "secure registers"
Done
File src/soc/mediatek/mt8188/devapc.c:
https://review.coreboot.org/c/coreboot/+/69088/comment/909a3f78_8e6ebd3f
PS10, Line 1553: Side band
> "Side band" or "Sideband"? Please be consistent with the commit message.
Done
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Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Angel Pons, Yidi Lin, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69089
to look at the new patch set (#11).
Change subject: soc/mediatek/mt8188: Disable input-gating for big-core SRAM
......................................................................
soc/mediatek/mt8188: Disable input-gating for big-core SRAM
The input-gating is an experimental feature (but unfortunately default
enabled) and would lead to crash on MT8188, so we have to disable it
in the firmware stage.
BUG=b:233720142
TEST=CPUfreq in kernel test pass.
Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca
Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com>
---
M src/soc/mediatek/mt8188/Makefile.inc
A src/soc/mediatek/mt8188/cpu_input_gating.c
A src/soc/mediatek/mt8188/include/soc/cpu_input_gating.h
M src/soc/mediatek/mt8188/soc.c
4 files changed, 45 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/69089/11
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Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Angel Pons, Yidi Lin, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69088
to look at the new patch set (#11).
Change subject: soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver
......................................................................
soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver
When enabling cpufreq-hw driver, it is required for MCUPM to access
secure registers. Therefore, we enable Side-band to allow MCUPM to
access the secure registers.
BUG=b:236331463
TEST=It works well after boot to login shell.
Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6
Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com>
---
M src/soc/mediatek/mt8188/devapc.c
M src/soc/mediatek/mt8188/include/soc/devapc.h
2 files changed, 23 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/69088/11
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