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Change subject: checkpatch: add Co-authored-by to signature list
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/alderlake: Add support to enable PMC firmware trace
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS7:
> >Sorrym which one you need additionally? Are you referring to the FSP params which you need to set w […]
Done
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Change subject: soc/intel/alderlake: Enable the runtime debug capability
......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/64434/comment/92cebac2_2f37f0fc
PS7, Line 906: cntrl
> Agree, can I fix it after the patch set is up streamed? Is that fine?
Ack
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Change subject: drivers/ocp/ewl: Set CMOS flag to enforce MRC when there's EWL type3 error
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69148/comment/2758e657_f8b52c7d
PS2, Line 12: Reference CPX change https://review.coreboot.org/c/coreboot/+/51230
> How about: […]
Done
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Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69148
to look at the new patch set (#4).
Change subject: drivers/ocp/ewl: Set CMOS flag to enforce MRC when there's EWL type3 error
......................................................................
drivers/ocp/ewl: Set CMOS flag to enforce MRC when there's EWL type3 error
If Fastboot is enabled, the next boot will skip MRC and won't be able
to detect MRC error via EWL and still continues booting. Set a CMOS flag
to enforce FSP MRC training in the next boot.
See commit 95059b705500 (soc/intel/xeon_sp/cpx: Set the MRC "cold boot)
Change-Id: I9dee0472f8e2602cecf88c6d00dec0bf02b9f7bd
Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com>
---
M src/drivers/ocp/ewl/ewl.c
1 file changed, 36 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/69148/4
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Venkat Thogaru has uploaded a new patch set (#11) to the change originally created by Sudheer Amrabadi. ( https://review.coreboot.org/c/coreboot/+/68384 )
Change subject: soc/qualcomm/sc7280: Add API to differentialize PRO and NON_PRO SKUs
......................................................................
soc/qualcomm/sc7280: Add API to differentialize PRO and NON_PRO SKUs
The API socinfo_pro_part() returns 1 for Pro and 0 for NON_PRO SKUs. To
reduce the binary footprint for chipinfo structure, change its members
range from uint32_t to uint16_t. Add helper functions for reading and
matching jtagid.
BUG=b:248187555
TEST=Validate boards are detected correctly on PRO and NON_PRO SKUs
Signed-off-by: Taniya Das <quic_tdas(a)quicinc.com>
Change-Id: Id9f23696384a6c1a89000292eafebd8a16c273ca
---
M src/soc/qualcomm/sc7280/include/soc/socinfo.h
M src/soc/qualcomm/sc7280/socinfo.c
2 files changed, 89 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/68384/11
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Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69147 )
Change subject: drivers/ocp/ewl: Add sending Meta's BMC SEL for memory training error
......................................................................
Patch Set 3:
(2 comments)
File src/drivers/ipmi/ocp/ipmi_ocp.h:
https://review.coreboot.org/c/coreboot/+/69147/comment/a292c061_5813b950
PS2, Line 195: #define INTEL_MEMORY_ERROR 0x21
> nit: place this so that the macro numbers are in ascending order?
Done
File src/drivers/ocp/ewl/ewl.c:
https://review.coreboot.org/c/coreboot/+/69147/comment/c13e213d_0bb7a16b
PS2, Line 12: = 0xff
> Unused assignment
Done
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Change subject: mb/ocp/deltalake: Add EWL Hob processing for MRC error
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69146/comment/61d343bb_98a3f06f
PS1, Line 9: Override the weak function mainboard_ewl_check() and
> > 'disble' may be misspelled - perhaps 'disable'? […]
Done
https://review.coreboot.org/c/coreboot/+/69146/comment/b1e4b8a7_7218e97d
PS1, Line 10: The Intel FSP needs to disble promote
: MRC Warnings
> Is this an UPD? Where is it set?
It's not in the public CedarIsland FSP. Please see my updated git comment.
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