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Change subject: drivers/ocp/ewl: Set CMOS flag to enforce MRC when there's EWL type3 error
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162279):
https://review.coreboot.org/c/coreboot/+/69148/comment/369e077c_5398e845
PS3, Line 12: See commit 95059b7055 (soc/intel/xeon_sp/cpx: Set the MRC "cold boot)
Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 95059b705500 ("soc/intel/xeon_sp/cpx: Set the MRC "cold boot required" status bit")'
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Change subject: util/docker/coreboot.org-status: Rewrite parser
......................................................................
Patch Set 18:
(1 comment)
File util/docker/coreboot.org-status/board-status.html/boards.go:
https://review.coreboot.org/c/coreboot/+/59958/comment/8757f542_c84f5ff1
PS17, Line 587: /*
: venboard := vendor + "/" + board
: if bi["Clone of"] != "" {
: venboard = bi["Clone of"]
: }
: */
> Is it still needed? If so, maybe add some short comment about it?
Thanks, removed the stub here and implemented it properly in CB:69184
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Change subject: drivers/ocp/ewl: Set CMOS flag to enforce MRC when there's EWL type3 error
......................................................................
drivers/ocp/ewl: Set CMOS flag to enforce MRC when there's EWL type3 error
If Fastboot is enabled, the next boot will skip MRC and won't be able
to detect MRC error via EWL and still continues booting. Set a CMOS flag
to enforce FSP MRC training in the next boot.
See commit 95059b7055 (soc/intel/xeon_sp/cpx: Set the MRC "cold boot)
Change-Id: I9dee0472f8e2602cecf88c6d00dec0bf02b9f7bd
Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com>
---
M src/drivers/ocp/ewl/ewl.c
1 file changed, 36 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/69148/3
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Change subject: drivers/ocp/ewl: Add sending Meta's BMC SEL for memory training error
......................................................................
drivers/ocp/ewl: Add sending Meta's BMC SEL for memory training error
Add sending Meta's BMC SEL for memory training error occurred in EWL
type 3 error.
Change-Id: I664e9d3da7910b47260881c0df64159c8dbe2dca
Signed-off-by: Shelly Chang <Shelly_Chang(a)wiwynn.com>
Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com>
---
M src/drivers/ipmi/ocp/Makefile.inc
M src/drivers/ipmi/ocp/ipmi_ocp.h
M src/drivers/ocp/ewl/ewl.c
3 files changed, 72 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/69147/3
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Change subject: mb/ocp/deltalake: Add EWL Hob processing for MRC error
......................................................................
mb/ocp/deltalake: Add EWL Hob processing for MRC error
Override the weak function mainboard_ewl_check() and
select OCP_EWL. The Intel FSP needs to disable promote
MRC Warnings otherwise FSP won't return after MRC error.
The official public CedarIsland FSP doesn't provide this
via UPD.
Tested=On OCP Deltalake, with a customized FSP that disabled
promote MRC Warnings, connected with a faulty DIMM can see
EWL type 3 error being generated.
Change-Id: I4419ef43815f8181af89c49514a69bdb29858c13
Signed-off-by: Shelly Chang <Shelly_Chang(a)wiwynn.com>
Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com>
---
M src/mainboard/ocp/deltalake/Kconfig
M src/mainboard/ocp/deltalake/romstage.c
2 files changed, 28 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/69146/2
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Change subject: util/docker/coreboot.org-status: Rewrite parser
......................................................................
util/docker/coreboot.org-status: Rewrite parser
The current tool is a shell script that mixes data collection and HTML
generation and is generally a pain to work with. It takes 15 minutes to
run.
The new tool is written in go, collects all data first, then generates
the output HTML from the data and a single template, and finishes in
10 seconds.
The goal in this version is to produce output as similar as possible to
the output of the shell script. Some difference will remain because the
shell script returns some trash data whose reproduction would require
more effort than is worth.
Change-Id: I4fab86d24088e4f9eff434c21ce9caa077f3f9e2
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
A util/docker/coreboot.org-status/board-status.html/boards.go
A util/docker/coreboot.org-status/board-status.html/go.mod
A util/docker/coreboot.org-status/board-status.html/go.sum
A util/docker/coreboot.org-status/board-status.html/logs.go
A util/docker/coreboot.org-status/board-status.html/status-to-html.go
A util/docker/coreboot.org-status/board-status.html/templates/board-status.html
A util/docker/coreboot.org-status/board-status.html/types.go
7 files changed, 1,181 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/59958/18
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Change subject: mb/google/brya/var/kano: Add mipi hi556 camera support
......................................................................
Patch Set 3: Code-Review+1
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Change subject: drivers/ocp/dmi: Fix smbios type 11 get wrong ppin value for second socket
......................................................................
drivers/ocp/dmi: Fix smbios type 11 get wrong ppin value for second socket
The last logic cpu number not always comes from second socket, this may
cause the wrong smbios type 11 ppin value for second socket.
Add function to get logic cpu number from desired socket. With this way,
can get ppin value from second socket.
TESTED=On not public yet system, can get correct ppin value for smbios
type 11.
Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com>
Change-Id: I9174522c57680a57e6e4629b4e81fd837c38d47a
---
M src/drivers/ocp/dmi/smbios.c
1 file changed, 34 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/68910/5
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Change subject: include/device/pci_def.h: Add some PCIe DPC/AER definitions
......................................................................
include/device/pci_def.h: Add some PCIe DPC/AER definitions
* Add DPC related definitions which are defined in 7.9.14 of PCIe
6.0 spec.
* Add AER related definitions which are defined in 7.8.4 of PCIe
6.0 spec.
Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com>
Change-Id: Ifb6722c326ef69ef1bf3b1c2c1d5bc0cb29d7c12
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M src/include/device/pci_def.h
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