coreboot-gerrit November 2022

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[M] Change in coreboot[master]: soc/intel: Include <cpu/cpu.h> instead of <arch/cpu.h>
by Werner Zeh (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal, Lean Sheng Tan, Elyes Haouas. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69032 ) Change subject: soc/intel: Include <cpu/cpu.h> instead of <arch/cpu.h> ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7da9c672ee230dfaebd943247639b78d675957e4 Gerrit-Change-Number: 69032 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 03 Nov 2022 13:11:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: {device,drivers}: Include <cpu/cpu.h> instead of <arch/cpu.h>
by Felix Held (Code Review) 03 Nov '22

03 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69038 ) Change subject: {device,drivers}: Include <cpu/cpu.h> instead of <arch/cpu.h> ...................................................................... {device,drivers}: Include <cpu/cpu.h> instead of <arch/cpu.h> Also sort includes. Change-Id: I1727bf56b4090d040aab413006dec7aca0587d44 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69038 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/device/oprom/realmode/x86.h M src/drivers/amd/agesa/romstage.c M src/drivers/intel/fsp1_1/include/fsp/util.h M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/mipi_camera/camera.c 5 files changed, 24 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/device/oprom/realmode/x86.h b/src/device/oprom/realmode/x86.h index b0efe90..a770bcd 100644 --- a/src/device/oprom/realmode/x86.h +++ b/src/device/oprom/realmode/x86.h @@ -3,7 +3,7 @@ #ifndef __DEVICE_OPROM_REALMODE_X86_H__ #define __DEVICE_OPROM_REALMODE_X86_H__ -#include <arch/cpu.h> +#include <cpu/cpu.h> #include <stdint.h> #define REALMODE_BASE ((void *)0x600) diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index f60239a..5c3d904 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -1,21 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <amdblocks/biosram.h> #include <acpi/acpi.h> -#include <arch/cpu.h> +#include <amdblocks/biosram.h> #include <arch/romstage.h> #include <cbmem.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/x86/lapic.h> #include <halt.h> +#include <northbridge/amd/agesa/agesa_helper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <program_loading.h> +#include <romstage_common.h> #include <romstage_handoff.h> #include <smp/node.h> #include <string.h> #include <timestamp.h> -#include <romstage_common.h> -#include <northbridge/amd/agesa/agesa_helper.h> -#include <northbridge/amd/agesa/state_machine.h> void __weak board_BeforeAgesa(struct sysinfo *cb) { } diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index 2dec3f0..2f92760 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -3,7 +3,7 @@ #ifndef FSP1_1_UTIL_H #define FSP1_1_UTIL_H -#include <arch/cpu.h> +#include <cpu/cpu.h> #include <fsp/api.h> /* Current users expect to get the SoC's FSP definitions by including util.h. */ #include <fsp/soc_binding.h> diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 96dc472..1cc422e 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -6,7 +6,7 @@ #include <boot/coreboot_tables.h> #include <cbfs.h> #include <commonlib/region.h> -#include <arch/cpu.h> +#include <cpu/cpu.h> #include <fsp/api.h> #include <efi/efi_datatype.h> #include <fsp/info_header.h> diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index ad473bc..5b69c01 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -5,7 +5,7 @@ #include <acpi/acpi_device.h> #include <acpi/acpigen.h> #include <acpi/acpigen_pci.h> -#include <arch/cpu.h> +#include <cpu/cpu.h> #include <console/console.h> #include <cpu/intel/cpu_ids.h> #include <device/i2c_simple.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/69038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1727bf56b4090d040aab413006dec7aca0587d44 Gerrit-Change-Number: 69038 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: {device,drivers}: Include <cpu/cpu.h> instead of <arch/cpu.h>
by Felix Held (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Andrey Petrov, Elyes Haouas. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69038 ) Change subject: {device,drivers}: Include <cpu/cpu.h> instead of <arch/cpu.h> ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1727bf56b4090d040aab413006dec7aca0587d44 Gerrit-Change-Number: 69038 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 03 Nov 2022 13:08:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd: Include <cpu/cpu.h> instead of <arch/cpu.h>
by Felix Held (Code Review) 03 Nov '22

03 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69033 ) Change subject: soc/amd: Include <cpu/cpu.h> instead of <arch/cpu.h> ...................................................................... soc/amd: Include <cpu/cpu.h> instead of <arch/cpu.h> Also sort includes. Change-Id: Iea29938623fe1b2bcdd7f869b0accbc1f8758e7a Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69033 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/romstage.c M src/soc/amd/common/block/acpi/cppc.c M src/soc/amd/common/block/cpu/cpu.c M src/soc/amd/common/block/cpu/noncar/write_resume_eip.c M src/soc/amd/common/block/cpu/update_microcode.c M src/soc/amd/glinda/romstage.c M src/soc/amd/mendocino/romstage.c M src/soc/amd/morgana/romstage.c M src/soc/amd/picasso/agesa_acpi.c M src/soc/amd/picasso/romstage.c M src/soc/amd/picasso/soc_util.c M src/soc/amd/stoneyridge/romstage.c 12 files changed, 43 insertions(+), 28 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index dce0b69..b843bff 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -4,8 +4,8 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> -#include <arch/cpu.h> #include <console/console.h> +#include <cpu/cpu.h> #include <fsp/api.h> #include <program_loading.h> #include <romstage_common.h> diff --git a/src/soc/amd/common/block/acpi/cppc.c b/src/soc/amd/common/block/acpi/cppc.c index ce40057..81a09b4 100644 --- a/src/soc/amd/common/block/acpi/cppc.c +++ b/src/soc/amd/common/block/acpi/cppc.c @@ -3,7 +3,7 @@ #include <acpi/acpi_pm.h> #include <acpi/acpigen.h> #include <amdblocks/cppc.h> -#include <arch/cpu.h> +#include <cpu/cpu.h> #include <soc/msr.h> #include <types.h> diff --git a/src/soc/amd/common/block/cpu/cpu.c b/src/soc/amd/common/block/cpu/cpu.c index bece89b..7c1daf9 100644 --- a/src/soc/amd/common/block/cpu/cpu.c +++ b/src/soc/amd/common/block/cpu/cpu.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> #include <amdblocks/cpu.h> +#include <cpu/cpu.h> int get_cpu_count(void) { diff --git a/src/soc/amd/common/block/cpu/noncar/write_resume_eip.c b/src/soc/amd/common/block/cpu/noncar/write_resume_eip.c index d539161..5863917 100644 --- a/src/soc/amd/common/block/cpu/noncar/write_resume_eip.c +++ b/src/soc/amd/common/block/cpu/noncar/write_resume_eip.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <arch/cpu.h> #include <amdblocks/cpu.h> #include <cpu/amd/msr.h> +#include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <stdint.h> diff --git a/src/soc/amd/common/block/cpu/update_microcode.c b/src/soc/amd/common/block/cpu/update_microcode.c index 79aaaf5..cfffbc0 100644 --- a/src/soc/amd/common/block/cpu/update_microcode.c +++ b/src/soc/amd/common/block/cpu/update_microcode.c @@ -1,15 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> -#include <types.h> -#include <cpu/amd/microcode.h> +#include <cbfs.h> #include <commonlib/helpers.h> #include <console/console.h> -#include <cpu/x86/msr.h> +#include <cpu/amd/microcode.h> #include <cpu/amd/msr.h> -#include <cbfs.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> #include <stdio.h> #include <timestamp.h> +#include <types.h> #define CPU_MICROCODE_BLOB_NAME "cpu_microcode_XXXX.bin" #define CPU_MICROCODE_BLOB_FORMAT "cpu_microcode_%04x.bin" diff --git a/src/soc/amd/glinda/romstage.c b/src/soc/amd/glinda/romstage.c index dce0b69..b843bff 100644 --- a/src/soc/amd/glinda/romstage.c +++ b/src/soc/amd/glinda/romstage.c @@ -4,8 +4,8 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> -#include <arch/cpu.h> #include <console/console.h> +#include <cpu/cpu.h> #include <fsp/api.h> #include <program_loading.h> #include <romstage_common.h> diff --git a/src/soc/amd/mendocino/romstage.c b/src/soc/amd/mendocino/romstage.c index dfec897..3548a79 100644 --- a/src/soc/amd/mendocino/romstage.c +++ b/src/soc/amd/mendocino/romstage.c @@ -7,8 +7,8 @@ #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> #include <amdblocks/stb.h> -#include <arch/cpu.h> #include <console/console.h> +#include <cpu/cpu.h> #include <fsp/api.h> #include <program_loading.h> #include <romstage_common.h> diff --git a/src/soc/amd/morgana/romstage.c b/src/soc/amd/morgana/romstage.c index dce0b69..b843bff 100644 --- a/src/soc/amd/morgana/romstage.c +++ b/src/soc/amd/morgana/romstage.c @@ -4,8 +4,8 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> -#include <arch/cpu.h> #include <console/console.h> +#include <cpu/cpu.h> #include <fsp/api.h> #include <program_loading.h> #include <romstage_common.h> diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index 35eedcb..839d7c0 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -1,24 +1,24 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpi.h> #include <acpi/acpi_crat.h> #include <acpi/acpi_ivrs.h> -#include <arch/cpu.h> -#include <cpu/amd/cpuid.h> -#include <cpu/amd/msr.h> -#include <FspGuids.h> -#include <soc/acpi.h> -#include <stdint.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> +#include <acpi/acpi.h> #include <amdblocks/acpi.h> #include <amdblocks/cpu.h> #include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> +#include <arch/mmio.h> +#include <cpu/amd/cpuid.h> +#include <cpu/amd/msr.h> +#include <cpu/cpu.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <FspGuids.h> +#include <soc/acpi.h> #include <soc/data_fabric.h> #include <soc/pci_devs.h> -#include <arch/mmio.h> +#include <stdint.h> static unsigned long gen_crat_hsa_entry(struct acpi_crat_header *crat, unsigned long current) { diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index ccb11f0..9958af2 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -3,9 +3,9 @@ #include <acpi/acpi.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> -#include <arch/cpu.h> #include <commonlib/helpers.h> #include <console/console.h> +#include <cpu/cpu.h> #include <fsp/api.h> #include <program_loading.h> #include <romstage_common.h> diff --git a/src/soc/amd/picasso/soc_util.c b/src/soc/amd/picasso/soc_util.c index c82416e..9616f26 100644 --- a/src/soc/amd/picasso/soc_util.c +++ b/src/soc/amd/picasso/soc_util.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> #include <console/console.h> -#include <FspGuids.h> +#include <cpu/cpu.h> #include <fsp/util.h> +#include <FspGuids.h> #include <misc_data.h> #include <soc/cpu.h> #include <soc/soc_util.h> diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 7d1124a..54fc51e 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -2,16 +2,16 @@ #include <acpi/acpi.h> #include <amdblocks/acpi.h> -#include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> +#include <amdblocks/agesawrapper.h> #include <amdblocks/biosram.h> #include <amdblocks/psp.h> -#include <arch/cpu.h> #include <arch/romstage.h> #include <cbmem.h> #include <commonlib/helpers.h> #include <console/console.h> #include <cpu/amd/mtrr.h> +#include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/69033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea29938623fe1b2bcdd7f869b0accbc1f8758e7a Gerrit-Change-Number: 69033 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd: Include <cpu/cpu.h> instead of <arch/cpu.h>
by Felix Held (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Elyes Haouas. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69033 ) Change subject: soc/amd: Include <cpu/cpu.h> instead of <arch/cpu.h> ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea29938623fe1b2bcdd7f869b0accbc1f8758e7a Gerrit-Change-Number: 69033 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 03 Nov 2022 13:07:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: treewide: Add 'IWYU pragma: export' comment
by Felix Held (Code Review) 03 Nov '22

03 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68332 ) Change subject: treewide: Add 'IWYU pragma: export' comment ...................................................................... treewide: Add 'IWYU pragma: export' comment This pragma says to IWYU (Include What You Use) that the current file is supposed to provide commented headers. Change-Id: I482c645f6b5f955e532ad94def1b2f74f15ca908 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68332 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/arch/x86/include/arch/cpu.h M src/include/cbmem.h M src/include/console/console.h M src/include/cpu/cpu.h M src/include/cpu/x86/msr.h M src/include/device/mmio.h M src/include/device/pci.h M src/include/device/pci_ops.h M src/include/device/pnp.h M src/include/string.h M src/include/types.h M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/pch.h 17 files changed, 41 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 3402215..7c1a52e 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -4,7 +4,7 @@ #define ARCH_CPU_H #include <types.h> -#include <arch/cpuid.h> +#include <arch/cpuid.h> /* IWYU pragma: export */ /* * EFLAGS bits diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 5b5191a..40a0acb 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -3,7 +3,7 @@ #ifndef _CBMEM_H_ #define _CBMEM_H_ -#include <commonlib/bsd/cbmem_id.h> +#include <commonlib/bsd/cbmem_id.h> /* IWYU pragma: export */ #include <stddef.h> #include <stdint.h> #include <boot/coreboot_tables.h> diff --git a/src/include/console/console.h b/src/include/console/console.h index 49bce61..6f44d7f 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -8,7 +8,7 @@ #include <stdint.h> /* console.h is supposed to provide the log levels defined in here: */ -#include <commonlib/loglevel.h> +#include <commonlib/loglevel.h> /* IWYU pragma: export */ #define RAM_DEBUG (CONFIG(DEBUG_RAM_SETUP) ? BIOS_DEBUG : BIOS_NEVER) #define RAM_SPEW (CONFIG(DEBUG_RAM_SETUP) ? BIOS_SPEW : BIOS_NEVER) diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index 6610368..e668de8 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -3,7 +3,7 @@ #ifndef CPU_CPU_H #define CPU_CPU_H -#include <arch/cpu.h> +#include <arch/cpu.h> /* IWYU pragma: export */ #include <stdint.h> void cpu_initialize(unsigned int cpu_index); diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 999fdaa..f4e3985 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -3,7 +3,7 @@ #ifndef CPU_X86_MSR_H #define CPU_X86_MSR_H -#include <cpu/x86/msr_access.h> +#include <cpu/x86/msr_access.h> /* IWYU pragma: export */ /* Intel SDM: Table 2-1 * IA-32 architectural MSR: Extended Feature Enable Register diff --git a/src/include/device/mmio.h b/src/include/device/mmio.h index b5b79ee..2b9949e 100644 --- a/src/include/device/mmio.h +++ b/src/include/device/mmio.h @@ -3,7 +3,7 @@ #ifndef __DEVICE_MMIO_H__ #define __DEVICE_MMIO_H__ -#include <arch/mmio.h> +#include <arch/mmio.h> /* IWYU pragma: export */ #include <commonlib/helpers.h> #include <endian.h> #include <types.h> diff --git a/src/include/device/pci.h b/src/include/device/pci.h index f28f319..88b9555 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -19,14 +19,15 @@ #if CONFIG(PCI) -#include <stdint.h> -#include <stddef.h> -#include <device/pci_def.h> -#include <device/resource.h> +/* When <device/pci.h> is needed, it supposed to provide <device/pci_{def,type}.h> */ #include <device/device.h> +#include <device/pci_def.h> /* IWYU pragma: export */ #include <device/pci_ops.h> #include <device/pci_rom.h> -#include <device/pci_type.h> +#include <device/pci_type.h> /* IWYU pragma: export */ +#include <device/resource.h> +#include <stddef.h> +#include <stdint.h> /* Common pci operations without a standard interface */ struct pci_operations { diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index a167825..b5d4e23 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -6,7 +6,7 @@ #include <stdint.h> #include <device/device.h> #include <device/pci_type.h> -#include <arch/pci_ops.h> +#include <arch/pci_ops.h> /* IWYU pragma: export */ void __noreturn pcidev_die(void); diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index e2a6dc2..ac23a49 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -6,8 +6,8 @@ #include <stdint.h> #include <device/device.h> /* When <device/pnp.h> is needed, it supposed to provide <device/pnp_{def,type}.h> */ -#include <device/pnp_def.h> -#include <device/pnp_type.h> +#include <device/pnp_def.h> /* IWYU pragma: export */ +#include <device/pnp_type.h> /* IWYU pragma: export */ #include <arch/io.h> #if !ENV_PNP_SIMPLE_DEVICE diff --git a/src/include/string.h b/src/include/string.h index f595c7e..92ea5e5 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -3,9 +3,9 @@ #ifndef STRING_H #define STRING_H -#include <stdarg.h> +#include <stdarg.h> /* IWYU pragma: export */ #include <stddef.h> -#include <stdio.h> +#include <stdio.h> /* IWYU pragma: export */ void *memcpy(void *dest, const void *src, size_t n); void *memmove(void *dest, const void *src, size_t n); diff --git a/src/include/types.h b/src/include/types.h index 8724d4b..ca45717 100644 --- a/src/include/types.h +++ b/src/include/types.h @@ -4,11 +4,13 @@ #define __TYPES_H /* types.h is supposed to provide the standard headers defined in here: */ +/* IWYU pragma: begin_exports */ #include <commonlib/bsd/cb_err.h> #include <limits.h> #include <stdbool.h> #include <stdint.h> #include <stddef.h> +/* IWYU pragma: end_exports */ /* * This may mean something else on architectures where the bits are numbered diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 15d908a..34b36c3 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -22,7 +22,7 @@ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 -#include <southbridge/intel/common/rcba.h> +#include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */ #if CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) #define CROS_GPIO_DEVICE_NAME "CougarPoint" diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index f2ec1c6..68a32df 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -7,7 +7,7 @@ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 -#include <southbridge/intel/common/rcba.h> +#include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index 56f14b0..f0b60f6 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -5,7 +5,7 @@ #define DEFAULT_TBAR ((u8 *)0xfed1b000) -#include <southbridge/intel/common/rcba.h> +#include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */ #if CONFIG(BOARD_EMULATION_QEMU_X86_Q35) /* diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 2254689..33386f5 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -5,7 +5,7 @@ #define DEFAULT_TBAR ((u8 *)0xfed1b000) -#include <southbridge/intel/common/rcba.h> +#include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */ #define DEFAULT_PMBASE 0x00000500 #define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60) diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 83e86c2..1f5b4ea 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -4,6 +4,7 @@ #define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H #include <acpi/acpi.h> +#include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */ /* PCH types */ #define PCH_TYPE_CPT 0x1c /* CougarPoint */ @@ -24,8 +25,6 @@ #define DEFAULT_PMBASE 0x0500 #define DEFAULT_HECIBAR ((u8 *)0xfed17000) -#include <southbridge/intel/common/rcba.h> - #ifndef __ACPI__ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 7d9fc6d..1623274 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -4,6 +4,7 @@ #define SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H #include <acpi/acpi.h> +#include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */ #define CROS_GPIO_DEVICE_NAME "LynxPoint" @@ -55,8 +56,6 @@ #define DEFAULT_GPIOSIZE 0x80 #endif -#include <southbridge/intel/common/rcba.h> - #ifndef __ACPI__ #if CONFIG(INTEL_LYNXPOINT_LP) -- To view, visit https://review.coreboot.org/c/coreboot/+/68332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I482c645f6b5f955e532ad94def1b2f74f15ca908 Gerrit-Change-Number: 68332 Gerrit-PatchSet: 16 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: include/acpi/acpi_crat.h: Add missing <stdint.h>
by Felix Held (Code Review) 03 Nov '22

03 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69060 ) Change subject: include/acpi/acpi_crat.h: Add missing <stdint.h> ...................................................................... include/acpi/acpi_crat.h: Add missing <stdint.h> Change-Id: Ic157cd820be204035706f8074dd6dbcb95c0f04f Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69060 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/include/acpi/acpi_crat.h 1 file changed, 15 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/include/acpi/acpi_crat.h b/src/include/acpi/acpi_crat.h index b6ae1d6..d18d66c 100644 --- a/src/include/acpi/acpi_crat.h +++ b/src/include/acpi/acpi_crat.h @@ -3,6 +3,8 @@ #ifndef __ACPI_CRAT_H__ #define __ACPI_CRAT_H__ +#include <stdint.h> + enum crat_entry_type { CRAT_HSA_PROC_UNIT_TYPE, CRAT_MEMORY_TYPE, -- To view, visit https://review.coreboot.org/c/coreboot/+/69060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic157cd820be204035706f8074dd6dbcb95c0f04f Gerrit-Change-Number: 69060 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: ec/google/wilco: Include <cpu/cpu.h> instead of <arch/cpu.h>
by Felix Held (Code Review) 03 Nov '22

03 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69059 ) Change subject: ec/google/wilco: Include <cpu/cpu.h> instead of <arch/cpu.h> ...................................................................... ec/google/wilco: Include <cpu/cpu.h> instead of <arch/cpu.h> Also sort includes. Change-Id: I93f02674fde0415e4d831ec13541a806bbc3bd91 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69059 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Caveh Jalali <caveh(a)chromium.org> --- M src/ec/google/wilco/chip.c 1 file changed, 17 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Caveh Jalali: Looks good to me, approved diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index 2243004..7d85c6f 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpi.h> #include <acpi/acpi_device.h> +#include <acpi/acpi.h> #include <acpi/acpigen.h> -#include <arch/cpu.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> +#include <cpu/cpu.h> #include <device/pnp.h> #include <ec/acpi/ec.h> #include <intelblocks/cpulib.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/69059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93f02674fde0415e4d831ec13541a806bbc3bd91 Gerrit-Change-Number: 69059 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: test/lib: Add non-existent DIMMs test case in spd_cache-test
by Felix Held (Code Review) 03 Nov '22

03 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63643 ) Change subject: test/lib: Add non-existent DIMMs test case in spd_cache-test ...................................................................... test/lib: Add non-existent DIMMs test case in spd_cache-test Add non-existent DIMMs test case in spd_cache-test. BUG=b:213964936 TEST=make unit-tests PASSED Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I3c8aa92ee0cfd5908399f4bbd305f8f306571d40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63643 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Tim Wawrzynczak <inforichland(a)gmail.com> Reviewed-by: Jakub Czapiga <jacz(a)semihalf.com> --- M tests/lib/spd_cache-test.c 1 file changed, 41 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, but someone else must approve Jakub Czapiga: Looks good to me, approved diff --git a/tests/lib/spd_cache-test.c b/tests/lib/spd_cache-test.c index 48f06e3..b949d1b 100644 --- a/tests/lib/spd_cache-test.c +++ b/tests/lib/spd_cache-test.c @@ -230,6 +230,25 @@ assert_true(check_if_dimm_changed(spd_cache, &blk)); } +__attribute__((unused)) static void test_check_if_dimm_changed_with_nonexistent(void **state) +{ + uint8_t *spd_cache; + size_t spd_cache_sz; + struct spd_block blk = {.addr_map = {0x50, 0, 0, 0}, + .spd_array = {0}, .len = 0}; + + assert_int_equal(CB_SUCCESS, load_spd_cache(&spd_cache, &spd_cache_sz)); + memcpy(spd_cache, spd_data_ddr4_1, spd_data_ddr4_1_sz); + memset(spd_cache + spd_data_ddr4_1_sz, 0xff, spd_cache_sz - spd_data_ddr4_1_sz); + calc_spd_cache_crc(spd_cache); + assert_int_equal(CB_SUCCESS, spd_fill_from_cache(spd_cache, &blk)); + + get_sn_from_spd_cache(spd_cache, get_spd_sn_ret_sn); + get_spd_sn_ret_sn_idx = 0; + will_return_always(get_spd_sn, CB_SUCCESS); + assert_false(check_if_dimm_changed(spd_cache, &blk)); +} + int main(void) { const struct CMUnitTest tests[] = { @@ -247,6 +266,8 @@ setup_spd_cache_test), cmocka_unit_test_setup(test_check_if_dimm_changed_sn_changed, setup_spd_cache_test), + cmocka_unit_test_setup(test_check_if_dimm_changed_with_nonexistent, + setup_spd_cache_test), #endif }; -- To view, visit https://review.coreboot.org/c/coreboot/+/63643 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c8aa92ee0cfd5908399f4bbd305f8f306571d40 Gerrit-Change-Number: 63643 Gerrit-PatchSet: 2 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/brya/gaelin: Configure GPIO settings
by Felix Held (Code Review) 03 Nov '22

03 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69136 ) Change subject: mb/google/brya/gaelin: Configure GPIO settings ...................................................................... mb/google/brya/gaelin: Configure GPIO settings Override GPIO pad configuration based on the latest gaelin schematic. BUG=b:249000573 BRANCH=firmware-brya-14505.B TEST=FW_NAME=emerge-brask coreboot Change-Id: I649ac5131393008787cbb403fc64b914de23312b Signed-off-by: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69136 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> --- M src/mainboard/google/brya/variants/gaelin/Makefile.inc A src/mainboard/google/brya/variants/gaelin/gpio.c 2 files changed, 209 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raymond Chung: Looks good to me, but someone else must approve Tarun Tuli: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/gaelin/Makefile.inc b/src/mainboard/google/brya/variants/gaelin/Makefile.inc index fd45b94..7d1f886 100644 --- a/src/mainboard/google/brya/variants/gaelin/Makefile.inc +++ b/src/mainboard/google/brya/variants/gaelin/Makefile.inc @@ -1 +1,6 @@ +bootblock-y += gpio.c + +romstage-y += gpio.c romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/gaelin/gpio.c b/src/mainboard/google/brya/variants/gaelin/gpio.c new file mode 100644 index 0000000..a20e385 --- /dev/null +++ b/src/mainboard/google/brya/variants/gaelin/gpio.c @@ -0,0 +1,185 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* A17 : DISP_MISCC ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_A17, 0, DEEP), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : PROC_GP2 ==> NC */ + PAD_NC(GPP_B3, NONE), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* B7 : ISH_12C1_SDA ==> NC */ + PAD_NC(GPP_B7, NONE), + /* B8 : ISH_I2C1_SCL ==> NC */ + PAD_NC(GPP_B8, NONE), + + /* C6 : SML1CLK ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C6, 0, DEEP), + /* C7 : SML1DATA ==> USI_INT_L */ + PAD_CFG_GPO(GPP_C7, 0, DEEP), + + /* D0 : ISH_GP0 ==> NC */ + PAD_NC(GPP_D0, NONE), + /* D1 : ISH_GP1 ==> NC */ + PAD_NC(GPP_D1, NONE), + /* D2 : ISH_GP2 ==> NC */ + PAD_NC(GPP_D2, NONE), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC(GPP_D3, NONE), + /* D8 : SRCCLKREQ3# ==> NC */ + PAD_NC(GPP_D8, NONE), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC(GPP_D9, NONE), + /* D11 : ISH_SPI_MISO ==> NC */ + PAD_NC(GPP_D11, NONE), + /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ + PAD_NC(GPP_D12, NONE), + /* D17 : UART1_RXD ==> NC */ + PAD_NC(GPP_D17, NONE), + /* D18 : UART1_TXD ==> NC */ + PAD_NC(GPP_D18, NONE), + + /* E4 : SATA_DEVSLP0 ==> USB_A0_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E4, 1, DEEP), + /* E5 : SATA_DEVSLP1 ==> USB_A1_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E5, 1, DEEP), + /* E7 : PROC_GP1 ==> EN_MIC_PWR */ + PAD_CFG_GPO(GPP_E7, 0, DEEP), + /* E14 : DDSP_HPDA ==> EDP_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> NC */ + PAD_NC(GPP_F12, NONE), + /* F13 : GSXDOUT ==> NC */ + PAD_NC(GPP_F13, NONE), + /* F14 : GSXDIN ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC(GPP_F15, NONE), + /* F16 : GSXCLK ==> NC */ + PAD_NC(GPP_F16, NONE), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H12 : I2C7_SDA ==> NC */ + PAD_NC(GPP_H12, NONE), + /* H13 : I2C7_SCL ==> NC */ + PAD_NC(GPP_H13, NONE), + + /* R6 : I2S2_TXD ==> NC */ + PAD_NC(GPP_R6, NONE), + /* R7 : I2S2_RXD ==> NC */ + PAD_NC(GPP_R7, NONE), + + /* S0 : SNDW0_CLK ==> I2S1_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), + /* S1 : SNDW0_DATA ==> I2S1_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), + /* S2 : SNDW1_CLK ==> I2S1_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), + /* S6 : SNDW3_CLK ==> DMIC_CLK1_R */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA1_R */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F14 : GSXDIN ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/69136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I649ac5131393008787cbb403fc64b914de23312b Gerrit-Change-Number: 69136 Gerrit-PatchSet: 2 Gerrit-Owner: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bruce Chiang <brucechiang(a)msi.corp-partner.google.com> Gerrit-CC: Eason Chang <easonchang(a)msi.corp-partner.google.com> Gerrit-CC: Eddy Lu <eddylu(a)ami.corp-partner.google.com> Gerrit-MessageType: merged

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coreboot-gerrit November 2022