coreboot-gerrit November 2022

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[M] Change in coreboot[master]: soc/amd/common/block/data_fabric: Use register bitslice structs
by Felix Held (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69073 ) Change subject: soc/amd/common/block/data_fabric: Use register bitslice structs ...................................................................... Patch Set 1: Code-Review+1 (2 comments) File src/soc/amd/common/block/data_fabric/data_fabric_helper.c: https://review.coreboot.org/c/coreboot/+/69073/comment/0e100555_3e5714e7 PS1, Line 17: ficaa.reg_num = reg >> 2; not sure if this is obvious from the code, but maybe add a comment here that this is the number of the 32bit register? https://review.coreboot.org/c/coreboot/+/69073/comment/9b7bea72_d32170b2 PS1, Line 119: ctrl.raw = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); : if (!(ctrl.we || ctrl.re)) hm, this is basically is_mmio_reg_disabled, but since we need ctrl.raw in line 147, using that here would result in an additional pci config space access. i'dleave it as it is for now, but maybe look into this in a future patch -- To view, visit https://review.coreboot.org/c/coreboot/+/69073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5566f7af6cf5444fc8c627e004dd08185468c77 Gerrit-Change-Number: 69073 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 14:04:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/qualcomm/sc7280: Add API to differentialize PRO and NON_PRO SKUs
by Venkat Thogaru (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Shelley Chen, Taniya Das, Paul Menzel, Sudheer Amrabadi. Venkat Thogaru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68384 ) Change subject: soc/qualcomm/sc7280: Add API to differentialize PRO and NON_PRO SKUs ...................................................................... Patch Set 11: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68384/comment/4ad4cbc9_3cd6219e PS9, Line 7: > Please use one space. Done https://review.coreboot.org/c/coreboot/+/68384/comment/566a11ce_a25e6508 PS9, Line 7: Add socinfo_pro_part() function in : coreboot > Maybe: Add function to differentiate between PRO and NON_PRO SKUs Done https://review.coreboot.org/c/coreboot/+/68384/comment/ab35e357_75b646b5 PS9, Line 8: coreboot > Please just use one line for the summary [1]. […] Done https://review.coreboot.org/c/coreboot/+/68384/comment/a339731d_c67fdcf4 PS9, Line 10: > Please use exactly one space. Done https://review.coreboot.org/c/coreboot/+/68384/comment/6db0aeed_ce6445a2 PS9, Line 10: The API socinfo_pro_part is added to help to differentiate : between PRO and NON_PRO SKUs. Returns 1 for Pro : and 0 for NON_PRO SKUs. > Please reflow for 72 characters per line. Done https://review.coreboot.org/c/coreboot/+/68384/comment/6313a331_131f5337 PS9, Line 15: Validate boards are detected correctly on PRO : and NON_PRO SKUs > Ditto. Done Patchset: PS9: > The commit seems to do more changes than documented in the commit message. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9f23696384a6c1a89000292eafebd8a16c273ca Gerrit-Change-Number: 68384 Gerrit-PatchSet: 11 Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Thu, 03 Nov 2022 13:58:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: [test]mb/google/brya/marasov: Update gpio table
by Tarun Tuli (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Frank Chu. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69180 ) Change subject: [test]mb/google/brya/marasov: Update gpio table ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Hi Frank. For [test] or changes not ready to get submitted yet, could you please mark them as "Work In Progress" -- To view, visit https://review.coreboot.org/c/coreboot/+/69180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03b443826d39182eaf23ad3e4e0ba8d6b8a93022 Gerrit-Change-Number: 69180 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 13:53:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: util/docker/coreboot.org-status: Rewrite parser
by Patrick Georgi (Code Review) 03 Nov '22

03 Nov '22

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59958 ) Change subject: util/docker/coreboot.org-status: Rewrite parser ...................................................................... util/docker/coreboot.org-status: Rewrite parser The current tool is a shell script that mixes data collection and HTML generation and is generally a pain to work with. It takes 15 minutes to run. The new tool is written in go, collects all data first, then generates the output HTML from the data and a single template, and finishes in 10 seconds. The goal in this version is to produce output as similar as possible to the output of the shell script. Some difference will remain because the shell script returns some trash data whose reproduction would require more effort than is worth. Change-Id: I4fab86d24088e4f9eff434c21ce9caa077f3f9e2 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59958 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A util/docker/coreboot.org-status/board-status.html/boards.go A util/docker/coreboot.org-status/board-status.html/go.mod A util/docker/coreboot.org-status/board-status.html/go.sum A util/docker/coreboot.org-status/board-status.html/logs.go A util/docker/coreboot.org-status/board-status.html/status-to-html.go A util/docker/coreboot.org-status/board-status.html/templates/board-status.html A util/docker/coreboot.org-status/board-status.html/types.go 7 files changed, 1,184 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Maxim Polyakov: Looks good to me, approved diff --git a/util/docker/coreboot.org-status/board-status.html/boards.go b/util/docker/coreboot.org-status/board-status.html/boards.go new file mode 100644 index 0000000..dc68cb6 --- /dev/null +++ b/util/docker/coreboot.org-status/board-status.html/boards.go @@ -0,0 +1,601 @@ +package main + +import ( + "fmt" + "io/fs" + "os" + "path/filepath" + "regexp" + "sort" + "strings" +) + +func readBoardInfo(dir NamedFS) map[string]string { + result := make(map[string]string) + c, err := fs.ReadFile(dir.FS, filepath.Join(dir.Name, "board_info.txt")) + if err != nil { + return result + } + ls := strings.Split(string(c), "\n") + for _, l := range ls { + spl := strings.SplitN(l, ":", 2) + if len(spl) != 2 { + // This shouldn't ever happen, but let's try to + // extract as much information from erroneous + // board_info files (if they exist) as possible. + continue + } + result[strings.TrimSpace(spl[0])] = strings.TrimSpace(spl[1]) + } + return result +} + +func fetchBoards(dirs chan<- NamedFS) { + defer close(dirs) + ds, err := fs.Glob(cbdirFS, filepath.Join("src", "mainboard", "*", "*")) + if err != nil { + fmt.Fprintf(os.Stderr, "Could not find mainboard directories: %v\n", err) + return + } + for _, d := range ds { + if _, err := fs.ReadDir(cbdirFS, d); err != nil { + continue + } + dirs <- NamedFS{ + FS: cbdirFS, + Name: d, + } + } +} + +var niceVendors = make(map[string]string) + +func getNiceVendor(dir string, vendor string) (string, error) { + if _, exists := niceVendors[vendor]; !exists { + c, err := fs.ReadFile(cbdirFS, filepath.Join(dir, "..", "Kconfig.name")) + if err != nil { + return "", err + } + re, err := regexp.Compile("(?i)config VENDOR_" + vendor) + if err != nil { + return "", err + } + ls := strings.Split(string(c), "\n") + next := false + for _, l := range ls { + if next { + niceVendors[vendor] = strings.Split(l, "\"")[1] + break + } + if re.Match([]byte(l)) { + next = true + } + } + } + return niceVendors[vendor], nil +} + +func readKconfig(dir NamedFS) (string, string, string, string, string, error) { + var north, south, superio, cpu, partnum string + c, err := fs.ReadFile(dir.FS, filepath.Join(dir.Name, "Kconfig")) + if err != nil { + return north, south, superio, cpu, partnum, err + } + ls := strings.Split(string(c), "\n") + partoffset := 0 + for _, l := range ls { + l = strings.TrimSpace(l) + if len(l) < 7 { + continue + } + // TODO: handling of MAINBOARD_PART_NUMBER is rather broken + // and fragile. Doesn't help that many boards use different + // part numbers for different models and this code can't + // figure it out. + if strings.Contains(strings.ToLower(l), "config mainboard_part_number") { + partoffset = 2 + continue + } + if partoffset > 0 { + partoffset-- + if strings.Contains(l, "default") { + partnum = strings.Split(l, "\"")[1] + continue + } + } + if l[0:7] != "select " { + continue + } + l = l[7:] + if len(l) > 12 && l[0:12] == "NORTHBRIDGE_" { + north = l[12:] + continue + } + if len(l) > 12 && l[0:12] == "SOUTHBRIDGE_" { + if strings.Contains(l, "SKIP_") || + strings.Contains(l, "DISABLE_") { + continue + } + south = l[12:] + continue + } + if len(l) > 8 && l[0:8] == "SUPERIO_" { + superio = l[8:] + continue + } + if len(l) > 4 && (l[0:4] == "CPU_" || l[0:4] == "SOC_") { + if strings.Contains(l, "AMD_AGESA_FAMILY") || + strings.Contains(l, "AMD_COMMON_") || + strings.Contains(l, "INTEL_COMMON_") || + strings.Contains(l, "INTEL_DISABLE_") || + strings.Contains(l, "INTEL_CSE_") || + strings.Contains(l, "CPU_MICROCODE_CBFS_NONE") { + continue + } + cpu = l[4:] + } + } + return north, south, superio, cpu, partnum, nil +} + +type reReplace struct { + pattern *regexp.Regexp + replace string +} + +func prettify(input string, rules *[]reReplace) string { + for _, rule := range *rules { + input = rule.pattern.ReplaceAllString(input, rule.replace) + } + return input +} + +var northbridgeRules = []reReplace{ + { + pattern: regexp.MustCompile("AMD_AGESA_FAMILY([0-9a-fA-F]*)(.*)"), + replace: "AMD Family ${1}h${2} (AGESA)", + }, + { + pattern: regexp.MustCompile("AMD_PI_(.*)"), + replace: "AMD ${1} (PI)", + }, + { + pattern: regexp.MustCompile("INTEL_FSP_(.*)"), + replace: "Intel® ${1} (FSP)", + }, + { + pattern: regexp.MustCompile("AMD_FAMILY([0-9a-fA-F]*)"), + replace: "AMD Family ${1}h,", + }, + { + pattern: regexp.MustCompile("AMD_AMDFAM([0-9a-fA-F]*)"), + replace: "AMD Family ${1}h", + }, + { + pattern: regexp.MustCompile("_"), + replace: " ", + }, + { + pattern: regexp.MustCompile("INTEL"), + replace: "Intel®", + }, +} + +func prettifyNorthbridge(northbridge string) string { + return prettify(northbridge, &northbridgeRules) +} + +var southbridgeRules = []reReplace{ + { + pattern: regexp.MustCompile("_"), + replace: " ", + }, + { + pattern: regexp.MustCompile("INTEL"), + replace: "Intel®", + }, +} + +func prettifySouthbridge(southbridge string) string { + return prettify(southbridge, &southbridgeRules) +} + +var superIORules = []reReplace{ + { + pattern: regexp.MustCompile("_"), + replace: " ", + }, + { + pattern: regexp.MustCompile("WINBOND"), + replace: "Winbond™,", + }, + { + pattern: regexp.MustCompile("ITE"), + replace: "ITE™", + }, + { + pattern: regexp.MustCompile("SMSC"), + replace: "SMSC®", + }, + { + pattern: regexp.MustCompile("NUVOTON"), + replace: "Nuvoton ", + }, +} + +func prettifySuperIO(superio string) string { + return prettify(superio, &superIORules) +} + +type cpuMapping struct { + cpu string + socket string +} + +var cpuMappings = map[string]cpuMapping{ + "ALLWINNER_A10": { + cpu: "Allwinner A10", + socket: "?", + }, + "AMD_GEODE_LX": { + cpu: "AMD Geode™ LX", + socket: "—", + }, + "AMD_SOCKET_754": { + cpu: "AMD Sempron™ / Athlon™ 64 / Turion™ 64", + socket: "Socket 754", + }, + "AMD_SOCKET_ASB2": { + cpu: "AMD Turion™ II Neo/Athlon™ II Neo", + socket: "ASB2 (BGA812)", + }, + "AMD_SOCKET_S1G1": { + cpu: "AMD Turion™ / X2 Sempron™", + socket: "Socket S1G1", + }, + "AMD_SOCKET_G34": { + cpu: "AMD Opteron™ Magny-Cours/Interlagos", + socket: "Socket G34", + }, + "AMD_SOCKET_G34_NON_AGESA": { + cpu: "AMD Opteron™ Magny-Cours/Interlagos", + socket: "Socket G34", + }, + "AMD_SOCKET_C32": { + cpu: "AMD Opteron™ Magny-Cours/Interlagos", + socket: "Socket C32", + }, + "AMD_SOCKET_C32_NON_AGESA": { + cpu: "AMD Opteron™ Magny-Cours/Interlagos", + socket: "Socket C32", + }, + "AMD_SOCKET_AM2": { + cpu: "?", + socket: "Socket AM2", + }, + "AMD_SOCKET_AM3": { + cpu: "AMD Athlon™ 64 / FX / X2", + socket: "Socket AM3", + }, + "AMD_SOCKET_AM2R2": { + cpu: "AMD Athlon™ 64 / X2 / FX, Sempron™", + socket: "Socket AM2+", + }, + "AMD_SOCKET_F": { + cpu: "AMD Opteron™", + socket: "Socket F", + }, + "AMD_SOCKET_F_1207": { + cpu: "AMD Opteron™", + socket: "Socket F 1207", + }, + "AMD_SOCKET_940": { + cpu: "AMD Opteron™", + socket: "Socket 940", + }, + "AMD_SOCKET_939": { + cpu: "AMD Athlon™ 64 / FX / X2", + socket: "Socket 939", + }, + "AMD_SC520": { + cpu: "AMD Élan™SC520", + socket: "—", + }, + "AMD_STONEYRIDGE_FP4": { + cpu: "AMD Stoney Ridge", + socket: "FP4 BGA", + }, + "ARMLTD_CORTEX_A9": { + cpu: "ARM Cortex A9", + socket: "?", + }, + "DMP_VORTEX86EX": { + cpu: "DMP VORTEX86EX", + socket: "?", + }, + "MEDIATEK_MT8173": { + cpu: "MediaTek MT8173", + socket: "—", + }, + "NVIDIA_TEGRA124": { + cpu: "NVIDIA Tegra 124", + socket: "—", + }, + "NVIDIA_TEGRA210": { + cpu: "NVIDIA Tegra 210", + socket: "—", + }, + "SAMSUNG_EXYNOS5420": { + cpu: "Samsung Exynos 5420", + socket: "?", + }, + "SAMSUNG_EXYNOS5250": { + cpu: "Samsung Exynos 5250", + socket: "?", + }, + "TI_AM335X": { + cpu: "TI AM335X", + socket: "?", + }, + "INTEL_APOLLOLAKE": { + cpu: "Intel® Apollo Lake", + socket: "—", + }, + "INTEL_BAYTRAIL": { + cpu: "Intel® Bay Trail", + socket: "—", + }, + "INTEL_BRASWELL": { + cpu: "Intel® Braswell", + socket: "—", + }, + "INTEL_BROADWELL": { + cpu: "Intel® Broadwell", + socket: "—", + }, + "INTEL_DENVERTON_NS": { + cpu: "Intel® Denverton-NS", + socket: "—", + }, + "INTEL_FSP_BROADWELL_DE": { + cpu: "Intel® Broadwell-DE", + socket: "—", + }, + "INTEL_GLK": { + cpu: "Intel® Gemini Lake", + socket: "—", + }, + "INTEL_GEMINILAKE": { + cpu: "Intel® Gemini Lake", + socket: "—", + }, + "INTEL_ICELAKE": { + cpu: "Intel® Ice Lake", + socket: "—", + }, + "INTEL_KABYLAKE": { + cpu: "Intel® Kaby Lake", + socket: "—", + }, + "INTEL_SANDYBRIDGE": { + cpu: "Intel® Sandy Bridge", + socket: "—", + }, + "INTEL_SKYLAKE": { + cpu: "Intel® Skylake", + socket: "—", + }, + "INTEL_SLOT_1": { + cpu: "Intel® Pentium® II/III, Celeron®", + socket: "Slot 1", + }, + "INTEL_SOCKET_MPGA604": { + cpu: "Intel® Xeon®", + socket: "Socket 604", + }, + "INTEL_SOCKET_M": { + cpu: "Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M", + socket: "Socket M (mPGA478MT)", + }, + "INTEL_SOCKET_LGA771": { + cpu: "Intel Xeon™ 5000 series", + socket: "Socket LGA771", + }, + "INTEL_SOCKET_LGA775": { + cpu: "Intel® Core 2, Pentium 4/D", + socket: "Socket LGA775", + }, + "INTEL_SOCKET_PGA370": { + cpu: "Intel® Pentium® III-800, Celeron®", + socket: "Socket PGA370", + }, + "INTEL_SOCKET_MPGA479M": { + cpu: "Intel® Mobile Celeron", + socket: "Socket 479", + }, + "INTEL_HASWELL": { + cpu: "Intel® 4th Gen (Haswell) Core i3/i5/i7", + socket: "?", + }, + "INTEL_FSP_RANGELEY": { + cpu: "Intel® Atom Rangeley (FSP)", + socket: "?", + }, + "INTEL_SOCKET_441": { + cpu: "Intel® Atom™ 230", + socket: "Socket 441", + }, + "INTEL_SOCKET_FC_PGA370": { + cpu: "Intel® Pentium® III, Celeron®", + socket: "Socket PGA370", + }, + "INTEL_EP80579": { + cpu: "Intel® EP80579", + socket: "Intel® EP80579", + }, + "INTEL_SOCKET_MFCBGA479": { + cpu: "Intel® Mobile Celeron", + socket: "Socket 479", + }, + "INTEL_WHISKEYLAKE": { + cpu: "Intel® Whiskey Lake", + socket: "—", + }, + "QC_IPQ806X": { + cpu: "Qualcomm IPQ806x", + socket: "—", + }, + "QUALCOMM_QCS405": { + cpu: "Qualcomm QCS405", + socket: "—", + }, + "ROCKCHIP_RK3288": { + cpu: "Rockchip RK3288", + socket: "—", + }, + "ROCKCHIP_RK3399": { + cpu: "Rockchip RK3399", + socket: "—", + }, + "VIA_C3": { + cpu: "VIA C3™", + socket: "?", + }, + "VIA_C7": { + cpu: "VIA C7™", + socket: "?", + }, + "VIA_NANO": { + cpu: "VIA NANO™", + socket: "?", + }, + "QEMU_X86": { + cpu: "QEMU x86", + socket: "—", + }, +} + +func prettifyCPU(cpu, north string, northNice string) (string, string) { + if match, ok := cpuMappings[cpu]; ok { + return match.cpu, match.socket + } + if cpu == "" { + if match, ok := cpuMappings[north]; ok { + return match.cpu, match.socket + } + if north == "INTEL_IRONLAKE" { + return "Intel® 1st Gen (Westmere) Core i3/i5/i7", "?" + } + if north == "RDC_R8610" { + return "RDC R8610", "—" + } + if (len(north) > 10 && north[0:10] == "AMD_AGESA_") || (len(north) > 7 && north[0:7] == "AMD_PI_") { + return northNice, "?" + } + return north, north + } + if cpu == "INTEL_SOCKET_BGA956" { + if north == "INTEL_GM45" { + return "Intel® Core 2 Duo (Penryn)", "Socket P" + } + return "Intel® Pentium® M", "BGA956" + } + if cpu == "INTEL_SOCKET_RPGA989" || cpu == "INTEL_SOCKET_LGA1155" || cpu == "INTEL_SOCKET_RPGA988B" { + socket := "Socket " + cpu[13:] + if north == "INTEL_HASWELL" { + return "Intel® 4th Gen (Haswell) Core i3/i5/i7", socket + } + if north == "INTEL_IVYBRIDGE" || north == "INTEL_FSP_IVYBRIDGE" { + return "Intel® 3rd Gen (Ivybridge) Core i3/i5/i7", socket + } + if north == "INTEL_SANDYBRIDGE" { + return "Intel® 2nd Gen (Sandybridge) Core i3/i5/i7", socket + } + return north, socket + } + return cpu, cpu +} + +func collectBoards(dirs <-chan NamedFS) { + for dir := range dirs { + path := strings.Split(dir.Name, string(filepath.Separator)) + vendor, board := path[2], path[3] + vendorNice, err := getNiceVendor(dir.Name, vendor) + + if err != nil { + fmt.Fprintf(os.Stderr, "Could not find nice vendor name for %s: %v\n", dir.Name, err) + continue + } + + bi := readBoardInfo(dir) + cat := Category(bi["Category"]) + if _, ok := data.CategoryNiceNames[cat]; !ok { + cat = "unclass" + } + if bi["Vendor cooperation score"] == "" { + bi["Vendor cooperation score"] = "—" + } + + north, south, superio, cpu, partnum, err := readKconfig(dir) + if err != nil { + fmt.Fprintf(os.Stderr, "'%s' is not a mainboard directory: %v\n", dir.Name, err) + // Continue with the path because that's what the + // shell script did. We might want to change semantics + // later. + } + northbridgeNice := prettifyNorthbridge(north) + southbridgeNice := prettifySouthbridge(south) + superIONice := prettifySuperIO(superio) + cpuNice, socketNice := prettifyCPU(cpu, north, northbridgeNice) + + boardNice := bi["Board name"] + if boardNice == "" { + boardNice = partnum + } + if boardNice == "" { + boardNice = strings.ReplaceAll(boardNice, "_", " ") + boardNice = strings.ToUpper(boardNice) + } + + b := Board{ + Vendor: vendor, + Vendor2nd: bi["Vendor name"], + VendorNice: vendorNice, + VendorBoard: vendor + "/" + board, + Board: board, + BoardNice: boardNice, + BoardURL: bi["Board URL"], + NorthbridgeNice: northbridgeNice, + SouthbridgeNice: southbridgeNice, + SuperIONice: superIONice, + CPUNice: cpuNice, + SocketNice: socketNice, + ROMPackage: bi["ROM package"], + ROMProtocol: bi["ROM protocol"], + ROMSocketed: bi["ROM socketed"], + FlashromSupport: bi["Flashrom support"], + VendorCooperationScore: bi["Vendor cooperation score"], + VendorCooperationPage: bi["Vendor cooperation page"], + } + if b.ROMPackage == "" { + b.ROMPackage = "?" + } + if b.ROMProtocol == "" { + b.ROMProtocol = "?" + } + + if data.BoardsByCategory[cat] == nil { + data.BoardsByCategory[cat] = []Board{} + } + data.BoardsByCategory[cat] = append(data.BoardsByCategory[cat], b) + } + for ci := range data.BoardsByCategory { + cat := data.BoardsByCategory[ci] + sort.Slice(data.BoardsByCategory[ci], func(i, j int) bool { + if cat[i].Vendor == cat[j].Vendor { + return cat[i].Board < cat[j].Board + } + return cat[i].Vendor < cat[j].Vendor + }) + } +} diff --git a/util/docker/coreboot.org-status/board-status.html/go.mod b/util/docker/coreboot.org-status/board-status.html/go.mod new file mode 100644 index 0000000..7fcf434 --- /dev/null +++ b/util/docker/coreboot.org-status/board-status.html/go.mod @@ -0,0 +1,23 @@ +module review.coreboot.org/coreboot.git/util/docker/coreboot.org-status/board-stat… + +go 1.17 + +require ( + github.com/Microsoft/go-winio v0.4.16 // indirect + github.com/ProtonMail/go-crypto v0.0.0-20210428141323-04723f9f07d7 // indirect + github.com/acomagu/bufpipe v1.0.3 // indirect + github.com/emirpasic/gods v1.12.0 // indirect + github.com/go-git/gcfg v1.5.0 // indirect + github.com/go-git/go-billy/v5 v5.3.1 // indirect + github.com/go-git/go-git/v5 v5.4.2 // indirect + github.com/imdario/mergo v0.3.12 // indirect + github.com/jbenet/go-context v0.0.0-20150711004518-d14ea06fba99 // indirect + github.com/kevinburke/ssh_config v0.0.0-20201106050909-4977a11b4351 // indirect + github.com/mitchellh/go-homedir v1.1.0 // indirect + github.com/sergi/go-diff v1.1.0 // indirect + github.com/xanzy/ssh-agent v0.3.0 // indirect + golang.org/x/crypto v0.0.0-20210421170649-83a5a9bb288b // indirect + golang.org/x/net v0.0.0-20210326060303-6b1517762897 // indirect + golang.org/x/sys v0.0.0-20210502180810-71e4cd670f79 // indirect + gopkg.in/warnings.v0 v0.1.2 // indirect +) diff --git a/util/docker/coreboot.org-status/board-status.html/go.sum b/util/docker/coreboot.org-status/board-status.html/go.sum new file mode 100644 index 0000000..2ea7b18 --- /dev/null +++ b/util/docker/coreboot.org-status/board-status.html/go.sum @@ -0,0 +1,84 @@ +github.com/Microsoft/go-winio v0.4.14/go.mod h1:qXqCSQ3Xa7+6tgxaGTIe4Kpcdsi+P8jBhyzoq1bpyYA= +github.com/Microsoft/go-winio v0.4.16 h1:FtSW/jqD+l4ba5iPBj9CODVtgfYAD8w2wS923g/cFDk= +github.com/Microsoft/go-winio v0.4.16/go.mod h1:XB6nPKklQyQ7GC9LdcBEcBl8PF76WugXOPRXwdLnMv0= +github.com/ProtonMail/go-crypto v0.0.0-20210428141323-04723f9f07d7 h1:YoJbenK9C67SkzkDfmQuVln04ygHj3vjZfd9FL+GmQQ= +github.com/ProtonMail/go-crypto v0.0.0-20210428141323-04723f9f07d7/go.mod h1:z4/9nQmJSSwwds7ejkxaJwO37dru3geImFUdJlaLzQo= +github.com/acomagu/bufpipe v1.0.3 h1:fxAGrHZTgQ9w5QqVItgzwj235/uYZYgbXitB+dLupOk= +github.com/acomagu/bufpipe v1.0.3/go.mod h1:mxdxdup/WdsKVreO5GpW4+M/1CE2sMG4jeGJ2sYmHc4= +github.com/anmitsu/go-shlex v0.0.0-20161002113705-648efa622239/go.mod h1:2FmKhYUyUczH0OGQWaF5ceTx0UBShxjsH6f8oGKYe2c= +github.com/armon/go-socks5 v0.0.0-20160902184237-e75332964ef5/go.mod h1:wHh0iHkYZB8zMSxRWpUBQtwG5a7fFgvEO+odwuTv2gs= +github.com/creack/pty v1.1.9/go.mod h1:oKZEueFk5CKHvIhNR5MUki03XCEU+Q6VDXinZuGJ33E= +github.com/davecgh/go-spew v1.1.0/go.mod h1:J7Y8YcW2NihsgmVo/mv3lAwl/skON4iLHjSsI+c5H38= +github.com/davecgh/go-spew v1.1.1/go.mod h1:J7Y8YcW2NihsgmVo/mv3lAwl/skON4iLHjSsI+c5H38= +github.com/emirpasic/gods v1.12.0 h1:QAUIPSaCu4G+POclxeqb3F+WPpdKqFGlw36+yOzGlrg= +github.com/emirpasic/gods v1.12.0/go.mod h1:YfzfFFoVP/catgzJb4IKIqXjX78Ha8FMSDh3ymbK86o= +github.com/flynn/go-shlex v0.0.0-20150515145356-3f9db97f8568/go.mod h1:xEzjJPgXI435gkrCt3MPfRiAkVrwSbHsst4LCFVfpJc= +github.com/gliderlabs/ssh v0.2.2/go.mod h1:U7qILu1NlMHj9FlMhZLlkCdDnU1DBEAqr0aevW3Awn0= +github.com/go-git/gcfg v1.5.0 h1:Q5ViNfGF8zFgyJWPqYwA7qGFoMTEiBmdlkcfRmpIMa4= +github.com/go-git/gcfg v1.5.0/go.mod h1:5m20vg6GwYabIxaOonVkTdrILxQMpEShl1xiMF4ua+E= +github.com/go-git/go-billy/v5 v5.2.0/go.mod h1:pmpqyWchKfYfrkb/UVH4otLvyi/5gJlGI4Hb3ZqZ3W0= +github.com/go-git/go-billy/v5 v5.3.1 h1:CPiOUAzKtMRvolEKw+bG1PLRpT7D3LIs3/3ey4Aiu34= +github.com/go-git/go-billy/v5 v5.3.1/go.mod h1:pmpqyWchKfYfrkb/UVH4otLvyi/5gJlGI4Hb3ZqZ3W0= +github.com/go-git/go-git-fixtures/v4 v4.2.1/go.mod h1:K8zd3kDUAykwTdDCr+I0per6Y6vMiRR/nnVTBtavnB0= +github.com/go-git/go-git/v5 v5.4.2 h1:BXyZu9t0VkbiHtqrsvdq39UDhGJTl1h55VW6CSC4aY4= +github.com/go-git/go-git/v5 v5.4.2/go.mod h1:gQ1kArt6d+n+BGd+/B/I74HwRTLhth2+zti4ihgckDc= +github.com/google/go-cmp v0.3.0/go.mod h1:8QqcDgzrUqlUb/G2PQTWiueGozuR1884gddMywk6iLU= +github.com/imdario/mergo v0.3.12 h1:b6R2BslTbIEToALKP7LxUvijTsNI9TAe80pLWN2g/HU= +github.com/imdario/mergo v0.3.12/go.mod h1:jmQim1M+e3UYxmgPu/WyfjB3N3VflVyUjjjwH0dnCYA= +github.com/jbenet/go-context v0.0.0-20150711004518-d14ea06fba99 h1:BQSFePA1RWJOlocH6Fxy8MmwDt+yVQYULKfN0RoTN8A= +github.com/jbenet/go-context v0.0.0-20150711004518-d14ea06fba99/go.mod h1:1lJo3i6rXxKeerYnT8Nvf0QmHCRC1n8sfWVwXF2Frvo= +github.com/jessevdk/go-flags v1.5.0/go.mod h1:Fw0T6WPc1dYxT4mKEZRfG5kJhaTDP9pj1c2EWnYs/m4= +github.com/kevinburke/ssh_config v0.0.0-20201106050909-4977a11b4351 h1:DowS9hvgyYSX4TO5NpyC606/Z4SxnNYbT+WX27or6Ck= +github.com/kevinburke/ssh_config v0.0.0-20201106050909-4977a11b4351/go.mod h1:CT57kijsi8u/K/BOFA39wgDQJ9CxiF4nAY/ojJ6r6mM= +github.com/konsorten/go-windows-terminal-sequences v1.0.1/go.mod h1:T0+1ngSBFLxvqU3pZ+m/2kptfBszLMUkC4ZK/EgS/cQ= +github.com/kr/pretty v0.1.0/go.mod h1:dAy3ld7l9f0ibDNOQOHHMYYIIbhfbHSm3C4ZsoJORNo= +github.com/kr/pretty v0.2.1/go.mod h1:ipq/a2n7PKx3OHsz4KJII5eveXtPO4qwEXGdVfWzfnI= +github.com/kr/pty v1.1.1/go.mod h1:pFQYn66WHrOpPYNljwOMqo10TkYh1fy3cYio2l3bCsQ= +github.com/kr/text v0.1.0/go.mod h1:4Jbv+DJW3UT/LiOwJeYQe1efqtUx/iVham/4vfdArNI= +github.com/kr/text v0.2.0/go.mod h1:eLer722TekiGuMkidMxC/pM04lWEeraHUUmBw8l2grE= +github.com/matryer/is v1.2.0/go.mod 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+gopkg.in/warnings.v0 v0.1.2 h1:wFXVbFY8DY5/xOe1ECiWdKCzZlxgshcYVNkBHstARME= +gopkg.in/warnings.v0 v0.1.2/go.mod h1:jksf8JmL6Qr/oQM2OXTHunEvvTAsrWBLb6OOjuVWRNI= +gopkg.in/yaml.v2 v2.2.2/go.mod h1:hI93XBmqTisBFMUTm0b8Fm+jr3Dg1NNxqwp+5A1VGuI= +gopkg.in/yaml.v2 v2.2.4/go.mod h1:hI93XBmqTisBFMUTm0b8Fm+jr3Dg1NNxqwp+5A1VGuI= +gopkg.in/yaml.v2 v2.3.0/go.mod h1:hI93XBmqTisBFMUTm0b8Fm+jr3Dg1NNxqwp+5A1VGuI= +gopkg.in/yaml.v3 v3.0.0-20200313102051-9f266ea9e77c/go.mod h1:K4uyk7z7BCEPqu6E+C64Yfv1cQ7kz7rIZviUmN+EgEM= diff --git a/util/docker/coreboot.org-status/board-status.html/logs.go b/util/docker/coreboot.org-status/board-status.html/logs.go new file mode 100644 index 0000000..21e91f2 --- /dev/null +++ b/util/docker/coreboot.org-status/board-status.html/logs.go @@ -0,0 +1,165 @@ +package main + +import ( + "fmt" + "io/fs" + "os" + "os/exec" + "path/filepath" + "sort" + "strings" + "time" +) + +// Color returns a HTML color code between green and yellow based on the +// number of days that passed since ds. +func (ds DateString) Color() string { + date, _ := time.Parse("2006-01-02T15:04:05Z", string(ds)) + days := int(time.Since(date).Hours() / 24) + if days > 255 { + days = 255 + } + return fmt.Sprintf("#%02xff00", days) +} + +func fetchLogs(dirs chan<- NamedFS) { + err := fs.WalkDir(bsdirFS, ".", func(path string, d fs.DirEntry, err error) error { + if err != nil { + return err + } + if path[0] == '.' { + return nil + } + if d.IsDir() && len(strings.Split(path, string(filepath.Separator))) == 4 { + dirs <- NamedFS{ + FS: bsdirFS, + Name: path, + } + } + return nil + }) + if err != nil { + fmt.Fprintf(os.Stderr, "Reading logs failed: %v\n", err) + } + close(dirs) +} + +func collectLogs(dirs <-chan NamedFS) { + data.Logs = make(map[Timeframe][]Log) + data.VendorBoardDate = make(map[string]DateString) + data.VendorBoardReferenced = make(map[string]bool) + timeframes := make(map[Timeframe]bool) + gitcache := make(map[string]string) + for dir := range dirs { + upstream := "" + revB, err := fs.ReadFile(dir.FS, filepath.Join(dir.Name, "revision.txt")) + if err != nil { + continue + } + rev := string(revB) + skipDir := false + for _, line := range strings.Split(rev, "\n") { + item := strings.SplitN(line, ":", 2) + if len(item) != 2 { + // This is an error, but let's try to extract + // as much value out of revision.txt files as + // possible, even if some lines are erroneous. + continue + } + if item[0] == "Upstream revision" { + upstream = strings.TrimSpace(item[1]) + // tried using go-git, but its resolver + // couldn't expand short hashes despite the + // docs claiming that it can. + if val, ok := gitcache[upstream]; ok { + upstream = val + } else { + res, err := exec.Command("/usr/bin/git", "-C", cbdir, "log", "-n1", "--format=%H", upstream).Output() + if err != nil { + fmt.Fprintf(os.Stderr, "revision %s not found \n", upstream) + skipDir = true + break + } + gitcache[upstream] = strings.TrimSpace(string(res)) + upstream = gitcache[upstream] + } + } + } + if skipDir { + continue + } + + rawFiles, err := fs.Glob(dir.FS, filepath.Join(dir.Name, "*")) + if err != nil { + fmt.Fprintf(os.Stderr, "Could not fetch log data, skipping: %v\n", err) + continue + } + + pieces := strings.Split(dir.Name, string(filepath.Separator)) + if len(pieces) < 4 { + fmt.Fprintf(os.Stderr, "log directory %s is malformed, skipping\n", dir.Name) + continue + } + vendorBoard := strings.Join(pieces[:2], "/") + // TODO: these need to become "second to last" and "last" item + // but only after compatibility to the current system has been ensured. + dateTimePath := pieces[3] + dateTime, err := time.Parse(time.RFC3339, strings.ReplaceAll(dateTimePath, "_", ":")) + if err != nil { + fmt.Fprintf(os.Stderr, "Could not parse timestamp from %s: %v\n", dir.Name, err) + continue + } + dateTimeNormal := dateTime.UTC().Format("2006-01-02T15:04:05Z") + dateTimeHuman := dateTime.UTC().Format(time.UnixDate) + tfYear, tfWeek := dateTime.ISOWeek() + timeframe := Timeframe(fmt.Sprintf("%dW%02d", tfYear, tfWeek)) + + if !timeframes[timeframe] { + timeframes[timeframe] = true + data.Timeframes = append(data.Timeframes, timeframe) + data.Logs[timeframe] = []Log{} + } + + files := []Path{} + l := len(dir.Name) + 1 + for _, file := range rawFiles { + if file[l:] == "revision.txt" { + continue + } + files = append(files, Path{ + Path: dir.Name + "/", + Basename: file[l:], + }) + } + + data.Logs[timeframe] = append(data.Logs[timeframe], Log{ + VendorBoard: vendorBoard, + Time: dateTimeNormal, + TimeReadable: dateTimeHuman, + Upstream: upstream, + Files: files, + }) + } + sort.Slice(data.Timeframes, func(i, j int) bool { + // reverse sort + return data.Timeframes[i] > data.Timeframes[j] + }) + for bi := range data.Logs { + bucket := data.Logs[bi] + sort.Slice(data.Logs[bi], func(i, j int) bool { + if bucket[i].Time == bucket[j].Time { + return (bucket[i].VendorBoard > bucket[j].VendorBoard) + } + return (bucket[i].Time > bucket[j].Time) + }) + } + for _, ts := range data.Timeframes { + for li, l := range data.Logs[ts] { + if _, match := data.VendorBoardDate[l.VendorBoard]; match { + continue + } + data.VendorBoardDate[l.VendorBoard] = DateString(l.Time) + data.Logs[ts][li].Reference = true + } + } +} diff --git a/util/docker/coreboot.org-status/board-status.html/status-to-html.go b/util/docker/coreboot.org-status/board-status.html/status-to-html.go new file mode 100644 index 0000000..ae341fa --- /dev/null +++ b/util/docker/coreboot.org-status/board-status.html/status-to-html.go @@ -0,0 +1,92 @@ +package main + +import ( + "embed" + "errors" + "flag" + "fmt" + "html/template" + "io/fs" + "os" + "path/filepath" +) + +//go:embed templates +var templates embed.FS + +var data = TemplateData{ + Categories: []Category{ + "laptop", + "server", + "desktop", + "half", + "mini", + "settop", + "eval", + "sbc", + "emulation", + "misc", + "unclass", + }, + CategoryNiceNames: map[Category]string{ + "desktop": "Desktops / Workstations", + "server": "Servers", + "laptop": "Laptops", + "half": "Embedded / PC/104 / Half-size boards", + "mini": "Mini-ITX / Micro-ITX / Nano-ITX", + "settop": "Set-top-boxes / Thin clients", + "eval": "Devel/Eval Boards", + "sbc": "Single-Board computer", + "emulation": "Emulation", + "misc": "Miscellaneous", + "unclass": "Unclassified", + }, + BoardsByCategory: map[Category][]Board{}, +} + +var ( + cbdirFS fs.FS + cbdir string + bsdirFS fs.FS +) + +func main() { + var cbDir, bsDir string + flag.StringVar(&cbDir, "coreboot-dir", filepath.Join("..", "coreboot.git"), "coreboot.git checkout") + flag.StringVar(&bsDir, "board-status-dir", filepath.Join("..", "board-status.git"), "board-status.git checkout") + flag.Parse() + + tpls, err := template.ParseFS(templates, filepath.Join("templates", "*")) + if err != nil { + fmt.Fprintf(os.Stderr, "Parsing templates failed: %v\n", err) + os.Exit(1) + } + + if _, err := os.Stat(cbDir); errors.Is(err, os.ErrNotExist) { + fmt.Fprintf(os.Stderr, "coreboot root %s does not exist\n", cbDir) + os.Exit(1) + } + + if _, err := os.Stat(bsDir); errors.Is(err, os.ErrNotExist) { + fmt.Fprintf(os.Stderr, "board-status dir %s does not exist\n", bsDir) + os.Exit(1) + } + + cbdirFS = os.DirFS(cbDir) + cbdir = cbDir + bsdirFS = os.DirFS(bsDir) + + dirs := make(chan NamedFS) + go fetchLogs(dirs) + collectLogs(dirs) + + dirs = make(chan NamedFS) + go fetchBoards(dirs) + collectBoards(dirs) + + err = tpls.ExecuteTemplate(os.Stdout, "board-status.html", data) + if err != nil { + fmt.Fprintf(os.Stderr, "Executing template failed: %v\n", err) + os.Exit(1) + } +} diff --git a/util/docker/coreboot.org-status/board-status.html/templates/board-status.html b/util/docker/coreboot.org-status/board-status.html/templates/board-status.html new file mode 100644 index 0000000..93fcc45 --- /dev/null +++ b/util/docker/coreboot.org-status/board-status.html/templates/board-status.html @@ -0,0 +1,133 @@ +{{$data := . -}} +{{- define "colorcode" -}} +{{- if eq . "n" }}<td style="background:red">N</td>{{else + if eq . "y" }}<td style="background:lime">Y</td>{{else + if eq . "" }}<td>?</td>{{else + }}<td>{{.}}</td>{{end -}} +{{end -}} +<html> +<head> + <meta charset="utf-8"> + <title>status report for coreboot boards</title> +</head> +<body> +<h1>Mainboards supported by coreboot</h1> + +This page shows two representations of the same data: + +First a list of all mainboards supported by coreboot (current within +one hour) ordered by category. For each mainboard the table shows the +latest user-contributed report of a successful boot on the device. + +After that, the page provides a time-ordered list of these contributed +reports, with the newest report first. + +Boards without such reports may boot or there may be some maintenance +required. The reports contain the coreboot configuration and precise commit +id, so it is possible to reproduce the build. + +We encourage developers and users to contribute reports so we know which +devices are well-tested. We have +<a href='https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/ut…'>a tool in the coreboot repository</a> +to make contributing easy. The data resides in the +<a href='https://review.coreboot.org/plugins/gitiles/board-status/'>board status repository</a>. +Contributing requires an account on review.coreboot.org. After +logging into the site with your preferred OpenID or GitHub/Google +credentials, you can get a user name and password for git pushes on <a +href="https://review.coreboot.org/settings/#HTTPCredentials">gerrit's +settings screen</a>. + +Sometimes the same board is sold under different names, we've tried to +list all known names but some names might be missing. + +If the board is not found in the coreboot's source code, there might +be some form of support that is not ready yet for inclusion in coreboot, +usually people willing to send their patches to coreboot goes through +<a href='https://review.coreboot.org'>gerrit</a>, so looking there could find some +code for boards that are not yet merged. + +<h1>Vendor trees</h1> +Some vendors have their own coreboot trees/fork, for instance: +<ul> + <li><a href='https://chromium.googlesource.com/chromiumos/third_party/coreboot/'>chrome/chromium's tree</a> +</ul> + +<h1>Motherboards supported in coreboot</h1> + +<table border="0" style="font-size: smaller"> +<tr bgcolor="#6699ff"> +<td>Vendor</td> +<td>Mainboard</td> +<td>Latest known good</td> +<td>Northbridge</td> +<td>Southbridge</td> +<td>Super I/O</td> +<td>CPU</td> +<td>Socket</td> +<td>ROM 1</td> +<td>P 2</td> +<td>S 3</td> +<td>F 4</td> +<td>VCS5</td> +</tr> +{{range $category := .Categories -}} +<tr bgcolor="#6699ff"> +<td colspan="13"><h4>{{index $data.CategoryNiceNames $category}}</h4></td> +</tr> + +{{$color := "#eeeeee" -}} +{{$oldVendor := "" -}} +{{range $b := index $data.BoardsByCategory $category -}} +{{if ne $oldVendor $b.VendorNice}}{{$oldVendor = $b.VendorNice -}} +{{if eq $color "#dddddd"}}{{$color = "#eeeeee"}}{{else}}{{$color = "#dddddd"}}{{end -}} +{{end -}} +<tr bgcolor="{{$color}}"> +<td>{{if $b.BoardURL}}<a href='{{$b.BoardURL}}'>{{$b.VendorNice}}</a>{{else}}{{$b.VendorNice}}{{end}} +{{if $b.Vendor2nd}} ({{$b.Vendor2nd}}) +{{end -}} +</td><td><a href='https://www.coreboot.org/Board:{{$b.Vendor}}/{{$b.Board}}'>{{$b.BoardNice}}</a></td> +{{if eq "" (index $data.VendorBoardDate $b.VendorBoard) -}} +<td style="background:red">Unknown</td> +{{- else -}} +{{- $date := index $data.VendorBoardDate $b.VendorBoard -}} +<td style="background:{{ $date.Color }}"><a href='#{{ $b.VendorBoard }}'>{{ $date }}</a></td> +{{- end}} +<td>{{$b.NorthbridgeNice}}</td> +<td>{{$b.SouthbridgeNice}}</td> +<td>{{$b.SuperIONice}}</td> +<td>{{$b.CPUNice}}</td> +<td>{{$b.SocketNice}}</td> +<td>{{$b.ROMPackage}}</td> +<td>{{$b.ROMProtocol}}</td> +{{template "colorcode" $b.ROMSocketed}} +{{template "colorcode" $b.FlashromSupport}} +<td>{{$b.VendorCooperationScore}} +</td></tr> +{{end -}} +{{end -}} +</table> + +1 ROM chip package (PLCC, DIP32, DIP8, SOIC8). +2 ROM chip protocol/type (parallel flash, LPC, FWH, SPI). +3 ROM chip socketed (Y/N)? +4 Board supported by [http://www.flashrom.org flashrom] (Y/N)? +5 Vendor Cooperation Score. +6 [http://www.flashrom.org flashrom] does not work when the vendor BIOS is booted, but it does work when the machine is booted with coreboot. +7 Some boards have ROM sockets, others are soldered. + +{{range $t := .Timeframes -}} +<h1>{{$t}}</h1> +{{range $l := index $data.Logs $t -}} +{{if $l.Reference}} +{{end -}} +<a href='https://www.coreboot.org/Board:{{$l.VendorBoard}}'>{{$l.VendorBoard}}</a> at {{$l.TimeReadable}} +<a href='https://review.coreboot.org/plugins/gitiles/coreboot/+/{{$l.Upstream}}'>upstream tree</a> ( +{{range $f := $l.Files -}} +<a href='https://review.coreboot.org/plugins/gitiles/board-status/+/refs/heads/maste…'>{{$f.Basename}}</a> {{/* */}} +{{end -}} +) +{{- end -}} +{{end -}} +{{/* */}} +</body> +</html> diff --git a/util/docker/coreboot.org-status/board-status.html/types.go b/util/docker/coreboot.org-status/board-status.html/types.go new file mode 100644 index 0000000..93094d3 --- /dev/null +++ b/util/docker/coreboot.org-status/board-status.html/types.go @@ -0,0 +1,60 @@ +package main + +import ( + "io/fs" +) + +type Board struct { + Vendor string + VendorNice string + Vendor2nd string + VendorBoard string + Board string + BoardNice string + BoardURL string + NorthbridgeNice string + SouthbridgeNice string + SuperIONice string + CPUNice string + SocketNice string + ROMPackage string + ROMProtocol string + ROMSocketed string + FlashromSupport string + VendorCooperationScore string + VendorCooperationPage string +} + +type Path struct { + Path string + Basename string +} + +type Log struct { + Reference bool + VendorBoard string + Time string + TimeReadable string + Upstream string + Files []Path +} + +type Category string +type Timeframe string + +type DateString string + +type TemplateData struct { + Categories []Category + CategoryNiceNames map[Category]string + BoardsByCategory map[Category][]Board + Timeframes []Timeframe + Logs map[Timeframe][]Log + VendorBoardDate map[string]DateString + VendorBoardReferenced map[string]bool +} + +type NamedFS struct { + FS fs.FS + Name string +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fab86d24088e4f9eff434c21ce9caa077f3f9e2 Gerrit-Change-Number: 59958 Gerrit-PatchSet: 19 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/amd/morgana/data_fabric: Add register bitslice struct
by Felix Held (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69071 ) Change subject: soc/amd/morgana/data_fabric: Add register bitslice struct ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69071/comment/49fc3a50_6141bb2f PS1, Line 11: please also mention that you update bot IOMS0_FABRIC_ID and DF_MMIO_NP in this patch in the commit message -- To view, visit https://review.coreboot.org/c/coreboot/+/69071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If64c875026b643c584975f7abffad9b35f1a7b44 Gerrit-Change-Number: 69071 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 13:44:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: lib/coreboot_table: Rename lb_fill_pcie
by Hung-Te Lin (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Arthur Heymans. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69183 ) Change subject: lib/coreboot_table: Rename lb_fill_pcie ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I046016b3898308bb56b4ad6a5834ab942fdd50f2 Gerrit-Change-Number: 69183 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 03 Nov 2022 13:40:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: payloads: Make PAYLOAD_NONE a bool outside of the choice
by Sean Rhodes (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Martin L Roth, Martin Roth. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68595 ) Change subject: payloads: Make PAYLOAD_NONE a bool outside of the choice ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I932c65630261a5b39809abf4dfbda5bf932c6684 Gerrit-Change-Number: 68595 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 13:40:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: lib/coreboot_table: Simplify API to set up lb_serial
by Hung-Te Lin (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Julius Werner, Arthur Heymans, ron minnich. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68768 ) Change subject: lib/coreboot_table: Simplify API to set up lb_serial ...................................................................... Patch Set 11: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c08a88fb5fc035eb28d0becf19471c709c8043d Gerrit-Change-Number: 68768 Gerrit-PatchSet: 11 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 13:40:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/amd: Specify memory types supported by each chip
by Sean Rhodes (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Fred Reitberger, Felix Held. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68994 ) Change subject: soc/amd: Specify memory types supported by each chip ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c7f47b43d8d4a89630fbd645a725e61d74bc2a5 Gerrit-Change-Number: 68994 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Nov 2022 13:40:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: lib/coreboot_table: Simplify API to set up lb_serial
by Hung-Te Lin (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Julius Werner, Arthur Heymans, ron minnich. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68768 ) Change subject: lib/coreboot_table: Simplify API to set up lb_serial ...................................................................... Patch Set 11: (1 comment) File src/lib/coreboot_table.c: https://review.coreboot.org/c/coreboot/+/68768/comment/dc1a7999_5b517081 PS11, Line 498: lb_add_serial if you look at all lb_XXX calls in this function, they don't have 'add' (except the lb_add_console and lb_add_acpi_rsdp). Maybe lb_serial is a better name? But I'm fine either way. -- To view, visit https://review.coreboot.org/c/coreboot/+/68768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c08a88fb5fc035eb28d0becf19471c709c8043d Gerrit-Change-Number: 68768 Gerrit-PatchSet: 11 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 13:40:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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