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Change subject: include/device/pci_def.h: Add some PCIe DPC/AER definitions
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69106/comment/d8f94bb0_8d98d052
PS2, Line 7: inc/dev: Add some PCIe DPC/AER definitions
> I would prefer not to short it "include/device/pci_def. […]
Ack
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/meteorlake: Provide mitigation support for CNVi RFI
......................................................................
soc/intel/meteorlake: Provide mitigation support for CNVi RFI
The DDR RFIM is a frequency shifting RFI mitigation feature required by
the Intel integrated Wi-Fi firmware(CNVi) for Meteor Lake. Please refer
to Intel technical white paper 640438_Intel_DDR_Mem_RFIM_Policy_Enable
once it is externally available. This change has backport changes from
commit hash 6f73a20 (soc/intel/alderlake: Move CnviDdrRfim property to
drivers) and provides the CNVi RFIM support for Meteor Lake. This patch
also alphabetically orders all fill_fspm_xxx_params functions.
BUG=b:248391777
TEST=Booted to OS on Rex. Looked the DDR_DVFS_RFI_CONFIG_PCU_REG
register at the offset 0x5A40 of Mchbar and verified the BIT0
(RFI_DISABLE bit) is 0.
Change-Id: I87110bc10b98a27a8f274680597b15a1df488824
Signed-off-by: zhaojohn <john.zhao(a)intel.com>
---
M src/soc/intel/meteorlake/romstage/fsp_params.c
1 file changed, 137 insertions(+), 100 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/67789/9
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Change subject: soc/intel/meteorlake: Provide mitigation support for CNVi RFI
......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/meteorlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/67789/comment/3609a82e_8ce6c505
PS7, Line 289: fill_fspm_audio_params,
: fill_fspm_cnvi_params,
: fill_fspm_cpu_params,
: fill_fspm_igd_params,
: fill_fspm_ipu_params,
: fill_fspm_ish_params,
: fill_fspm_misc_params,
: fill_fspm_mrc_params,
: fill_fspm_pcie_rp_params,
: fill_fspm_security_params,
: fill_fspm_smbus_params,
: fill_fspm_tcss_params,
: fill_fspm_trace_params,
: fill_fspm_uart_params,
: fill_fspm_usb4_params,
: fill_fspm_vtd_params,
> Done
I request you not to take the alphabetically modification in the same CL. As there is no such rule that function calling has to be alphabetically ordered.
Please just keep this CL meaningful.
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Change subject: soc/intel/meteorlake: Provide mitigation support for CNVi RFI
......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/meteorlake/romstage/fsp_params.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162296):
https://review.coreboot.org/c/coreboot/+/67789/comment/dce7f7f8_f12d74e9
PS8, Line 241: if (CONFIG(SOC_INTEL_CRASHLOG)) {
braces {} are not necessary for single statement blocks
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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/67789
to look at the new patch set (#8).
Change subject: soc/intel/meteorlake: Provide mitigation support for CNVi RFI
......................................................................
soc/intel/meteorlake: Provide mitigation support for CNVi RFI
The DDR RFIM is a frequency shifting RFI mitigation feature required by
the Intel integrated Wi-Fi firmware(CNVi) for Meteor Lake. Please refer
to Intel technical white paper 640438_Intel_DDR_Mem_RFIM_Policy_Enable
once it is externally available. This change has backport changes from
commit hash 6f73a20 (soc/intel/alderlake: Move CnviDdrRfim property to
drivers) and provides the CNVi RFIM support for Meteor Lake. This patch
also alphabetically orders all fill_fspm_xxx_params functions.
BUG=b:248391777
TEST=Booted to OS on Rex. Looked the DDR_DVFS_RFI_CONFIG_PCU_REG
register at the offset 0x5A40 of Mchbar and verified the BIT0
(RFI_DISABLE bit) is 0.
Change-Id: I87110bc10b98a27a8f274680597b15a1df488824
Signed-off-by: zhaojohn <john.zhao(a)intel.com>
---
M src/soc/intel/meteorlake/romstage/fsp_params.c
1 file changed, 138 insertions(+), 100 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/67789/8
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Change subject: soc/qualcomm/sc7280: Move AOP load and reset handle to Romstage
......................................................................
Patch Set 18:
(1 comment)
Patchset:
PS18:
I'm not seeing the 110ms boot time savings on herobrine, but it does seem to save something. I'll try to get real numbers on an official build after this lands.
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