coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/intel/alderlake: Hook up GMA ACPI brightness controls
by Felix Held (Code Review) 03 Nov '22

03 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69076 ) Change subject: soc/intel/alderlake: Hook up GMA ACPI brightness controls ...................................................................... soc/intel/alderlake: Hook up GMA ACPI brightness controls Add function needed to generate ACPI backlight control SSDT, along with Kconfig values for accessing the registers. Tested by adding gfx register on system76/lemp11. Backlight controls work on Windows 10 and Linux 6.1. Change-Id: I1cc33bf0121ff44aea68a7e3615c5e58e2ab6ce2 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69076 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/chip.h A src/soc/intel/alderlake/graphics.c 4 files changed, 47 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index cbc02e7..08d4132 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -484,4 +484,16 @@ help Set this option if debug build of FSP is used. +config INTEL_GMA_BCLV_OFFSET + default 0xc8258 + +config INTEL_GMA_BCLV_WIDTH + default 32 + +config INTEL_GMA_BCLM_OFFSET + default 0xc8254 + +config INTEL_GMA_BCLM_WIDTH + default 32 + endif diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index a4c6336..7f808ff 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -32,6 +32,7 @@ ramstage-y += espi.c ramstage-y += finalize.c ramstage-y += fsp_params.c +ramstage-y += graphics.c ramstage-y += hsphy.c ramstage-y += lockdown.c ramstage-y += me.c diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index a1a8fb3..46721b0 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -4,6 +4,7 @@ #define _SOC_CHIP_H_ #include <drivers/i2c/designware/dw_i2c.h> +#include <drivers/intel/gma/gma.h> #include <device/pci_ids.h> #include <intelblocks/cfg.h> #include <intelblocks/gpio.h> @@ -647,6 +648,9 @@ * Default is set to 0 and set to 1 to skip the MBP HOB. */ bool skip_mbp_hob; + + /* i915 struct for GMA backlight control */ + struct i915_gpu_controller_info gfx; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/graphics.c b/src/soc/intel/alderlake/graphics.c new file mode 100644 index 0000000..f2c792c --- /dev/null +++ b/src/soc/intel/alderlake/graphics.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <intelblocks/graphics.h> +#include <soc/ramstage.h> + +const struct i915_gpu_controller_info * +intel_igd_get_controller_info(const struct device *const dev) +{ + const struct soc_intel_alderlake_config *const chip = dev->chip_info; + return &chip->gfx; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/69076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cc33bf0121ff44aea68a7e3615c5e58e2ab6ce2 Gerrit-Change-Number: 69076 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/ocp/deltalake: Revert OVERRIDE_UART_FOR_CONSOLE
by Felix Held (Code Review) 03 Nov '22

03 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56468 ) Change subject: mb/ocp/deltalake: Revert OVERRIDE_UART_FOR_CONSOLE ...................................................................... mb/ocp/deltalake: Revert OVERRIDE_UART_FOR_CONSOLE This reverts commit f6efeae66c (mb/ocp/deltalake: Override uart base address via VPD variable). Both SOL and UART would use 0x2f8, disabling it can also avoid searching flash VPD during each UART tx. Change-Id: I453fdddbb883eb956bac708913c17bb581f75b9d Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56468 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang(a)fb.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/ocp/deltalake/Makefile.inc M src/mainboard/ocp/deltalake/romstage.c D src/mainboard/ocp/deltalake/uartio_vpd.c M src/mainboard/ocp/deltalake/vpd.h 5 files changed, 19 insertions(+), 28 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Jonathan Zhang: Looks good to me, approved diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index dbf4a2e..74212f9 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -16,7 +16,6 @@ select IPMI_OCP select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM2 - select OVERRIDE_UART_FOR_CONSOLE config UART_FOR_CONSOLE int diff --git a/src/mainboard/ocp/deltalake/Makefile.inc b/src/mainboard/ocp/deltalake/Makefile.inc index 08db2c7..245a6d6 100644 --- a/src/mainboard/ocp/deltalake/Makefile.inc +++ b/src/mainboard/ocp/deltalake/Makefile.inc @@ -8,5 +8,4 @@ ramstage-y += ramstage.c ipmi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c all-$(CONFIG_CONSOLE_OVERRIDE_LOGLEVEL) += loglevel_vpd.c -all-$(CONFIG_OVERRIDE_UART_FOR_CONSOLE) += uartio_vpd.c CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index 2efed1c..23bbffe 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <console/uart.h> #include <drivers/ipmi/ipmi_if.h> #include <drivers/ipmi/ocp/ipmi_ocp.h> #include <drivers/vpd/vpd.h> @@ -60,10 +59,7 @@ "SerialIoUartDebugEnable to %d\n", FSP_LOG, FSP_LOG_DEFAULT); mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; } - - /* Select UART IO of FSP */ - static const unsigned int bases[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; - mupd->FspmConfig.SerialIoUartDebugIoBase = bases[get_uart_for_console()]; + mupd->FspmConfig.SerialIoUartDebugIoBase = 0x2f8; if (mupd->FspmConfig.SerialIoUartDebugEnable) { /* FSP debug log level */ diff --git a/src/mainboard/ocp/deltalake/uartio_vpd.c b/src/mainboard/ocp/deltalake/uartio_vpd.c deleted file mode 100644 index 4c2d876..0000000 --- a/src/mainboard/ocp/deltalake/uartio_vpd.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <drivers/vpd/vpd.h> -#include <console/uart.h> - -#include "vpd.h" - -unsigned int get_uart_for_console(void) -{ - int val_int = COREBOOT_UART_IO_DEFAULT; - - if (vpd_get_int(COREBOOT_UART_IO, VPD_RW_THEN_RO, (int *const) &val_int)) { - if (val_int > 3) - val_int = COREBOOT_UART_IO_DEFAULT; - } - return val_int; -} diff --git a/src/mainboard/ocp/deltalake/vpd.h b/src/mainboard/ocp/deltalake/vpd.h index fb33ef2..f927134 100644 --- a/src/mainboard/ocp/deltalake/vpd.h +++ b/src/mainboard/ocp/deltalake/vpd.h @@ -37,10 +37,6 @@ #define FSPM_MEMREFRESHWATERMARK "fspm_mem_refresh_watermark" #define FSPM_MEMREFRESHWATERMARK_DEFAULT 1 -/* coreboot uart io select: 0 = 0x3f8, 1 = 0x2f8, 2 = 0x3e8, 3 = 0x2e8 */ -#define COREBOOT_UART_IO "coreboot_uart_io" -#define COREBOOT_UART_IO_DEFAULT 1 - /* FSP dimm frequency limit, 0:Auto, 1:DDR_1333, 2:DDR_1600, 3:DDR_1866, 4:DDR_2133, * 5:DDR_2400, 6:DDR_2666, 7:DDR_2933, 8:DDR_3200 */ #define FSP_DIMM_FREQ "fsp_dimm_freq" -- To view, visit https://review.coreboot.org/c/coreboot/+/56468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I453fdddbb883eb956bac708913c17bb581f75b9d Gerrit-Change-Number: 56468 Gerrit-PatchSet: 5 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Rocky Phagura Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/skyrim: Disable SD ASPM
by Felix Held (Code Review) 03 Nov '22

03 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68940 ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/skyrim: Disable SD ASPM ...................................................................... mb/google/skyrim: Disable SD ASPM Disable ASPM on SD until b/245550573 is root-caused/fixed. Logical_lane 1 on winterhold is EMMC device. Disable ASPM for suspend issue. BUG=b:249914847, b:245550573 TEST=emerge-skyrim coreboot chromeos-bootimage and test on whiterun proto emmc sku with suspend_stress_test -c 10 Change-Id: If080cdb517a3f22aa89c8053fb6bba9e931c6f76 Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68940 Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Tim Van Patten <timvp(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/skyrim/port_descriptors.c 1 file changed, 25 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Fred Reitberger: Looks good to me, approved Tim Van Patten: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/skyrim/port_descriptors.c b/src/mainboard/google/skyrim/port_descriptors.c index 91316b3..c7b1a8b 100644 --- a/src/mainboard/google/skyrim/port_descriptors.c +++ b/src/mainboard/google/skyrim/port_descriptors.c @@ -28,7 +28,7 @@ .function_number = PCI_FUNC(SD_DEVFN), .link_speed_capability = GEN3, .turn_off_unused_lanes = true, - .link_aspm = ASPM_L1, + .link_aspm = ASPM_DISABLED, // TODO: switch to ASPM_L1 after b:245550573 .link_hotplug = 3, .gpio_group_id = GPIO_27, .clk_req = CLK_REQ1, -- To view, visit https://review.coreboot.org/c/coreboot/+/68940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If080cdb517a3f22aa89c8053fb6bba9e931c6f76 Gerrit-Change-Number: 68940 Gerrit-PatchSet: 9 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: tests: Add option for debug symbols & no optimization
by Felix Held (Code Review) 03 Nov '22

03 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67918 ) Change subject: tests: Add option for debug symbols & no optimization ...................................................................... tests: Add option for debug symbols & no optimization To make it easier to build the tests with debug symbols, add a check for the "GDB_DEBUG" environment variable. If set, build with -g and -Og to enable the symbols and disable optimization. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I3a644dcccb7e15473413b775da8f70617afaefce Reviewed-on: https://review.coreboot.org/c/coreboot/+/67918 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jakub Czapiga <jacz(a)semihalf.com> --- M tests/Makefile.inc 1 file changed, 25 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Jakub Czapiga: Looks good to me, approved diff --git a/tests/Makefile.inc b/tests/Makefile.inc index 2c1a30b..90f01d1 100644 --- a/tests/Makefile.inc +++ b/tests/Makefile.inc @@ -10,7 +10,13 @@ include $(top)/tests/Makefile.common -# Enable code coverage if COV=1 +# Enable GDB debug build if requested +GDB_DEBUG ?= 0 +ifneq ($(GDB_DEBUG),0) +TEST_CFLAGS += -g -Og +endif + +# Enable code coverage if requested ifeq ($(COV),1) TEST_CFLAGS += --coverage TEST_LDFLAGS += --coverage @@ -175,6 +181,7 @@ help-unit-tests help:: @echo '*** coreboot unit-tests targets ***' @echo ' Use "COV=1 make [target]" to enable code coverage for unit tests' + @echo ' Use "GDB_DEBUG=1 make [target]" to build with debug symbols' @echo ' unit-tests - Run all unit-tests from tests/' @echo ' clean-unit-tests - Remove unit-tests build artifacts' @echo ' list-unit-tests - List all unit-tests' -- To view, visit https://review.coreboot.org/c/coreboot/+/67918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a644dcccb7e15473413b775da8f70617afaefce Gerrit-Change-Number: 67918 Gerrit-PatchSet: 5 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/block/power_limit: Avoid MSR read if it is not needed
by Werner Zeh (Code Review) 03 Nov '22

03 Nov '22

Werner Zeh has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/69185 ) Change subject: soc/intel/block/power_limit: Avoid MSR read if it is not needed ...................................................................... soc/intel/block/power_limit: Avoid MSR read if it is not needed In function 'set_power_limits' there is a path to bail out early if the Kconfig switch SOC_INTEL_DISABLE_POWER_LIMITS is selected. In this case reading the MSR PLATFORM_INFO is useless and can be avoided. So read it right before the value is needed. This was found by the scanbuild. In addition, fix an unnecessary line break to increase code readability. Change-Id: Ibdededdfd56287fb9b9223e78033a3cd6425e1a2 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/common/block/power_limit/power_limit.c 1 file changed, 22 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/69185/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdededdfd56287fb9b9223e78033a3cd6425e1a2 Gerrit-Change-Number: 69185 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/block/power_limit: Avoid MSR read if it is not needed
by build bot (Jenkins) (Code Review) 03 Nov '22

03 Nov '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69185 ) Change subject: soc/intel/block/power_limit: Avoid MSR read if it is not needed ...................................................................... Patch Set 1: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162284): https://review.coreboot.org/c/coreboot/+/69185/comment/5e49dab8_60404ae4 PS1, Line 16: Found-by: scanbuild Non-standard signature: Found-by: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162284): https://review.coreboot.org/c/coreboot/+/69185/comment/0b0a7e4e_33f853cf PS1, Line 16: Found-by: scanbuild Unrecognized email address: 'scanbuild' -- To view, visit https://review.coreboot.org/c/coreboot/+/69185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdededdfd56287fb9b9223e78033a3cd6425e1a2 Gerrit-Change-Number: 69185 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Nov 2022 12:30:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/block/power_limit: Avoid MSR read if it is not needed
by Werner Zeh (Code Review) 03 Nov '22

03 Nov '22

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69185 ) Change subject: soc/intel/block/power_limit: Avoid MSR read if it is not needed ...................................................................... soc/intel/block/power_limit: Avoid MSR read if it is not needed In function 'set_power_limits' there is a path to bail out early if the Kconfig switch SOC_INTEL_DISABLE_POWER_LIMITS is selected. In this case reading the MSR PLATFORM_INFO is useless and can be avoided. So read it right before the value is needed. In addition, fix an unnecessary line break to increase code readability. Found-by: scanbuild Change-Id: Ibdededdfd56287fb9b9223e78033a3cd6425e1a2 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/common/block/power_limit/power_limit.c 1 file changed, 22 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/69185/1 diff --git a/src/soc/intel/common/block/power_limit/power_limit.c b/src/soc/intel/common/block/power_limit/power_limit.c index dce174b..d7c9077 100644 --- a/src/soc/intel/common/block/power_limit/power_limit.c +++ b/src/soc/intel/common/block/power_limit/power_limit.c @@ -72,7 +72,7 @@ void set_power_limits(u8 power_limit_1_time, struct soc_power_limits_config *conf) { - msr_t msr = rdmsr(MSR_PLATFORM_INFO); + msr_t msr; msr_t limit; unsigned int power_unit; unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; @@ -96,9 +96,9 @@ } if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) - power_limit_1_time = - ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; + power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; + msr = rdmsr(MSR_PLATFORM_INFO); if (!(msr.lo & PLATFORM_INFO_SET_TDP)) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/69185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdededdfd56287fb9b9223e78033a3cd6425e1a2 Gerrit-Change-Number: 69185 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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[XL] Change in coreboot[master]: util/docker/coreboot.org-status: Rewrite parser
by Maxim Polyakov (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Patrick Georgi, Martin L Roth, ron minnich. Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59958 ) Change subject: util/docker/coreboot.org-status: Rewrite parser ...................................................................... Patch Set 18: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fab86d24088e4f9eff434c21ce9caa077f3f9e2 Gerrit-Change-Number: 59958 Gerrit-PatchSet: 18 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 12:19:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/var/craask: Modify DPTF related settings
by Tyler Wang (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Kangheui Won, Ren Kuo, Tim Wawrzynczak, Reka Norman, Tyler Wang, Vidya Gopalakrishnan, Peter Ou. Hello build bot (Jenkins), Kangheui Won, Ren Kuo, Reka Norman, Tim Wawrzynczak, Vidya Gopalakrishnan, Angel Pons, Peter Ou, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68523 to look at the new patch set (#5). Change subject: mb/google/nissa/var/craask: Modify DPTF related settings ...................................................................... mb/google/nissa/var/craask: Modify DPTF related settings Request by thermal team, make below change: tdp_pl2_override: 12 --> 25 pl1.min_power: 3000 --> 5500 pl1.time_window_max: 32 * MSECS_PER_SEC --> 28 * MSECS_PER_SEC pl2.min_power: 12000 --> 25000 pl2.max_power: 12000 --> 25000 pl2.time_window_min: 28 * MSECS_PER_SEC --> 0 * MSECS_PER_SEC BUG=b:239495499 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Change-Id: I88c8c4e6798ec5bc2930dd713e8c8b2c543cfaf9 --- M src/mainboard/google/brya/variants/craask/overridetree.cb 1 file changed, 29 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/68523/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/68523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88c8c4e6798ec5bc2930dd713e8c8b2c543cfaf9 Gerrit-Change-Number: 68523 Gerrit-PatchSet: 5 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cathy Chen <cathy_chen(a)quanta.corp-partner.google.com> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-CC: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.corp-partner.google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.corp-partner.google.com> Gerrit-Attention: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/rex: Fix fw_config probe for UFC and WFC
by Tarun Tuli (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Kapil Porwal. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69152 ) Change subject: mb/google/rex: Fix fw_config probe for UFC and WFC ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5103e7da04004414d96f42057c105cf9fbf51b25 Gerrit-Change-Number: 69152 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 11:54:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2022