coreboot-gerrit November 2022

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[S] Change in coreboot[master]: commonlib: Reserve 0x50-0x5f postcodes for SoC/CPU/chipset
by Martin L Roth (Code Review) 04 Nov '22

04 Nov '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69203 ) Change subject: commonlib: Reserve 0x50-0x5f postcodes for SoC/CPU/chipset ...................................................................... commonlib: Reserve 0x50-0x5f postcodes for SoC/CPU/chipset Postcodes 0x50 to 0x5f are currently unallocated in post_codes.h. Reserve these values for SoC use. SoCs are currently using a variety of different values, so should be moved into this range where possible. If for some reason, the SoC vendors don't want to use this range, I'm fine with that, but this is the range that there shouldn't be conflicts with other coreboot codes. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ic9eeb05f66b66899b8471215c38af54eda816c8a --- M src/commonlib/include/commonlib/console/post_codes.h 1 file changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/69203/1 diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h index d838815..7513595 100644 --- a/src/commonlib/include/commonlib/console/post_codes.h +++ b/src/commonlib/include/commonlib/console/post_codes.h @@ -111,6 +111,31 @@ #define POST_CONSOLE_BOOT_MSG 0x40 /** + * @brief SoC/CPU/Chipset reserved postcodes + * + * The postcodes 0x50 to 0x5f are reserved for SoC specific functions. + * While there is no restriction on how these are used, it is recommended + * that the general flow be from lower values to higher values. It is + * further recommended that 0x5f be used if there is a fatal error. + */ +#define POST_SOC_SPECIFIC_0 0x50 +#define POST_SOC_SPECIFIC_1 0x51 +#define POST_SOC_SPECIFIC_2 0x52 +#define POST_SOC_SPECIFIC_3 0x53 +#define POST_SOC_SPECIFIC_4 0x54 +#define POST_SOC_SPECIFIC_5 0x55 +#define POST_SOC_SPECIFIC_6 0x56 +#define POST_SOC_SPECIFIC_7 0x57 +#define POST_SOC_SPECIFIC_8 0x58 +#define POST_SOC_SPECIFIC_9 0x59 +#define POST_SOC_SPECIFIC_10 0x5a +#define POST_SOC_SPECIFIC_11 0x5b +#define POST_SOC_SPECIFIC_12 0x5c +#define POST_SOC_SPECIFIC_13 0x5d +#define POST_SOC_SPECIFIC_14 0x5e +#define POST_SOC_SPECIFIC_15 0x5f + +/** * \brief Before enabling the cache * * Going to enable the cache -- To view, visit https://review.coreboot.org/c/coreboot/+/69203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9eeb05f66b66899b8471215c38af54eda816c8a Gerrit-Change-Number: 69203 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: lib/ramtest.c: Update ram failure post code
by Martin L Roth (Code Review) 04 Nov '22

04 Nov '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69202 ) Change subject: lib/ramtest.c: Update ram failure post code ...................................................................... lib/ramtest.c: Update ram failure post code coreboot already has a ram failure post code defined, but the ram test functions weren't using it, and were using 0xea instead. This changes those failures to display 0xe3, the value defined in post_codes.h by POST_RAM_FAILURE. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I21ef196e48ff37ffe320b575d6de66b43997e7eb --- M src/lib/ramtest.c 1 file changed, 17 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/69202/1 diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index d6f958f..7ac141a 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -110,7 +110,7 @@ } } if (failures) { - post_code(0xea); + post_code(POST_RAM_FAILURE); printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n"); return 1; } @@ -200,7 +200,7 @@ write_phys(dst, backup); if (fail) { - post_code(0xea); + post_code(POST_RAM_FAILURE); die("RAM INIT FAILURE!\n"); } phys_memory_barrier(); -- To view, visit https://review.coreboot.org/c/coreboot/+/69202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21ef196e48ff37ffe320b575d6de66b43997e7eb Gerrit-Change-Number: 69202 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: device & commonlib: Update pci_scan_bus postcodes
by Martin L Roth (Code Review) 04 Nov '22

04 Nov '22

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69201 to look at the new patch set (#2). Change subject: device & commonlib: Update pci_scan_bus postcodes ...................................................................... device & commonlib: Update pci_scan_bus postcodes The function pci_scan_bus had 3 post codes in it: 0x24 - beginning 0x25 - middle 0x55 - end I got rid of the middle postcode and used 0x25 for the code signifying the end of the function. I don't think all three are needed. 0x24 & 0x25 postcodes are currently also used in intel cache-as-ram code. Those postcodes should be adjusted to avoid conflicting. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I19c9d5e256505b64234919a99f73a71efbbfdae3 --- M src/commonlib/include/commonlib/console/post_codes.h M src/device/pci_device.c 2 files changed, 37 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/69201/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19c9d5e256505b64234919a99f73a71efbbfdae3 Gerrit-Change-Number: 69201 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: Revert "cpu/x86/mp_init.c: Set a bogus initial lapic_id"
by 9elements QA (Code Review) 04 Nov '22

04 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69186 ) Change subject: Revert "cpu/x86/mp_init.c: Set a bogus initial lapic_id" ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/133433 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/133432 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/133431 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/133430 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/133429 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/133428 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/133427 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/133426 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/133425 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/133424 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/133423 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/133422 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/133421 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/133420 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/133419 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/133418 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1cae88f7345f9ff79e8f6e574521095b57c8cb7 Gerrit-Change-Number: 69186 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 01:18:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: kconfig2html: Denote that the script is python3
by Patrick Georgi (Code Review) 04 Nov '22

04 Nov '22

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69190 ) Change subject: kconfig2html: Denote that the script is python3 ...................................................................... kconfig2html: Denote that the script is python3 `python` as a command isn't universally available anymore after the python2/python3 drama. Change-Id: I9d68873d86dc3f044238d921c10fc434a83a76f5 Signed-off-by: Patrick Georgi <patrick(a)coreboot.org> --- M util/docker/coreboot.org-status/kconfig2html 1 file changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/69190/1 diff --git a/util/docker/coreboot.org-status/kconfig2html b/util/docker/coreboot.org-status/kconfig2html index 3c1efc1..38de114 100755 --- a/util/docker/coreboot.org-status/kconfig2html +++ b/util/docker/coreboot.org-status/kconfig2html @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 # # kconfig2wiki - Kconfig to MediaWiki converter for # https://www.coreboot.org/coreboot_Options -- To view, visit https://review.coreboot.org/c/coreboot/+/69190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d68873d86dc3f044238d921c10fc434a83a76f5 Gerrit-Change-Number: 69190 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: board-status: Remove shell version, update docs
by Patrick Georgi (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Martin L Roth. Hello build bot (Jenkins), Martin L Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68960 to look at the new patch set (#3). Change subject: board-status: Remove shell version, update docs ...................................................................... board-status: Remove shell version, update docs Change-Id: I532db49799eadf3214a70297c5fc84aa006bc3f7 Signed-off-by: Patrick Georgi <patrick(a)coreboot.org> --- M util/docker/coreboot.org-status/Dockerfile M util/docker/coreboot.org-status/board-status.html/README D util/docker/coreboot.org-status/board-status.html/bucketize.sh D util/docker/coreboot.org-status/board-status.html/foreword.html D util/docker/coreboot.org-status/board-status.html/status-to-html.sh D util/docker/coreboot.org-status/board-status.html/tohtml.sh M util/docker/coreboot.org-status/run.sh 7 files changed, 50 insertions(+), 718 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/68960/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I532db49799eadf3214a70297c5fc84aa006bc3f7 Gerrit-Change-Number: 68960 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Add MTL reference mainboard for MTLRVP-P
by Usha P (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Tarun Tuli, Wonkyu Kim, Subrata Banik, Ravishankar Sarawadi, Kapil Porwal, Tim Wawrzynczak, Angel Pons, Raj Astekar. Usha P has uploaded a new patch set (#10) to the change originally created by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/66097 ) Change subject: mb/intel/mtlrvp: Add MTL reference mainboard for MTLRVP-P ...................................................................... mb/intel/mtlrvp: Add MTL reference mainboard for MTLRVP-P This adds an initial mainboard code for mtlrvp, Intel Meteorlake reference platform. BUG=b:224325352 TEST=util/abuild/abuild -p none -t intel/mtlrvp -a -c max Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I097db4de9734ff81283cf470aabf3eb23b63aab8 --- A src/mainboard/intel/mtlrvp/Kconfig A src/mainboard/intel/mtlrvp/Kconfig.name A src/mainboard/intel/mtlrvp/devicetree.cb A src/mainboard/intel/mtlrvp/dsdt.asl 4 files changed, 73 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/66097/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/66097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I097db4de9734ff81283cf470aabf3eb23b63aab8 Gerrit-Change-Number: 66097 Gerrit-PatchSet: 10 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: util/cbmem: Update formatting for cbmem -l command
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68644 ) Change subject: util/cbmem: Update formatting for cbmem -l command ...................................................................... util/cbmem: Update formatting for cbmem -l command Some of the cbmem area names have gotten longer, and were making the output of cbmem -l look bad, so expand the name area to 20 characters. Instead of printing a blank area if the name isn't recognized, call it unknown. Change the method of printing the title to match the way the actual text of the table is printed. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I9d91d21c6ad418d9fee9880550fb6cb9e41e93f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68644 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M util/cbmem/cbmem.c 1 file changed, 28 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index c537a7a..b1c2f89 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -1185,11 +1185,10 @@ printf("%2d. ", n); if (name == NULL) - printf("\t\t%08x", id); - else - printf("%s\t%08x", name, id); + name = "(unknown)"; + printf("%-20s %08x", name, id); printf(" %08" PRIx64 " ", base); - printf(" %08" PRIx64 "\n", size); + printf(" %08" PRIx64 "\n", size); } static void dump_cbmem_toc(void) @@ -1204,7 +1203,8 @@ return; printf("CBMEM table of contents:\n"); - printf(" NAME ID START LENGTH\n"); + printf(" %-20s %-8s %-8s %-8s\n", "NAME", "ID", "START", + "LENGTH"); i = 0; offset = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/68644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d91d21c6ad418d9fee9880550fb6cb9e41e93f0 Gerrit-Change-Number: 68644 Gerrit-PatchSet: 4 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/**/fast_spi.c: Drop spurious whitespace
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69167 ) Change subject: soc/intel/**/fast_spi.c: Drop spurious whitespace ...................................................................... soc/intel/**/fast_spi.c: Drop spurious whitespace Drop 1 (one) newline and 1 (one) space. Change-Id: I1972d173f99507dd167bd86c73d99434b04701ab Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69167 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/intel/common/block/fast_spi/fast_spi.c 1 file changed, 19 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved Michael Niewöhner: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 78225ec..471c85d 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -210,7 +210,7 @@ /* Write Soft Reset Data register at SPIBAR0 offset 0xF8[0:15] */ write32(spibar + SPIBAR_RESET_DATA, soft_reset_data); - /* Set Strap Mux Select set to '1' */ + /* Set Strap Mux Select set to '1' */ ssms = read32(spibar + SPIBAR_RESET_CTRL); ssms |= SPIBAR_RESET_CTRL_SSMC; write32(spibar + SPIBAR_RESET_CTRL, ssms); @@ -522,7 +522,6 @@ acpigen_pop_len(); /* Scope */ } - static void fast_spi_read_resources(struct device *dev) { /* Read standard PCI resources. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1972d173f99507dd167bd86c73d99434b04701ab Gerrit-Change-Number: 69167 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: commonlib: Fix AMD MP2 BUFFER id
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69165 ) Change subject: commonlib: Fix AMD MP2 BUFFER id ...................................................................... commonlib: Fix AMD MP2 BUFFER id Cut and paste error. Signed-off-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Change-Id: Iae6213ac99bc5c64fd5dcd681c7922eafa011fc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69165 Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h 1 file changed, 18 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Felix Held: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h index b3d0040..1e63c66 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h @@ -161,5 +161,5 @@ { CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"},\ { CBMEM_ID_MEM_CHIP_INFO, "MEM CHIP INFO"},\ { CBMEM_ID_AMD_STB, "AMD STB"},\ - { CBMEM_ID_AMD_STB, "AMD MP2 BUFFER"} + { CBMEM_ID_AMD_MP2, "AMD MP2 BUFFER"} #endif /* _CBMEM_ID_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae6213ac99bc5c64fd5dcd681c7922eafa011fc0 Gerrit-Change-Number: 69165 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2022