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Change subject: common/acpi/dptc: Implement DTTS Proposal
......................................................................
Patch Set 25:
(2 comments)
File src/soc/amd/common/acpi/dptc.asl:
https://review.coreboot.org/c/coreboot/+/68471/comment/957f9cd8_e742a349
PS21, Line 47: 123
> > As I know it is 123K = 50C […]
There is an offset of temperature value stored in mapped memory.
This allows reporting a temperature range of 200K to 454K = -73C to 181C.
[static void update_mapped_memory(void)](https://source.chromium.org/chromiumos/chromium…
[#define EC_TEMP_SENSOR_OFFSET 200](https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:sr…
So if the temperature is 50C, there will store 123(0x7b) in mapped memory.
50C=323K, 323-200(offset)=123(0x7b), example
https://review.coreboot.org/c/coreboot/+/68471/comment/3c212a1e_2c50b98c
PS21, Line 56: 118
> Also incorrect. […]
Because there is an offset(200) of temperature value stored in mapped memory.
45C will store 118(0x76) in mapped memory.
45C=318K, 318-200(offset)=118(0x76)
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Change subject: vboot: Add VBOOT_CBFS_INTEGRATION support
......................................................................
Patch Set 20:
(1 comment)
File src/security/vboot/vboot_common.c:
https://review.coreboot.org/c/coreboot/+/66909/comment/9210536b_fbc6ce7b
PS20, Line 84: if (ctx == NULL) {
: printk(BIOS_ERR, "Failed to get vboot context\n");
: goto fail;
: }
This is actually impossible to happen by the logic of `vboot_get_context`. `vboot_recovery_mode_enabled` also doesn't check the return value.
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Change subject: mb/google/guybrush: rename baseboard GPIO table getter for clarity
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Patch Set 1: Code-Review+2
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Change subject: mb/google/guybrush: Rename pcie_gpio_table to romstage_gpio_table
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Patch Set 1: Code-Review+2
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Change subject: vboot: Add VBOOT_CBFS_INTEGRATION support
......................................................................
Patch Set 20: Code-Review+1
(1 comment)
File src/security/vboot/vboot_common.c:
https://review.coreboot.org/c/coreboot/+/66909/comment/71346709_0c45b4cc
PS20, Line 73: void vboot_save_and_reboot(struct vb2_context *ctx, uint8_t subcode)
Can we split vboot_save_and_reboot and vboot_fail_and_reboot to another CL? Look more clear for the content.
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Change subject: soc/intel/common/block/pcie/rtd3: Skip Power On if _STA returns 1
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Patch Set 2: Code-Review+1
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Change subject: soc/intel/block/power_limit: Avoid MSR read if it is not needed
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Change subject: drivers/ipmi/ocp: add PCIe SEL support
......................................................................
Patch Set 8:
(1 comment)
File src/drivers/ipmi/ocp/ipmi_sel.c:
https://review.coreboot.org/c/coreboot/+/68758/comment/421a8b82_f2df2ec7
PS7, Line 11: if (CONFIG(IPMI_KCS))
> Why? […]
Done
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Shuming Chu (Shuming) has uploaded a new patch set (#8) to the change originally created by Jonathan Zhang. ( https://review.coreboot.org/c/coreboot/+/68758 )
Change subject: drivers/ipmi/ocp: add PCIe SEL support
......................................................................
drivers/ipmi/ocp: add PCIe SEL support
Add Kconfig SOC_RAS_BMS_SEL and corresponding support for
generating PCIe error SEL records and sending them to BMC.
Add PCIe error definitions.
This is needed for SMM, so build the ipmi kcs driver in SMM.
Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com>
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Change-Id: I1ee46c8da7dbccbe1e2cc00bfe62e5df2f072d65
---
M src/drivers/ipmi/Makefile.inc
M src/drivers/ipmi/ocp/Kconfig
M src/drivers/ipmi/ocp/Makefile.inc
M src/drivers/ipmi/ocp/ipmi_ocp.h
A src/drivers/ipmi/ocp/ipmi_sel.c
5 files changed, 248 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/68758/8
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