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Change subject: device/xhci: Factor out common PORTSC code
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Patch Set 7: Code-Review+2
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Change subject: soc/intel/block/power_limit: Avoid MSR read if it is not needed
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Patch Set 2: Code-Review+2
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Change subject: mb/google/skyrim/var/winterhold: Update DPTC setting for EVT-SMT
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Patch Set 4:
(1 comment)
Patchset:
PS4:
Hi all,
Please help to remind me if I still need to fix or update something.
If the commit is ok, please any one help code review +2?
BR,
Eric KY Cheng
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Change subject: mb/google/nissa/var/craask: Add wifi sar table
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Patch Set 6:
(1 comment)
File src/mainboard/google/brya/variants/craask/variants.c:
https://review.coreboot.org/c/coreboot/+/68660/comment/026829d9_3216b7e9
PS6, Line 8: enum {
> We don't really want to use SKU IDs in coreboot. […]
We have FW config for it. https://chrome-internal-review.googlesource.com/c/chromeos/project/nissa/cr…
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Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69204 )
Change subject: commonlib: Reserve postcodes 0x48-0x4f for mainboard use
......................................................................
commonlib: Reserve postcodes 0x48-0x4f for mainboard use
Currently the values 0x48-0x4f were not assigned, so reserve these
values for mainboard use. Currently mainboards use a variety of
codes, so they will need to be moved.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I0a553addc830bc7914cdf977bb996fe49276d97c
---
M src/commonlib/include/commonlib/console/post_codes.h
1 file changed, 30 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/69204/1
diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h
index 7513595..4feed42 100644
--- a/src/commonlib/include/commonlib/console/post_codes.h
+++ b/src/commonlib/include/commonlib/console/post_codes.h
@@ -111,6 +111,22 @@
#define POST_CONSOLE_BOOT_MSG 0x40
/**
+ * @brief Mainboard reserved postcodes
+ *
+ * The postcodes 0x48 to 0x4f are reserved for mainboard specific functions.
+ * While there is no restriction on how these are used, it is recommended
+ * that the general flow be from lower values to higher values.
+ */
+#define POST_MB_SPECIFIC_0 0x48
+#define POST_MB_SPECIFIC_1 0x49
+#define POST_MB_SPECIFIC_2 0x4a
+#define POST_MB_SPECIFIC_3 0x4b
+#define POST_MB_SPECIFIC_4 0x4c
+#define POST_MB_SPECIFIC_5 0x4d
+#define POST_MB_SPECIFIC_6 0x4e
+#define POST_MB_SPECIFIC_7 0x4f
+
+/**
* @brief SoC/CPU/Chipset reserved postcodes
*
* The postcodes 0x50 to 0x5f are reserved for SoC specific functions.
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