coreboot-gerrit November 2022

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[S] Change in coreboot[master]: soc/amd: Specify memory types supported by each chip
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68994 ) Change subject: soc/amd: Specify memory types supported by each chip ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c7f47b43d8d4a89630fbd645a725e61d74bc2a5 Gerrit-Change-Number: 68994 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 00:59:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/pineview: Specify supported memory types
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69020 ) Change subject: nb/intel/pineview: Specify supported memory types ...................................................................... nb/intel/pineview: Specify supported memory types Change-Id: If40010abdf180e40c2aab7a991c7382dc5b2d7d5 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69020 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/pineview/Kconfig 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 92185f5..7ece198 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -13,6 +13,11 @@ select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_GMA_ACPI + select NO_DDR5 + select NO_LPDDR4 + select NO_DDR4 + select USE_DDR3 + select USE_DDR2 config VGA_BIOS_ID string -- To view, visit https://review.coreboot.org/c/coreboot/+/69020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If40010abdf180e40c2aab7a991c7382dc5b2d7d5 Gerrit-Change-Number: 69020 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: nb/intel/x4x: Specify supported memory types
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68998 ) Change subject: nb/intel/x4x: Specify supported memory types ...................................................................... nb/intel/x4x: Specify supported memory types Change-Id: I07c24ece29616fa008da0935c3fe71e35f16ed2d Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68998 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/x4x/Kconfig 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 5318623..a548df2 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -13,6 +13,11 @@ select CACHE_MRC_SETTINGS select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select HAVE_EXP_X86_64_SUPPORT + select NO_DDR5 + select NO_LPDDR4 + select NO_DDR4 + select USE_DDR3 + select USE_DDR2 config CBFS_SIZE default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX -- To view, visit https://review.coreboot.org/c/coreboot/+/68998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c24ece29616fa008da0935c3fe71e35f16ed2d Gerrit-Change-Number: 68998 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: nb/intel/sandybridge: Specify supported memory types
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69019 ) Change subject: nb/intel/sandybridge: Specify supported memory types ...................................................................... nb/intel/sandybridge: Specify supported memory types Change-Id: Ie43e818d03f411733e1bba5b7a4721c9a54ff4a4 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69019 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/Kconfig 1 file changed, 21 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 3abbddf..551714a 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -9,6 +9,14 @@ if NORTHBRIDGE_INTEL_SANDYBRIDGE +config NORTHBRIDGE_SPECIFIC_OPTIONS + def_bool y + select NO_DDR5 + select NO_LPDDR4 + select NO_DDR4 + select NO_DDR2 + select USE_DDR3 + config SANDYBRIDGE_VBOOT_IN_ROMSTAGE bool default n -- To view, visit https://review.coreboot.org/c/coreboot/+/69019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie43e818d03f411733e1bba5b7a4721c9a54ff4a4 Gerrit-Change-Number: 69019 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: nb/intel/gm45: Specify supported memory types
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68997 ) Change subject: nb/intel/gm45: Specify supported memory types ...................................................................... nb/intel/gm45: Specify supported memory types Change-Id: I3a3a45a1a36ea6ad0b8fb2d3ee78add0b38460ac Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68997 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/gm45/Kconfig 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index c186f01..0b0ff5162 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -13,6 +13,11 @@ select INTEL_GMA_ACPI select INTEL_GMA_SSC_ALTERNATE_REF select HAVE_EXP_X86_64_SUPPORT + select NO_DDR5 + select NO_LPDDR4 + select NO_DDR4 + select USE_DDR3 + select USE_DDR2 config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK -- To view, visit https://review.coreboot.org/c/coreboot/+/68997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a3a45a1a36ea6ad0b8fb2d3ee78add0b38460ac Gerrit-Change-Number: 68997 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: nb/intel/i945: Specify supported memory type
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68996 ) Change subject: nb/intel/i945: Specify supported memory type ...................................................................... nb/intel/i945: Specify supported memory type Change-Id: I3cc2a9786dfb1f8fb1ec8e78bde7c46c07f8da48 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68996 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/i945/Kconfig 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 7a05d20..d1e7dbe 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -13,6 +13,11 @@ select INTEL_GMA_SSC_ALTERNATE_REF select INTEL_EDID select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT + select NO_DDR5 + select NO_LPDDR4 + select NO_DDR4 + select NO_DDR3 + select USE_DDR2 config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK -- To view, visit https://review.coreboot.org/c/coreboot/+/68996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cc2a9786dfb1f8fb1ec8e78bde7c46c07f8da48 Gerrit-Change-Number: 68996 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: device/dram: Add kconfig options for memory types
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68992 ) Change subject: device/dram: Add kconfig options for memory types ...................................................................... device/dram: Add kconfig options for memory types Currently, we're building support for all memory types into every board, and letting the linker remove anything that isn't needed. This is okay, but it'd be nice to be able to build in just what's actually needed. This change adds options to specify both what is used and what is not. By doing it that way, the default values don't change, but platforms can start removing support for memory types that are not needed. When all platforms (SoCs, CPUs and/or Northbridge chips) specify what memory types they support, the defaults on the options to use a particular memory type can be set to no, and the options not to use a memory type can be removed. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I07c98a702e0d67c5ad7bd9b8a4ff24c9288ab569 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68992 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/device/Kconfig A src/device/dram/Kconfig M src/device/dram/Makefile.inc 3 files changed, 103 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved Angel Pons: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/device/Kconfig b/src/device/Kconfig index c0ba3d1..60ee047 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -953,4 +953,6 @@ help Provides xHCI utility functions. +source "src/device/dram/Kconfig" + endmenu diff --git a/src/device/dram/Kconfig b/src/device/dram/Kconfig new file mode 100644 index 0000000..7bb1dab --- /dev/null +++ b/src/device/dram/Kconfig @@ -0,0 +1,57 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# Short-term plan: Start adding 'USE_' and "NO_" options to each chip. +# +# Long-term plan: Every SoC or chipset should select the memory types they +# use. When they all select their memory, the 'no_' options can be removed +# and the defaults for all memory types can be set to n. + +config NO_DDR5 + bool + +config NO_LPDDR4 + bool + +config NO_DDR4 + bool + +config NO_DDR3 + bool + +config NO_DDR2 + bool + +config USE_DDR5 + bool + default n if NO_DDR5 + default y + help + system supports DDR5 memory + +config USE_LPDDR4 + bool + default n if NO_LPDDR4 + default y + help + system supports LPDDR4 memory + +config USE_DDR4 + bool + default n if NO_DDR4 + default y + help + system supports DDR4 memory + +config USE_DDR3 + bool + default n if NO_DDR3 + default y + help + system supports DDR3 memory + +config USE_DDR2 + bool + default n if NO_DDR2 + default y + help + system supports DDR2 memory diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc index 31dfb91..fc472ea 100644 --- a/src/device/dram/Makefile.inc +++ b/src/device/dram/Makefile.inc @@ -1,3 +1,18 @@ -romstage-y += ddr5.c lpddr4.c ddr4.c ddr3.c ddr2.c ddr_common.c -ramstage-y += ddr5.c lpddr4.c ddr4.c ddr3.c ddr2.c ddr_common.c spd.c +romstage-y += ddr_common.c +ramstage-y += ddr_common.c spd.c + +romstage-$(CONFIG_USE_DDR5) += ddr5.c +ramstage-$(CONFIG_USE_DDR5) += ddr5.c + +romstage-$(CONFIG_USE_LPDDR4) += lpddr4.c +ramstage-$(CONFIG_USE_LPDDR4) += lpddr4.c + +romstage-$(CONFIG_USE_DDR4) += ddr4.c +ramstage-$(CONFIG_USE_DDR4) += ddr4.c + +romstage-$(CONFIG_USE_DDR3) += ddr3.c +ramstage-$(CONFIG_USE_DDR3) += ddr3.c + +romstage-$(CONFIG_USE_DDR2) += ddr2.c +ramstage-$(CONFIG_USE_DDR2) += ddr2.c -- To view, visit https://review.coreboot.org/c/coreboot/+/68992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c98a702e0d67c5ad7bd9b8a4ff24c9288ab569 Gerrit-Change-Number: 68992 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Skip Power On if _STA returns 1
by Kane Chen (Code Review) 04 Nov '22

04 Nov '22

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69189 ) Change subject: soc/intel/common/block/pcie/rtd3: Skip Power On if _STA returns 1 ...................................................................... soc/intel/common/block/pcie/rtd3: Skip Power On if _STA returns 1 RTD3,_ON method sometimes can create delays during system boot. Even when the power is already up, kernel still tries to call _ON method to power up device, but it's unnecessary. RTD3._STA returns device power, so _ON method can check _STA and see if the power on process can be skipped BUG=b:249931687 TEST=system can boot to OS with RTD3 pcie storage and save ~80 on Crota. Suspend stress test passes 100 cycles Change-Id: I296ce1b85417a5dbaca558511cd7fc51a3a38c84 Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> --- M src/soc/intel/common/block/pcie/rtd3/rtd3.c 1 file changed, 43 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/69189/1 diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index f99ae44..7a64734 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -143,10 +143,30 @@ static void pcie_rtd3_acpi_method_on(unsigned int pcie_rp, const struct soc_intel_common_block_pcie_rtd3_config *config, - enum pcie_rp_type rp_type) + enum pcie_rp_type rp_type, + const struct device *dev) { + const struct device *parent = dev->bus->dev; + acpigen_write_method_serialized("_ON", 0); + /* The _STA returns current power status of device, so we can skip _ON + * if _STA returns 1 + * Example: + * Local0 = \_SB.PCI0.RP01.RTD3._STA () + * If ((Local0 == One)) + * { + * Return (One) + * } + */ + acpigen_write_store(); + acpigen_emit_namestring(acpi_device_path_join(parent, "RTD3._STA")); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_if_lequal_op_int(LOCAL0_OP, ONE_OP); + acpigen_write_return_op(ONE_OP); + acpigen_write_if_end(); + + /* When this feature is enabled, ONSK indicates if the previous _OFF was * skipped. If so, since the device was not in Off state, and the current * _ON can be skipped as well. @@ -448,7 +468,7 @@ } pcie_rtd3_acpi_method_status(config); - pcie_rtd3_acpi_method_on(pcie_rp, config, rp_type); + pcie_rtd3_acpi_method_on(pcie_rp, config, rp_type, dev); pcie_rtd3_acpi_method_off(pcie_rp, config, rp_type); acpigen_pop_len(); /* PowerResource */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I296ce1b85417a5dbaca558511cd7fc51a3a38c84 Gerrit-Change-Number: 69189 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: vboot: Add VBOOT_CBFS_INTEGRATION support
by Julius Werner (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Hung-Te Lin, Jason Glenesk, Raul Rangel, Jakub Czapiga, Matt DeVillier, Fred Reitberger, Felix Held. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66909 ) Change subject: vboot: Add VBOOT_CBFS_INTEGRATION support ...................................................................... Patch Set 20: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/66909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40ae01c477c4e4f7a1c90e4026a8a868ae64b5ca Gerrit-Change-Number: 66909 Gerrit-PatchSet: 20 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Nov 2022 00:51:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/guybrush: Rename pcie_gpio_table to romstage_gpio_table
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Jason Nien, Matt DeVillier, Martin Roth. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69177 ) Change subject: mb/google/guybrush: Rename pcie_gpio_table to romstage_gpio_table ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72e7febfb532262be7e4c14bf136e0d69c91301e Gerrit-Change-Number: 69177 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 00:47:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2022