coreboot-gerrit November 2022

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[S] Change in coreboot[master]: mb/google/guybrush: rename baseboard GPIO table getter for clarity
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Jason Nien, Matt DeVillier, Martin Roth. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69176 ) Change subject: mb/google/guybrush: rename baseboard GPIO table getter for clarity ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14c79fad04f18d874ce6ff7e572bb237445db8b1 Gerrit-Change-Number: 69176 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 00:46:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/picasso/acpi: include pci_int_defs.asl from soc.asl
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Jason Glenesk, Jason Nien, Matt DeVillier, Martin Roth, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69188 ) Change subject: soc/amd/picasso/acpi: include pci_int_defs.asl from soc.asl ...................................................................... soc/amd/picasso/acpi: include pci_int_defs.asl from soc.asl Instead of including pci_int_defs.asl in each board's DSDT, include it in the common soc.asl. This moves the PRQM OperationRegion and the PRQI IndexField defined in pci_int_defs.asl into the \_SB scope, but those are defined inside the \_SB scope both in the Picasso reference code and for the AMD SoCs from Cezanne on. TEST=Both Linux and Windows still boot and don't show ACPI errors on Mandolin after moving this inside the \_SB scope Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib4e7bfb15de184cc43cd17c8249be0f59405793f --- M src/mainboard/amd/bilby/dsdt.asl M src/mainboard/amd/mandolin/dsdt.asl M src/mainboard/google/zork/dsdt.asl M src/soc/amd/picasso/acpi/soc.asl 4 files changed, 22 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/69188/1 diff --git a/src/mainboard/amd/bilby/dsdt.asl b/src/mainboard/amd/bilby/dsdt.asl index 140f395..dd42608 100644 --- a/src/mainboard/amd/bilby/dsdt.asl +++ b/src/mainboard/amd/bilby/dsdt.asl @@ -16,9 +16,6 @@ #include <acpi/dsdt_top.asl> #include <globalnvs.asl> - /* PCI IRQ mapping for the Southbridge */ - #include <pci_int_defs.asl> - /* Power state notification to ALIB */ #include <pnot.asl> diff --git a/src/mainboard/amd/mandolin/dsdt.asl b/src/mainboard/amd/mandolin/dsdt.asl index 140f395..dd42608 100644 --- a/src/mainboard/amd/mandolin/dsdt.asl +++ b/src/mainboard/amd/mandolin/dsdt.asl @@ -16,9 +16,6 @@ #include <acpi/dsdt_top.asl> #include <globalnvs.asl> - /* PCI IRQ mapping for the Southbridge */ - #include <pci_int_defs.asl> - /* Power state notification to ALIB */ #include <pnot.asl> diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl index 732ebea..62520b9 100644 --- a/src/mainboard/google/zork/dsdt.asl +++ b/src/mainboard/google/zork/dsdt.asl @@ -17,9 +17,6 @@ #include <acpi/dsdt_top.asl> #include <globalnvs.asl> - /* PCI IRQ mapping for the Southbridge */ - #include <pci_int_defs.asl> - /* Power state notification to ALIB */ #include <pnot.asl> diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl index c4425eb..f44f873 100644 --- a/src/soc/amd/picasso/acpi/soc.asl +++ b/src/soc/amd/picasso/acpi/soc.asl @@ -8,6 +8,9 @@ #include "sb_pci0_fch.asl" } +/* PCI IRQ mapping for the Southbridge */ +#include "pci_int_defs.asl" + /* Describe PCI INT[A-H] for the Southbridge */ #include <soc/amd/common/acpi/pci_int.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/69188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4e7bfb15de184cc43cd17c8249be0f59405793f Gerrit-Change-Number: 69188 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd/picasso/acpi: rename pcie.asl to pci_int_defs.asl
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69187 ) Change subject: soc/amd/picasso/acpi: rename pcie.asl to pci_int_defs.asl ...................................................................... soc/amd/picasso/acpi: rename pcie.asl to pci_int_defs.asl This aligns Picasso more with the newer AMD SoCs and also makes it a bit clearer what this file does. Also remove the unneeded tabs at the beginning of each line. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie6e5ee815e4346004bc864a6111a255dc689eae8 --- M src/mainboard/amd/bilby/dsdt.asl M src/mainboard/amd/mandolin/dsdt.asl M src/mainboard/google/zork/dsdt.asl A src/soc/amd/picasso/acpi/pci_int_defs.asl D src/soc/amd/picasso/acpi/pcie.asl 5 files changed, 82 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/69187/1 diff --git a/src/mainboard/amd/bilby/dsdt.asl b/src/mainboard/amd/bilby/dsdt.asl index e0059c9..140f395 100644 --- a/src/mainboard/amd/bilby/dsdt.asl +++ b/src/mainboard/amd/bilby/dsdt.asl @@ -17,7 +17,7 @@ #include <globalnvs.asl> /* PCI IRQ mapping for the Southbridge */ - #include <pcie.asl> + #include <pci_int_defs.asl> /* Power state notification to ALIB */ #include <pnot.asl> diff --git a/src/mainboard/amd/mandolin/dsdt.asl b/src/mainboard/amd/mandolin/dsdt.asl index e0059c9..140f395 100644 --- a/src/mainboard/amd/mandolin/dsdt.asl +++ b/src/mainboard/amd/mandolin/dsdt.asl @@ -17,7 +17,7 @@ #include <globalnvs.asl> /* PCI IRQ mapping for the Southbridge */ - #include <pcie.asl> + #include <pci_int_defs.asl> /* Power state notification to ALIB */ #include <pnot.asl> diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl index 3a92fe1..732ebea 100644 --- a/src/mainboard/google/zork/dsdt.asl +++ b/src/mainboard/google/zork/dsdt.asl @@ -18,7 +18,7 @@ #include <globalnvs.asl> /* PCI IRQ mapping for the Southbridge */ - #include <pcie.asl> + #include <pci_int_defs.asl> /* Power state notification to ALIB */ #include <pnot.asl> diff --git a/src/soc/amd/picasso/acpi/pci_int_defs.asl b/src/soc/amd/picasso/acpi/pci_int_defs.asl new file mode 100644 index 0000000..0e1a5b6 --- /dev/null +++ b/src/soc/amd/picasso/acpi/pci_int_defs.asl @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* PCI IRQ mapping registers, C00h-C01h. */ +OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ +} +IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0: INTA */ + PIRB, 0x00000008, /* Index 1: INTB */ + PIRC, 0x00000008, /* Index 2: INTC */ + PIRD, 0x00000008, /* Index 3: INTD */ + PIRE, 0x00000008, /* Index 4: INTE */ + PIRF, 0x00000008, /* Index 5: INTF */ + PIRG, 0x00000008, /* Index 6: INTG */ + PIRH, 0x00000008, /* Index 7: INTH */ + + Offset (0x43), + PMMC, 0x00000008, /* Index 0x43: eMMC */ + + Offset (0x62), + PGPI, 0x00000008, /* Index 0x62: GPIO */ + + Offset (0x70), + PI20, 0x00000008, /* Index 0x70: I2C0 */ + PI21, 0x00000008, /* Index 0x71: I2C1 */ + PI22, 0x00000008, /* Index 0x72: I2C2 */ + PI23, 0x00000008, /* Index 0x73: I2C3 */ + PUA0, 0x00000008, /* Index 0x74: UART0 */ + PUA1, 0x00000008, /* Index 0x75: UART1 */ + PI24, 0x00000008, /* Index 0x76: I2C4 */ + PI25, 0x00000008, /* Index 0x77: I2C5 */ + PUA2, 0x00000008, /* Index 0x78: UART2 */ + PUA3, 0x00000008, /* Index 0x79: UART3 */ + + /* IO-APIC IRQs */ + Offset (0x80), + IORA, 0x00000008, /* Index 0x80: INTA */ + IORB, 0x00000008, /* Index 0x81: INTB */ + IORC, 0x00000008, /* Index 0x82: INTC */ + IORD, 0x00000008, /* Index 0x83: INTD */ + IORE, 0x00000008, /* Index 0x84: INTE */ + IORF, 0x00000008, /* Index 0x85: INTF */ + IORG, 0x00000008, /* Index 0x86: INTG */ + IORH, 0x00000008, /* Index 0x87: INTH */ + + Offset (0xC3), + IMMC, 0x00000008, /* Index 0xC3: eMMC */ + + Offset (0xE2), + IGPI, 0x00000008, /* Index 0xE2: GPIO */ + + Offset (0xF0), + II20, 0x00000008, /* Index 0xF0: I2C0 */ + II21, 0x00000008, /* Index 0xF1: I2C1 */ + II22, 0x00000008, /* Index 0xF2: I2C2 */ + II23, 0x00000008, /* Index 0xF3: I2C3 */ + IUA0, 0x00000008, /* Index 0xF4: UART0 */ + IUA1, 0x00000008, /* Index 0xF5: UART1 */ + II24, 0x00000008, /* Index 0xF6: I2C4 */ + II25, 0x00000008, /* Index 0xF7: I2C5 */ + IUA2, 0x00000008, /* Index 0xF8: UART2 */ + IUA3, 0x00000008, /* Index 0xF9: UART3 */ +} diff --git a/src/soc/amd/picasso/acpi/pcie.asl b/src/soc/amd/picasso/acpi/pcie.asl deleted file mode 100644 index 601de52..0000000 --- a/src/soc/amd/picasso/acpi/pcie.asl +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - /* PCI IRQ mapping registers, C00h-C01h. */ - OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PIRA, 0x00000008, /* Index 0: INTA */ - PIRB, 0x00000008, /* Index 1: INTB */ - PIRC, 0x00000008, /* Index 2: INTC */ - PIRD, 0x00000008, /* Index 3: INTD */ - PIRE, 0x00000008, /* Index 4: INTE */ - PIRF, 0x00000008, /* Index 5: INTF */ - PIRG, 0x00000008, /* Index 6: INTG */ - PIRH, 0x00000008, /* Index 7: INTH */ - - Offset (0x43), - PMMC, 0x00000008, /* Index 0x43: eMMC */ - - Offset (0x62), - PGPI, 0x00000008, /* Index 0x62: GPIO */ - - Offset (0x70), - PI20, 0x00000008, /* Index 0x70: I2C0 */ - PI21, 0x00000008, /* Index 0x71: I2C1 */ - PI22, 0x00000008, /* Index 0x72: I2C2 */ - PI23, 0x00000008, /* Index 0x73: I2C3 */ - PUA0, 0x00000008, /* Index 0x74: UART0 */ - PUA1, 0x00000008, /* Index 0x75: UART1 */ - PI24, 0x00000008, /* Index 0x76: I2C4 */ - PI25, 0x00000008, /* Index 0x77: I2C5 */ - PUA2, 0x00000008, /* Index 0x78: UART2 */ - PUA3, 0x00000008, /* Index 0x79: UART3 */ - - /* IO-APIC IRQs */ - Offset (0x80), - IORA, 0x00000008, /* Index 0x80: INTA */ - IORB, 0x00000008, /* Index 0x81: INTB */ - IORC, 0x00000008, /* Index 0x82: INTC */ - IORD, 0x00000008, /* Index 0x83: INTD */ - IORE, 0x00000008, /* Index 0x84: INTE */ - IORF, 0x00000008, /* Index 0x85: INTF */ - IORG, 0x00000008, /* Index 0x86: INTG */ - IORH, 0x00000008, /* Index 0x87: INTH */ - - Offset (0xC3), - IMMC, 0x00000008, /* Index 0xC3: eMMC */ - - Offset (0xE2), - IGPI, 0x00000008, /* Index 0xE2: GPIO */ - - Offset (0xF0), - II20, 0x00000008, /* Index 0xF0: I2C0 */ - II21, 0x00000008, /* Index 0xF1: I2C1 */ - II22, 0x00000008, /* Index 0xF2: I2C2 */ - II23, 0x00000008, /* Index 0xF3: I2C3 */ - IUA0, 0x00000008, /* Index 0xF4: UART0 */ - IUA1, 0x00000008, /* Index 0xF5: UART1 */ - II24, 0x00000008, /* Index 0xF6: I2C4 */ - II25, 0x00000008, /* Index 0xF7: I2C5 */ - IUA2, 0x00000008, /* Index 0xF8: UART2 */ - IUA3, 0x00000008, /* Index 0xF9: UART3 */ - } -- To view, visit https://review.coreboot.org/c/coreboot/+/69187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6e5ee815e4346004bc864a6111a255dc689eae8 Gerrit-Change-Number: 69187 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: cpu/x86/mp_init.c: Handle failed init_bsp()
by 9elements QA (Code Review) 04 Nov '22

04 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69109 ) Change subject: cpu/x86/mp_init.c: Handle failed init_bsp() ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 13 / 3 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/133415 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/133414 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/133413 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/133412 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/133411 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/133410 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/133409 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/133408 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/133407 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/133406 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/133405 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/133404 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/133403 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/133402 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/133401 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/133400 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7be5d6c32458ba98f4f8c5c9340790ff989c91e7 Gerrit-Change-Number: 69109 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 00:43:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: device & commonlib: Update pci_scan_bus postcodes
by Martin L Roth (Code Review) 04 Nov '22

04 Nov '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69201 ) Change subject: device & commonlib: Update pci_scan_bus postcodes ...................................................................... device & commonlib: Update pci_scan_bus postcodes The function pci_scan_bus had 3 post codes in it: 0x24 - beginning 0x25 - middle 0x55 - end I got rid of the middle postcode and used 0x25 for the code signifying the end of the function. I don't think all three are needed. 0x24 & 0x25 postcodes are not currently used anywhere else in the code. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I19c9d5e256505b64234919a99f73a71efbbfdae3 --- M src/commonlib/include/commonlib/console/post_codes.h M src/device/pci_device.c 2 files changed, 36 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/69201/1 diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h index 8ab069b..d838815 100644 --- a/src/commonlib/include/commonlib/console/post_codes.h +++ b/src/commonlib/include/commonlib/console/post_codes.h @@ -66,6 +66,20 @@ #define POST_ENTRY_C_START 0x13 /** + * \brief Entry into pci_scan_bus + * + * Entered pci_scan_bus() + */ +#define POST_ENTER_PCI_SCAN_BUS 0x24 + +/** + * \brief Entry into pci_scan_bus + * + * Entered pci_scan_bus() + */ +#define POST_EXIT_PCI_SCAN_BUS 0x25 + +/** * \brief Pre-memory init preparation start * * Post code emitted in romstage before making callbacks to allow SoC/mainboard diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 70af9c5..7ad8e5b 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1423,7 +1423,7 @@ max_devfn=0xff; } - post_code(0x24); + post_code(POST_ENTER_PCI_SCAN_BUS); if (pci_bus_only_one_child(bus)) max_devfn = MIN(max_devfn, 0x07); @@ -1464,8 +1464,6 @@ } } - post_code(0x25); - /* * Warn if any leftover static devices are found. * There's probably a problem in devicetree.cb. @@ -1516,7 +1514,7 @@ * side of any bridges that may be on this bus plus any devices. * Return how far we've got finding sub-buses. */ - post_code(0x55); + post_code(POST_EXIT_PCI_SCAN_BUS); } typedef enum { -- To view, visit https://review.coreboot.org/c/coreboot/+/69201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19c9d5e256505b64234919a99f73a71efbbfdae3 Gerrit-Change-Number: 69201 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: checkpatch: add Co-authored-by to signature list
by Patrick Georgi (Code Review) 04 Nov '22

04 Nov '22

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69166 ) Change subject: checkpatch: add Co-authored-by to signature list ...................................................................... checkpatch: add Co-authored-by to signature list Co-authored-by is commonly used for changes that have more than one author. Add it to the list to make Jenkins happy. Change-Id: I7f66824febe3be756c64ebf44c94bc653a66f1e1 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69166 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Patrick Georgi <patrick(a)coreboot.org> --- M util/lint/checkpatch.pl 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/util/lint/checkpatch.pl b/util/lint/checkpatch.pl index 95296b9..d044d8d 100755 --- a/util/lint/checkpatch.pl +++ b/util/lint/checkpatch.pl @@ -618,6 +618,7 @@ Reviewed-by:| Reported-by:| Suggested-by:| + Co-authored-by:| To:| Cc: )}; -- To view, visit https://review.coreboot.org/c/coreboot/+/69166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f66824febe3be756c64ebf44c94bc653a66f1e1 Gerrit-Change-Number: 69166 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: cpu/x86/mp_init.c: Set a bogus initial lapic_id
by 9elements QA (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans. 9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69108 ) Change subject: cpu/x86/mp_init.c: Set a bogus initial lapic_id ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 13 / 2 / 15 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/133398 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/133397 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/133396 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/133395 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/133394 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/133393 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/133392 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/133391 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/133390 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/133389 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/133388 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/133387 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/133386 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/133384 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/133383 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I938faf042bfa4fe1fc39e78ab740c9b210bc105c Gerrit-Change-Number: 69108 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 04 Nov 2022 00:23:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: arch/x86 & commonlib: Add macros for postcodes used in x86/tables
by Martin L Roth (Code Review) 04 Nov '22

04 Nov '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69200 ) Change subject: arch/x86 & commonlib: Add macros for postcodes used in x86/tables ...................................................................... arch/x86 & commonlib: Add macros for postcodes used in x86/tables The 0x9a, 0x9b, and 0x9c postcodes are not used anywhere else in the coreboot tree other than in arch/x86/tables.c. Add macros to standardize these postcodes. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I16be65ffa3f0b253fe4a9bb7bfb97597a760ad3f --- M src/arch/x86/tables.c M src/commonlib/include/commonlib/console/post_codes.h 2 files changed, 38 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/69200/1 diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 5940c64..b4b97b4 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -17,7 +17,7 @@ unsigned long high_table_pointer; #define MAX_PIRQ_TABLE_SIZE (4 * 1024) - post_code(0x9a); + post_code(POST_X86_WRITE_PIRQ_TABLE); /* This table must be between 0x0f0000 and 0x100000 */ rom_table_end = write_pirq_routing_table(rom_table_end); @@ -49,7 +49,7 @@ unsigned long high_table_pointer; #define MAX_MP_TABLE_SIZE (4 * 1024) - post_code(0x9b); + post_code(POST_X86_WRITE_MPTABLE); /* The smp table must be in 0-1K, 639K-640K, or 960K-1M */ rom_table_end = write_smp_table(rom_table_end); @@ -78,7 +78,7 @@ unsigned long high_table_pointer; const size_t max_acpi_size = CONFIG_MAX_ACPI_TABLE_SIZE_KB * KiB; - post_code(0x9c); + post_code(POST_X86_WRITE_ACPITABLE); /* Write ACPI tables to F segment and high tables area */ diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h index 8b154ca..8ab069b 100644 --- a/src/commonlib/include/commonlib/console/post_codes.h +++ b/src/commonlib/include/commonlib/console/post_codes.h @@ -287,6 +287,27 @@ #define POST_FSP_SILICON_EXIT 0x99 /** + * \brief Entry to write_pirq_table + * + * coreboot entered write_pirq_table + */ +#define POST_X86_WRITE_PIRQ_TABLE 0x9a + +/** + * \brief Entry to write_mptable + * + * coreboot entered write_mptable + */ +#define POST_X86_WRITE_MPTABLE 0x9b + +/** + * \brief Entry to write_acpi_table + * + * coreboot entered write_acpi_table + */ +#define POST_X86_WRITE_ACPITABLE 0x9c + +/** * \brief Before calling FSP Multiphase SiliconInit * * Going to call into FSP binary for Multiple phase SI Init -- To view, visit https://review.coreboot.org/c/coreboot/+/69200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16be65ffa3f0b253fe4a9bb7bfb97597a760ad3f Gerrit-Change-Number: 69200 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/glinda/data_fabric: Add register bitslice struct
by 9elements QA (Code Review) 04 Nov '22

04 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69072 ) Change subject: soc/amd/glinda/data_fabric: Add register bitslice struct ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 2 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/133381 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/133380 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/133379 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/133378 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/133377 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/133376 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/133375 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/133374 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/133373 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/133372 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/133371 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/133370 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/133369 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/133368 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/133367 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/133366 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I509eaf5910d8d65ce0956200d7c00451ff9ce864 Gerrit-Change-Number: 69072 Gerrit-PatchSet: 3 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 00:09:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Provide mitigation support for CNVi RFI
by Eric Lai (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Tarun Tuli, John Zhao, Kapil Porwal, Tim Wawrzynczak, Sumeet R Pawnikar. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67789 ) Change subject: soc/intel/meteorlake: Provide mitigation support for CNVi RFI ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87110bc10b98a27a8f274680597b15a1df488824 Gerrit-Change-Number: 67789 Gerrit-PatchSet: 10 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 23:58:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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