coreboot-gerrit November 2022

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[S] Change in coreboot[master]: cpu/x86/mp_init.c: Use existing code to create cpu struct device
by Jonathan Zhang (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Arthur Heymans, Kyösti Mälkki. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64341 ) Change subject: cpu/x86/mp_init.c: Use existing code to create cpu struct device ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80baadd405b31d6be2fdbb894b0f4b7c775da6f8 Gerrit-Change-Number: 64341 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 22:01:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/amd/*/data_fabric: move data_fabric_set_mmio_np to common
by 9elements QA (Code Review) 03 Nov '22

03 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69067 ) Change subject: soc/amd/*/data_fabric: move data_fabric_set_mmio_np to common ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 1 / 15 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/133313 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/133312 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/133311 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/133310 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/133309 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/133308 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/133307 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/133306 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/133305 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/133304 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/133302 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/133301 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/133300 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/133299 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/133298 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e524a34a20e1c6f088feaf39d592b8d5efab58 Gerrit-Change-Number: 69067 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 21:54:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/x86/mp_init.c: Handle failed init_bsp()
by Felix Held (Code Review) 03 Nov '22

03 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69109 ) Change subject: cpu/x86/mp_init.c: Handle failed init_bsp() ...................................................................... cpu/x86/mp_init.c: Handle failed init_bsp() Bail out of mp_init if this function fails. Change-Id: I7be5d6c32458ba98f4f8c5c9340790ff989c91e7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69109 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/cpu/x86/mp_init.c 1 file changed, 26 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Elyes Haouas: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 8cd785e..fa19104 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -532,7 +532,7 @@ return ret; } -static void init_bsp(struct bus *cpu_bus) +static enum cb_err init_bsp(struct bus *cpu_bus) { struct device_path cpu_path; struct cpu_info *info; @@ -554,11 +554,14 @@ info->cpu = alloc_find_dev(cpu_bus, &cpu_path); info->cpu->name = processor_name; - if (info->index != 0) + if (info->index != 0) { printk(BIOS_CRIT, "BSP index(%zd) != 0!\n", info->index); + return CB_ERR; + } /* Track BSP in cpu_map structures. */ cpu_add_map_entry(info->index); + return CB_SUCCESS; } /* @@ -585,7 +588,10 @@ g_cpu_bus = cpu_bus; - init_bsp(cpu_bus); + if (init_bsp(cpu_bus) != CB_SUCCESS) { + printk(BIOS_CRIT, "Setting up BSP failed\n"); + return CB_ERR; + } if (p == NULL || p->flight_plan == NULL || p->num_records < 1) { printk(BIOS_CRIT, "Invalid MP parameters\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/69109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7be5d6c32458ba98f4f8c5c9340790ff989c91e7 Gerrit-Change-Number: 69109 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: cpu/x86/mp_init.c: Handle failed init_bsp()
by Felix Held (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Arthur Heymans. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69109 ) Change subject: cpu/x86/mp_init.c: Handle failed init_bsp() ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: took me a while to figure out how the data that gets checked with info->index != 0 ends up being at the place where we look for it, but at least i learned a thing or two while doing that -- To view, visit https://review.coreboot.org/c/coreboot/+/69109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7be5d6c32458ba98f4f8c5c9340790ff989c91e7 Gerrit-Change-Number: 69109 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 03 Nov 2022 21:38:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/guybrush: Use detect vs probed flag for touchscreens
by Matt DeVillier (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Jason Nien, Martin Roth. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69199 ) Change subject: mb/google/guybrush: Use detect vs probed flag for touchscreens ...................................................................... mb/google/guybrush: Use detect vs probed flag for touchscreens Now that coreboot performs the necessary power sequencing, switch from using the 'probed' flag to 'detect' for all I2C touchscreens. This alleviates ChromeOS from having to probe to see which touchscreen model is actually present, prevents breaking ACPI spec by generating device entries with status 'enabled and present' which aren't actually present, and improves compatibility with upstream Linux and Windows. BUG=b:121309055 TEST=build/boot ChromeOS and Linux on guybrush, ensure touchscreen is functional, and ACPI device entry generated for correct touchscreen model. This mirrors the changes made for skyrim in CB:67779. Change-Id: Ib6a76b969d3a245eccde5352231eb7e36736f2e0 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/mainboard/google/guybrush/variants/dewatt/overridetree.cb M src/mainboard/google/guybrush/variants/guybrush/overridetree.cb M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb 3 files changed, 29 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/69199/1 diff --git a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb index 8649f1d..0ad0931 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb @@ -157,7 +157,7 @@ register "generic.hid" = ""ELAN6918"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_89)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_121)" register "generic.reset_delay_ms" = "20" register "generic.reset_off_delay_ms" = "2" diff --git a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb index 9577d14..23379c9 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb @@ -93,7 +93,7 @@ register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_89)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_68)" register "generic.enable_delay_ms" = "10" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_121)" diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index 18b1cab..ea1f7d6 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -300,7 +300,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "probed" = "1" + register "detect" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_89)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_68)" register "enable_delay_ms" = "1" @@ -313,7 +313,7 @@ register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_89)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_68)" register "generic.enable_delay_ms" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_121)" -- To view, visit https://review.coreboot.org/c/coreboot/+/69199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6a76b969d3a245eccde5352231eb7e36736f2e0 Gerrit-Change-Number: 69199 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/guybrush: Implement touchscreen power sequencing
by Matt DeVillier (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Jason Nien, Martin Roth. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69178 ) Change subject: mb/google/guybrush: Implement touchscreen power sequencing ...................................................................... mb/google/guybrush: Implement touchscreen power sequencing As all variants have a touchscreen option, in baseboard table set the enable GPIO high and hold in reset during romstage, then release reset in ramstage. This will allow the touchscreen to make use of the runtime I2C detect feature (enabled in a subsequent commit) so that an ACPI device entry is created only for the touchscreen actually present. Variants/SKUs which do not have a touchscreen (if any) can use the romstage/ramstage GPIO override tables to set the associated enable/ reset GPIOs to NC. This mirrors the change to skyrim in CB:67778. BUG=b:121309055 TEST=build/boot guybrush with rest of patch series Change-Id: I9b3356b8b3a0e68a307838a4b18775d25b32e548 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c 1 file changed, 31 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/69178/1 diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index beb654f..595f680 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -135,7 +135,7 @@ /* TCHSCR_REPORT_EN */ PAD_GPO(GPIO_120, LOW), /* TCHSCR_RESET_L */ - PAD_GPO(GPIO_121, LOW), + PAD_GPO(GPIO_121, HIGH), /* GPIO_122 - GPIO_128: Not available */ /* SOC_DISABLE_DISP_BL */ PAD_GPO(GPIO_129, LOW), @@ -284,6 +284,11 @@ PAD_NC(GPIO_70), /* PCIE_RST0_L */ PAD_NFO(GPIO_26, PCIE_RST_L, HIGH), + /* Enable touchscreen, hold in reset */ + /* EN_PP3300_TCHSCR */ + PAD_GPO(GPIO_68, HIGH), + /* TCHSCR_RESET_L */ + PAD_GPO(GPIO_121, LOW), }; const struct soc_amd_gpio *baseboard_romstage_gpio_table(size_t *size) -- To view, visit https://review.coreboot.org/c/coreboot/+/69178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b3356b8b3a0e68a307838a4b18775d25b32e548 Gerrit-Change-Number: 69178 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/guybrush: Rename pcie_gpio_table to romstage_gpio_table
by Matt DeVillier (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Jason Nien, Martin Roth. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69177 ) Change subject: mb/google/guybrush: Rename pcie_gpio_table to romstage_gpio_table ...................................................................... mb/google/guybrush: Rename pcie_gpio_table to romstage_gpio_table Rename so table more indicative of when GPIOs are set, and so it can be used for more than just setting PCIe GPIOs. Will be used to set touchscreen GPIOs as part of power sequencing in a subsequent commit. Rename all variant tables and getter functions to match. This mirrors the changes made for skyrim in CB:67810 Change-Id: I72e7febfb532262be7e4c14bf136e0d69c91301e Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/mainboard/google/guybrush/romstage.c M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/guybrush/variants/dewatt/gpio.c M src/mainboard/google/guybrush/variants/guybrush/gpio.c M src/mainboard/google/guybrush/variants/nipperkin/gpio.c 6 files changed, 40 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/69177/1 diff --git a/src/mainboard/google/guybrush/romstage.c b/src/mainboard/google/guybrush/romstage.c index 0b7649b..571eb44 100644 --- a/src/mainboard/google/guybrush/romstage.c +++ b/src/mainboard/google/guybrush/romstage.c @@ -8,9 +8,9 @@ size_t base_num_gpios, override_num_gpios; const struct soc_amd_gpio *base_gpios, *override_gpios; - /* Initialize PCIe reset. */ - base_gpios = baseboard_pcie_gpio_table(&base_num_gpios); - override_gpios = variant_pcie_override_gpio_table(&override_num_gpios); + /* Initialize PCIe reset and other romstage GPIOs */ + base_gpios = baseboard_romstage_gpio_table(&base_num_gpios); + override_gpios = variant_romstage_override_gpio_table(&override_num_gpios); gpio_configure_pads_with_override(base_gpios, base_num_gpios, override_gpios, override_num_gpios); diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 1ee70da..beb654f 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -268,7 +268,7 @@ }; /* PCIE_RST needs to be brought high before FSP-M runs */ -static const struct soc_amd_gpio pcie_gpio_table[] = { +static const struct soc_amd_gpio romstage_gpio_table[] = { /* Deassert all AUX_RESET lines & PCIE_RST */ /* Unused */ PAD_NC(GPIO_5), @@ -286,10 +286,10 @@ PAD_NFO(GPIO_26, PCIE_RST_L, HIGH), }; -const struct soc_amd_gpio *baseboard_pcie_gpio_table(size_t *size) +const struct soc_amd_gpio *baseboard_romstage_gpio_table(size_t *size) { - *size = ARRAY_SIZE(pcie_gpio_table); - return pcie_gpio_table; + *size = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; } const struct soc_amd_gpio *__weak variant_bootblock_gpio_table(size_t *size) @@ -322,7 +322,7 @@ return NULL; } -const struct soc_amd_gpio * __weak variant_pcie_override_gpio_table(size_t *size) +const struct soc_amd_gpio * __weak variant_romstage_override_gpio_table(size_t *size) { *size = 0; return NULL; diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index 9a57c41..24c03b0 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -21,7 +21,7 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size); const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size); const struct soc_amd_gpio *variant_bootblock_override_gpio_table(size_t *size); -const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size); +const struct soc_amd_gpio *variant_romstage_override_gpio_table(size_t *size); /* This function provides early GPIO init in early bootblock or psp. */ const struct soc_amd_gpio *variant_early_gpio_table(size_t *size); @@ -30,7 +30,7 @@ const struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size); /* This function provides GPIO settings before PCIe enumeration. */ -const struct soc_amd_gpio *baseboard_pcie_gpio_table(size_t *size); +const struct soc_amd_gpio *baseboard_romstage_gpio_table(size_t *size); /* This function provides GPIO settings for eSPI bus. */ const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size); diff --git a/src/mainboard/google/guybrush/variants/dewatt/gpio.c b/src/mainboard/google/guybrush/variants/dewatt/gpio.c index 10486351..571cbb4 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/gpio.c +++ b/src/mainboard/google/guybrush/variants/dewatt/gpio.c @@ -53,7 +53,7 @@ }; /* This table is used by guybrush variant */ -static const struct soc_amd_gpio override_pcie_gpio_table[] = { +static const struct soc_amd_gpio override_romstage_gpio_table[] = { /* Unused TP195*/ PAD_NC(GPIO_18), /* Unused TP217*/ @@ -78,10 +78,10 @@ return override_early_gpio_table; } -const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size) +const struct soc_amd_gpio *variant_romstage_override_gpio_table(size_t *size) { - *size = ARRAY_SIZE(override_pcie_gpio_table); - return override_pcie_gpio_table; + *size = ARRAY_SIZE(override_romstage_gpio_table); + return override_romstage_gpio_table; } const struct soc_amd_gpio *variant_bootblock_override_gpio_table(size_t *size) diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c index f3ed09f..dcbda20 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c +++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c @@ -48,7 +48,7 @@ }; /* This table is used by guybrush variant with board version < 2. */ -static const struct soc_amd_gpio bid1_pcie_gpio_table[] = { +static const struct soc_amd_gpio bid1_romstage_gpio_table[] = { /* SD_AUX_RESET_L */ PAD_GPO(GPIO_70, HIGH), }; @@ -87,13 +87,13 @@ return override_early_gpio_table; } -const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size) +const struct soc_amd_gpio *variant_romstage_override_gpio_table(size_t *size) { uint32_t board_version = board_id(); *size = 0; if (board_version < 2) { - *size = ARRAY_SIZE(bid1_pcie_gpio_table); - return bid1_pcie_gpio_table; + *size = ARRAY_SIZE(bid1_romstage_gpio_table); + return bid1_romstage_gpio_table; } return NULL; diff --git a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c index 0fdedbf..c9f637c 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c @@ -47,7 +47,7 @@ PAD_GPO(GPIO_31, LOW), }; -static const struct soc_amd_gpio override_pcie_gpio_table[] = { +static const struct soc_amd_gpio override_romstage_gpio_table[] = { PAD_NC(GPIO_18), }; @@ -91,10 +91,10 @@ return override_early_gpio_table; } -const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size) +const struct soc_amd_gpio *variant_romstage_override_gpio_table(size_t *size) { - *size = ARRAY_SIZE(override_pcie_gpio_table); - return override_pcie_gpio_table; + *size = ARRAY_SIZE(override_romstage_gpio_table); + return override_romstage_gpio_table; } const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) -- To view, visit https://review.coreboot.org/c/coreboot/+/69177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72e7febfb532262be7e4c14bf136e0d69c91301e Gerrit-Change-Number: 69177 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/guybrush: rename baseboard GPIO table getter for clarity
by Matt DeVillier (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Jason Nien, Martin Roth. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69176 ) Change subject: mb/google/guybrush: rename baseboard GPIO table getter for clarity ...................................................................... mb/google/guybrush: rename baseboard GPIO table getter for clarity Rename variant_pcie_gpio_table() to baseboard_pcie_gpio_table(), since the GPIO table comes from the baseboard and is overridden by a separate table from the variant. Drop the __weak qualifier as this function is not overridden. This is similar to the change made for skyrim in CB:67809 Change-Id: I14c79fad04f18d874ce6ff7e572bb237445db8b1 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/mainboard/google/guybrush/romstage.c M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h 3 files changed, 21 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/69176/1 diff --git a/src/mainboard/google/guybrush/romstage.c b/src/mainboard/google/guybrush/romstage.c index 23e7853..0b7649b 100644 --- a/src/mainboard/google/guybrush/romstage.c +++ b/src/mainboard/google/guybrush/romstage.c @@ -9,7 +9,7 @@ const struct soc_amd_gpio *base_gpios, *override_gpios; /* Initialize PCIe reset. */ - base_gpios = variant_pcie_gpio_table(&base_num_gpios); + base_gpios = baseboard_pcie_gpio_table(&base_num_gpios); override_gpios = variant_pcie_override_gpio_table(&override_num_gpios); gpio_configure_pads_with_override(base_gpios, base_num_gpios, diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 8554c4c..1ee70da 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -286,7 +286,7 @@ PAD_NFO(GPIO_26, PCIE_RST_L, HIGH), }; -const struct soc_amd_gpio *__weak variant_pcie_gpio_table(size_t *size) +const struct soc_amd_gpio *baseboard_pcie_gpio_table(size_t *size) { *size = ARRAY_SIZE(pcie_gpio_table); return pcie_gpio_table; diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index bf69443..9a57c41 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -30,7 +30,7 @@ const struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size); /* This function provides GPIO settings before PCIe enumeration. */ -const struct soc_amd_gpio *variant_pcie_gpio_table(size_t *size); +const struct soc_amd_gpio *baseboard_pcie_gpio_table(size_t *size); /* This function provides GPIO settings for eSPI bus. */ const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size); -- To view, visit https://review.coreboot.org/c/coreboot/+/69176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14c79fad04f18d874ce6ff7e572bb237445db8b1 Gerrit-Change-Number: 69176 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: Documentation/drivers: Update section on touchscreen runtime detection
by Matt DeVillier (Code Review) 03 Nov '22

03 Nov '22

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69175 to look at the new patch set (#2). Change subject: Documentation/drivers: Update section on touchscreen runtime detection ...................................................................... Documentation/drivers: Update section on touchscreen runtime detection Update section now that google/skyrim and google/guybrush implement power sequencing and touchscreen runtime detection. Change-Id: Ida63bebf18575d6856edfc65965ff82a4072df87 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M Documentation/drivers/dt_entries.md 1 file changed, 17 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/69175/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida63bebf18575d6856edfc65965ff82a4072df87 Gerrit-Change-Number: 69175 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd/common/block/spi: Mainboard to override SPI Read Mode
by Jon Murphy (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Martin Roth, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68946 ) Change subject: soc/amd/common/block/spi: Mainboard to override SPI Read Mode ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68946/comment/74c6810b_38a575b7 PS1, Line 15: BUG=b:225213679 This bug was marked dupe, and the one that it's a dupe of was marked won't fix infeasible, is this really the right bug? File src/mainboard/google/guybrush/spi_speeds.c: https://review.coreboot.org/c/coreboot/+/68946/comment/03b02890_8dc48def PS1, Line 7: void mainboard_spi_cfg_override(uint8_t *fast_speed, uint8_t *read_mode) Rename variable speed? It's no longer solely the fast speed -- To view, visit https://review.coreboot.org/c/coreboot/+/68946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I160b56f6201a798ce59e977ca40301e23ab63805 Gerrit-Change-Number: 68946 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Nov 2022 21:34:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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